1 /* $NetBSD: pci_6600.c,v 1.29 2020/09/26 21:07:48 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 by Ross Harvey. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Ross Harvey. 17 * 4. The name of Ross Harvey may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS 21 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE 23 * ARE DISCLAIMED. IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY 24 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34 #include <sys/cdefs.h> 35 36 __KERNEL_RCSID(0, "$NetBSD: pci_6600.c,v 1.29 2020/09/26 21:07:48 thorpej Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 #include <sys/cpu.h> 44 45 #include <machine/autoconf.h> 46 #define _ALPHA_BUS_DMA_PRIVATE 47 #include <sys/bus.h> 48 #include <machine/rpb.h> 49 #include <machine/alpha.h> 50 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pciidereg.h> 54 #include <dev/pci/pciidevar.h> 55 56 #include <alpha/pci/tsreg.h> 57 #include <alpha/pci/tsvar.h> 58 #include <alpha/pci/pci_6600.h> 59 60 #define pci_6600() { Generate ctags(1) key. } 61 62 #include "sio.h" 63 #if NSIO 64 #include <alpha/pci/siovar.h> 65 #endif 66 67 #define PCI_NIRQ 64 68 #define PCI_SIO_IRQ 55 69 #define PCI_STRAY_MAX 5 70 71 /* 72 * Some Tsunami models have a PCI device (the USB controller) with interrupts 73 * tied to ISA IRQ lines. The IRQ is encoded as: 74 * 75 * line = 0xe0 | isa_irq; 76 */ 77 #define DEC_6600_LINE_IS_ISA(line) ((line) >= 0xe0 && (line) <= 0xef) 78 #define DEC_6600_LINE_ISA_IRQ(line) ((line) & 0x0f) 79 80 static struct tsp_config *sioprimary; 81 82 static void dec_6600_intr_disestablish(pci_chipset_tag_t, void *); 83 static void *dec_6600_intr_establish(pci_chipset_tag_t, pci_intr_handle_t, 84 int, int (*func)(void *), void *); 85 static const char *dec_6600_intr_string(pci_chipset_tag_t, pci_intr_handle_t, 86 char *, size_t); 87 static const struct evcnt *dec_6600_intr_evcnt(pci_chipset_tag_t, 88 pci_intr_handle_t); 89 static int dec_6600_intr_map(const struct pci_attach_args *, 90 pci_intr_handle_t *); 91 92 static void *dec_6600_pciide_compat_intr_establish(device_t, 93 const struct pci_attach_args *, int, 94 int (*)(void *), void *); 95 96 static void dec_6600_intr_enable(pci_chipset_tag_t, int irq); 97 static void dec_6600_intr_disable(pci_chipset_tag_t, int irq); 98 static void dec_6600_intr_set_affinity(pci_chipset_tag_t, int, 99 struct cpu_info *); 100 101 static void dec_6600_intr_redistribute(void); 102 103 /* 104 * We keep 2 software copies of the interrupt enables: one global one, 105 * and one per-CPU for setting the interrupt affinity. 106 */ 107 static uint64_t dec_6600_intr_enables __read_mostly; 108 static uint64_t dec_6600_cpu_intr_enables[4] __read_mostly; 109 110 void 111 pci_6600_pickintr(struct tsp_config *pcp) 112 { 113 bus_space_tag_t iot = &pcp->pc_iot; 114 pci_chipset_tag_t pc = &pcp->pc_pc; 115 char *cp; 116 int i; 117 struct cpu_info *ci; 118 CPU_INFO_ITERATOR cii; 119 120 pc->pc_intr_v = pcp; 121 pc->pc_intr_map = dec_6600_intr_map; 122 pc->pc_intr_string = dec_6600_intr_string; 123 pc->pc_intr_evcnt = dec_6600_intr_evcnt; 124 pc->pc_intr_establish = dec_6600_intr_establish; 125 pc->pc_intr_disestablish = dec_6600_intr_disestablish; 126 127 pc->pc_pciide_compat_intr_establish = NULL; 128 129 pc->pc_intr_desc = "dec 6600 irq"; 130 pc->pc_vecbase = 0x900; 131 pc->pc_nirq = PCI_NIRQ; 132 133 pc->pc_intr_enable = dec_6600_intr_enable; 134 pc->pc_intr_disable = dec_6600_intr_disable; 135 pc->pc_intr_set_affinity = dec_6600_intr_set_affinity; 136 137 alpha_intr_redistribute = dec_6600_intr_redistribute; 138 139 /* Note eligible CPUs for interrupt routing purposes. */ 140 for (CPU_INFO_FOREACH(cii, ci)) { 141 KASSERT(ci->ci_cpuid < 4); 142 pc->pc_eligible_cpus |= __BIT(ci->ci_cpuid); 143 } 144 145 /* 146 * System-wide and Pchip-0-only logic... 147 */ 148 if (sioprimary == NULL) { 149 sioprimary = pcp; 150 /* 151 * Unless explicitly routed, all interrupts go to the 152 * primary CPU. 153 */ 154 dec_6600_cpu_intr_enables[cpu_info_primary.ci_cpuid] = 155 __BITS(0,63); 156 pc->pc_pciide_compat_intr_establish = 157 dec_6600_pciide_compat_intr_establish; 158 #define PCI_6600_IRQ_STR 8 159 pc->pc_shared_intrs = alpha_shared_intr_alloc(PCI_NIRQ, 160 PCI_6600_IRQ_STR); 161 for (i = 0; i < PCI_NIRQ; i++) { 162 alpha_shared_intr_set_maxstrays(pc->pc_shared_intrs, i, 163 PCI_STRAY_MAX); 164 alpha_shared_intr_set_private(pc->pc_shared_intrs, i, 165 sioprimary); 166 167 cp = alpha_shared_intr_string(pc->pc_shared_intrs, i); 168 snprintf(cp, PCI_6600_IRQ_STR, "irq %d", i); 169 evcnt_attach_dynamic(alpha_shared_intr_evcnt( 170 pc->pc_shared_intrs, i), EVCNT_TYPE_INTR, NULL, 171 "dec 6600", cp); 172 } 173 #if NSIO 174 sio_intr_setup(pc, iot); 175 176 mutex_enter(&cpu_lock); 177 dec_6600_intr_enable(pc, PCI_SIO_IRQ); 178 mutex_exit(&cpu_lock); 179 #endif 180 } else { 181 pc->pc_shared_intrs = sioprimary->pc_pc.pc_shared_intrs; 182 } 183 } 184 185 static int 186 dec_6600_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 187 { 188 pcitag_t bustag = pa->pa_intrtag; 189 int buspin = pa->pa_intrpin, line = pa->pa_intrline; 190 pci_chipset_tag_t pc = pa->pa_pc; 191 int bus, device, function; 192 193 if (buspin == 0) { 194 /* No IRQ used. */ 195 return 1; 196 } 197 if (buspin < 0 || buspin > 4) { 198 printf("intr_map: bad interrupt pin %d\n", buspin); 199 return 1; 200 } 201 202 pci_decompose_tag(pc, bustag, &bus, &device, &function); 203 204 /* 205 * The console places the interrupt mapping in the "line" value. 206 * A value of (char)-1 indicates there is no mapping. 207 */ 208 if (line == 0xff) { 209 printf("dec_6600_intr_map: no mapping for %d/%d/%d\n", 210 bus, device, function); 211 return (1); 212 } 213 214 #if NSIO == 0 215 if (DEC_6600_LINE_IS_ISA(line)) { 216 printf("dec_6600_intr_map: ISA IRQ %d for %d/%d/%d\n", 217 DEC_6600_LINE_ISA_IRQ(line), bus, device, function); 218 return (1); 219 } 220 #endif 221 222 if (DEC_6600_LINE_IS_ISA(line) == 0 && line >= PCI_NIRQ) 223 panic("dec_6600_intr_map: dec 6600 irq too large (%d)", 224 line); 225 226 alpha_pci_intr_handle_init(ihp, line, 0); 227 return (0); 228 } 229 230 static const char * 231 dec_6600_intr_string(pci_chipset_tag_t const pc, pci_intr_handle_t const ih, 232 char * const buf, size_t const len) 233 { 234 #if NSIO 235 const u_int irq = alpha_pci_intr_handle_get_irq(&ih); 236 237 if (DEC_6600_LINE_IS_ISA(irq)) 238 return (sio_intr_string(NULL /*XXX*/, 239 DEC_6600_LINE_ISA_IRQ(irq), buf, len)); 240 #endif 241 242 return alpha_pci_generic_intr_string(pc, ih, buf, len); 243 } 244 245 static const struct evcnt * 246 dec_6600_intr_evcnt(pci_chipset_tag_t const pc, pci_intr_handle_t const ih) 247 { 248 #if NSIO 249 const u_int irq = alpha_pci_intr_handle_get_irq(&ih); 250 251 if (DEC_6600_LINE_IS_ISA(irq)) 252 return (sio_intr_evcnt(NULL /*XXX*/, 253 DEC_6600_LINE_ISA_IRQ(irq))); 254 #endif 255 256 return alpha_pci_generic_intr_evcnt(pc, ih); 257 } 258 259 static void * 260 dec_6600_intr_establish(pci_chipset_tag_t const pc, pci_intr_handle_t const ih, 261 int const level, int (*func)(void *), void *arg) 262 { 263 #if NSIO 264 const u_int irq = alpha_pci_intr_handle_get_irq(&ih); 265 const u_int flags = alpha_pci_intr_handle_get_flags(&ih); 266 267 if (DEC_6600_LINE_IS_ISA(irq)) 268 return (sio_intr_establish(NULL /*XXX*/, 269 DEC_6600_LINE_ISA_IRQ(irq), IST_LEVEL, level, flags, 270 func, arg)); 271 #endif 272 273 return alpha_pci_generic_intr_establish(pc, ih, level, func, arg); 274 } 275 276 static void 277 dec_6600_intr_disestablish(pci_chipset_tag_t const pc, void * const cookie) 278 { 279 #if NSIO 280 struct alpha_shared_intrhand * const ih = cookie; 281 282 /* 283 * We have to determine if this is an ISA IRQ or not! We do this 284 * by checking to see if the intrhand points back to an intrhead 285 * that points to the sioprimary TSP. If not, it's an ISA IRQ. 286 * Pretty disgusting, eh? 287 */ 288 if (ih->ih_intrhead->intr_private != sioprimary) { 289 sio_intr_disestablish(NULL /*XXX*/, cookie); 290 return; 291 } 292 #endif 293 294 return alpha_pci_generic_intr_disestablish(pc, cookie); 295 } 296 297 static void 298 dec_6600_intr_program(pci_chipset_tag_t const pc) 299 { 300 unsigned int irq, cpuno, cnt; 301 302 /* 303 * Validate the configuration before we program it: each enabled 304 * IRQ must be routed to exactly one CPU. 305 */ 306 for (irq = 0; irq < PCI_NIRQ; irq++) { 307 if ((dec_6600_intr_enables & __BIT(irq)) == 0) 308 continue; 309 for (cpuno = 0, cnt = 0; cpuno < 4; cpuno++) { 310 if (dec_6600_cpu_intr_enables[cpuno] != 0 && 311 (pc->pc_eligible_cpus & __BIT(cpuno)) == 0) 312 panic("%s: interrupts enabled on non-existent CPU %u", 313 __func__, cpuno); 314 if (dec_6600_cpu_intr_enables[cpuno] & __BIT(irq)) 315 cnt++; 316 } 317 if (cnt != 1) { 318 panic("%s: irq %u enabled on %u CPUs", __func__, 319 irq, cnt); 320 } 321 } 322 323 const uint64_t enab0 = 324 dec_6600_intr_enables & dec_6600_cpu_intr_enables[0]; 325 const uint64_t enab1 = 326 dec_6600_intr_enables & dec_6600_cpu_intr_enables[1]; 327 const uint64_t enab2 = 328 dec_6600_intr_enables & dec_6600_cpu_intr_enables[2]; 329 const uint64_t enab3 = 330 dec_6600_intr_enables & dec_6600_cpu_intr_enables[3]; 331 332 /* Don't touch DIMx registers for non-existent CPUs. */ 333 uint64_t black_hole; 334 volatile uint64_t * const dim0 = (pc->pc_eligible_cpus & __BIT(0)) ? 335 (void *)ALPHA_PHYS_TO_K0SEG(TS_C_DIM0) : &black_hole; 336 volatile uint64_t * const dim1 = (pc->pc_eligible_cpus & __BIT(1)) ? 337 (void *)ALPHA_PHYS_TO_K0SEG(TS_C_DIM1) : &black_hole; 338 volatile uint64_t * const dim2 = (pc->pc_eligible_cpus & __BIT(2)) ? 339 (void *)ALPHA_PHYS_TO_K0SEG(TS_C_DIM2) : &black_hole; 340 volatile uint64_t * const dim3 = (pc->pc_eligible_cpus & __BIT(3)) ? 341 (void *)ALPHA_PHYS_TO_K0SEG(TS_C_DIM3) : &black_hole; 342 343 const unsigned long psl = alpha_pal_swpipl(ALPHA_PSL_IPL_HIGH); 344 345 alpha_mb(); 346 *dim0 = enab0; 347 *dim1 = enab1; 348 *dim2 = enab2; 349 *dim3 = enab3; 350 alpha_mb(); 351 (void) *dim0; 352 (void) *dim1; 353 (void) *dim2; 354 (void) *dim3; 355 alpha_mb(); 356 357 alpha_pal_swpipl(psl); 358 } 359 360 static void 361 dec_6600_intr_enable(pci_chipset_tag_t const pc, int const irq) 362 { 363 364 KASSERT(mutex_owned(&cpu_lock)); 365 366 dec_6600_intr_enables |= __BIT(irq); 367 dec_6600_intr_program(pc); 368 } 369 370 static void 371 dec_6600_intr_disable(pci_chipset_tag_t const pc, int const irq) 372 { 373 374 KASSERT(mutex_owned(&cpu_lock)); 375 376 dec_6600_intr_enables &= ~__BIT(irq); 377 dec_6600_intr_program(pc); 378 } 379 380 static void 381 dec_6600_intr_set_affinity(pci_chipset_tag_t const pc, int const irq, 382 struct cpu_info * const ci) 383 { 384 const uint64_t intr_bit = __BIT(irq); 385 cpuid_t cpuno; 386 387 KASSERT(mutex_owned(&cpu_lock)); 388 KASSERT(ci->ci_cpuid < 4); 389 KASSERT(pc->pc_eligible_cpus & __BIT(ci->ci_cpuid)); 390 391 for (cpuno = 0; cpuno < 4; cpuno++) { 392 if (cpuno == ci->ci_cpuid) 393 dec_6600_cpu_intr_enables[cpuno] |= intr_bit; 394 else 395 dec_6600_cpu_intr_enables[cpuno] &= ~intr_bit; 396 } 397 398 /* Only program the hardware if the irq is enabled. */ 399 if (dec_6600_intr_enables & intr_bit) 400 dec_6600_intr_program(pc); 401 } 402 403 static void 404 dec_6600_intr_redistribute(void) 405 { 406 KASSERT(sioprimary != NULL); 407 408 pci_chipset_tag_t const pc = &sioprimary->pc_pc; 409 410 /* ISA interrupts always stay on primary. Shuffle PCI interrupts. */ 411 alpha_pci_generic_intr_redistribute(pc); 412 } 413 414 static void * 415 dec_6600_pciide_compat_intr_establish(device_t dev, 416 const struct pci_attach_args *pa, int chan, int (*func)(void *), void *arg) 417 { 418 pci_chipset_tag_t const pc = pa->pa_pc; 419 420 /* 421 * If this isn't the TSP that holds the PCI-ISA bridge, 422 * all bets are off. 423 */ 424 if (pc->pc_intr_v != sioprimary) 425 return (NULL); 426 427 return sio_pciide_compat_intr_establish(dev, pa, chan, func, arg); 428 } 429