1 /* $NetBSD: pci_6600.c,v 1.18 2009/03/14 21:04:02 dsl Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 by Ross Harvey. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Ross Harvey. 17 * 4. The name of Ross Harvey may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS 21 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE 23 * ARE DISCLAIMED. IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY 24 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34 #include <sys/cdefs.h> 35 36 __KERNEL_RCSID(0, "$NetBSD: pci_6600.c,v 1.18 2009/03/14 21:04:02 dsl Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 44 #include <uvm/uvm_extern.h> 45 46 #include <machine/autoconf.h> 47 #define _ALPHA_BUS_DMA_PRIVATE 48 #include <machine/bus.h> 49 #include <machine/rpb.h> 50 #include <machine/alpha.h> 51 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pciidereg.h> 55 #include <dev/pci/pciidevar.h> 56 57 #include <alpha/pci/tsreg.h> 58 #include <alpha/pci/tsvar.h> 59 #include <alpha/pci/pci_6600.h> 60 61 #define pci_6600() { Generate ctags(1) key. } 62 63 #include "sio.h" 64 #if NSIO 65 #include <alpha/pci/siovar.h> 66 #endif 67 68 #define PCI_NIRQ 64 69 #define PCI_STRAY_MAX 5 70 71 /* 72 * Some Tsunami models have a PCI device (the USB controller) with interrupts 73 * tied to ISA IRQ lines. The IRQ is encoded as: 74 * 75 * line = 0xe0 | isa_irq; 76 */ 77 #define DEC_6600_LINE_IS_ISA(line) ((line) >= 0xe0 && (line) <= 0xef) 78 #define DEC_6600_LINE_ISA_IRQ(line) ((line) & 0x0f) 79 80 static const char *irqtype = "6600 irq"; 81 static struct tsp_config *sioprimary; 82 83 void dec_6600_intr_disestablish(void *, void *); 84 void *dec_6600_intr_establish( 85 void *, pci_intr_handle_t, int, int (*func)(void *), void *); 86 const char *dec_6600_intr_string(void *, pci_intr_handle_t); 87 const struct evcnt *dec_6600_intr_evcnt(void *, pci_intr_handle_t); 88 int dec_6600_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 89 void *dec_6600_pciide_compat_intr_establish(void *, struct device *, 90 struct pci_attach_args *, int, int (*)(void *), void *); 91 92 struct alpha_shared_intr *dec_6600_pci_intr; 93 94 void dec_6600_iointr(void *arg, unsigned long vec); 95 extern void dec_6600_intr_enable(int irq); 96 extern void dec_6600_intr_disable(int irq); 97 98 void 99 pci_6600_pickintr(struct tsp_config *pcp) 100 { 101 bus_space_tag_t iot = &pcp->pc_iot; 102 pci_chipset_tag_t pc = &pcp->pc_pc; 103 char *cp; 104 int i; 105 106 pc->pc_intr_v = pcp; 107 pc->pc_intr_map = dec_6600_intr_map; 108 pc->pc_intr_string = dec_6600_intr_string; 109 pc->pc_intr_evcnt = dec_6600_intr_evcnt; 110 pc->pc_intr_establish = dec_6600_intr_establish; 111 pc->pc_intr_disestablish = dec_6600_intr_disestablish; 112 pc->pc_pciide_compat_intr_establish = NULL; 113 114 /* 115 * System-wide and Pchip-0-only logic... 116 */ 117 if (dec_6600_pci_intr == NULL) { 118 sioprimary = pcp; 119 pc->pc_pciide_compat_intr_establish = 120 dec_6600_pciide_compat_intr_establish; 121 dec_6600_pci_intr = alpha_shared_intr_alloc(PCI_NIRQ, 8); 122 for (i = 0; i < PCI_NIRQ; i++) { 123 alpha_shared_intr_set_maxstrays(dec_6600_pci_intr, i, 124 PCI_STRAY_MAX); 125 alpha_shared_intr_set_private(dec_6600_pci_intr, i, 126 sioprimary); 127 128 cp = alpha_shared_intr_string(dec_6600_pci_intr, i); 129 sprintf(cp, "irq %d", i); 130 evcnt_attach_dynamic(alpha_shared_intr_evcnt( 131 dec_6600_pci_intr, i), EVCNT_TYPE_INTR, NULL, 132 "dec_6600", cp); 133 } 134 #if NSIO 135 sio_intr_setup(pc, iot); 136 dec_6600_intr_enable(55); /* irq line for sio */ 137 #endif 138 } 139 } 140 141 int 142 dec_6600_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 143 { 144 pcitag_t bustag = pa->pa_intrtag; 145 int buspin = pa->pa_intrpin, line = pa->pa_intrline; 146 pci_chipset_tag_t pc = pa->pa_pc; 147 int bus, device, function; 148 149 if (buspin == 0) { 150 /* No IRQ used. */ 151 return 1; 152 } 153 if (buspin > 4) { 154 printf("intr_map: bad interrupt pin %d\n", buspin); 155 return 1; 156 } 157 158 pci_decompose_tag(pc, bustag, &bus, &device, &function); 159 160 /* 161 * The console places the interrupt mapping in the "line" value. 162 * A value of (char)-1 indicates there is no mapping. 163 */ 164 if (line == 0xff) { 165 printf("dec_6600_intr_map: no mapping for %d/%d/%d\n", 166 bus, device, function); 167 return (1); 168 } 169 170 #if NSIO == 0 171 if (DEC_6600_LINE_IS_ISA(line)) { 172 printf("dec_6600_intr_map: ISA IRQ %d for %d/%d/%d\n", 173 DEC_6600_LINE_ISA_IRQ(line), bus, device, function); 174 return (1); 175 } 176 #endif 177 178 if (DEC_6600_LINE_IS_ISA(line) == 0 && line >= PCI_NIRQ) 179 panic("dec_6600_intr_map: dec 6600 irq too large (%d)", 180 line); 181 182 *ihp = line; 183 return (0); 184 } 185 186 const char * 187 dec_6600_intr_string(void *acv, pci_intr_handle_t ih) 188 { 189 190 static const char irqfmt[] = "dec 6600 irq %ld"; 191 static char irqstr[sizeof irqfmt]; 192 193 #if NSIO 194 if (DEC_6600_LINE_IS_ISA(ih)) 195 return (sio_intr_string(NULL /*XXX*/, 196 DEC_6600_LINE_ISA_IRQ(ih))); 197 #endif 198 199 snprintf(irqstr, sizeof irqstr, irqfmt, ih); 200 return (irqstr); 201 } 202 203 const struct evcnt * 204 dec_6600_intr_evcnt(void *acv, pci_intr_handle_t ih) 205 { 206 207 #if NSIO 208 if (DEC_6600_LINE_IS_ISA(ih)) 209 return (sio_intr_evcnt(NULL /*XXX*/, 210 DEC_6600_LINE_ISA_IRQ(ih))); 211 #endif 212 213 return (alpha_shared_intr_evcnt(dec_6600_pci_intr, ih)); 214 } 215 216 void * 217 dec_6600_intr_establish(acv, ih, level, func, arg) 218 void *acv, *arg; 219 pci_intr_handle_t ih; 220 int level; 221 int (*func)(void *); 222 { 223 void *cookie; 224 225 #if NSIO 226 if (DEC_6600_LINE_IS_ISA(ih)) 227 return (sio_intr_establish(NULL /*XXX*/, 228 DEC_6600_LINE_ISA_IRQ(ih), IST_LEVEL, level, func, arg)); 229 #endif 230 231 if (ih >= PCI_NIRQ) 232 panic("dec_6600_intr_establish: bogus dec 6600 IRQ 0x%lx", 233 ih); 234 235 cookie = alpha_shared_intr_establish(dec_6600_pci_intr, ih, IST_LEVEL, 236 level, func, arg, irqtype); 237 238 if (cookie != NULL && 239 alpha_shared_intr_firstactive(dec_6600_pci_intr, ih)) { 240 scb_set(0x900 + SCB_IDXTOVEC(ih), dec_6600_iointr, NULL, 241 level); 242 dec_6600_intr_enable(ih); 243 } 244 return (cookie); 245 } 246 247 void 248 dec_6600_intr_disestablish(void *acv, void *cookie) 249 { 250 struct alpha_shared_intrhand *ih = cookie; 251 unsigned int irq = ih->ih_num; 252 int s; 253 254 #if NSIO 255 /* 256 * We have to determine if this is an ISA IRQ or not! We do this 257 * by checking to see if the intrhand points back to an intrhead 258 * that points to the sioprimary TSP. If not, it's an ISA IRQ. 259 * Pretty disgusting, eh? 260 */ 261 if (ih->ih_intrhead->intr_private != sioprimary) { 262 sio_intr_disestablish(NULL /*XXX*/, cookie); 263 return; 264 } 265 #endif 266 267 s = splhigh(); 268 269 alpha_shared_intr_disestablish(dec_6600_pci_intr, cookie, irqtype); 270 if (alpha_shared_intr_isactive(dec_6600_pci_intr, irq) == 0) { 271 dec_6600_intr_disable(irq); 272 alpha_shared_intr_set_dfltsharetype(dec_6600_pci_intr, irq, 273 IST_NONE); 274 scb_free(0x900 + SCB_IDXTOVEC(irq)); 275 } 276 277 splx(s); 278 } 279 280 void 281 dec_6600_iointr(void *arg, unsigned long vec) 282 { 283 int irq; 284 285 irq = SCB_VECTOIDX(vec - 0x900); 286 287 if (irq >= PCI_NIRQ) 288 panic("iointr: irq %d is too high", irq); 289 290 if (!alpha_shared_intr_dispatch(dec_6600_pci_intr, irq)) { 291 alpha_shared_intr_stray(dec_6600_pci_intr, irq, 292 irqtype); 293 if (ALPHA_SHARED_INTR_DISABLE(dec_6600_pci_intr, irq)) 294 dec_6600_intr_disable(irq); 295 } else 296 alpha_shared_intr_reset_strays(dec_6600_pci_intr, irq); 297 } 298 299 void 300 dec_6600_intr_enable(int irq) 301 { 302 alpha_mb(); 303 STQP(TS_C_DIM0) |= 1UL << irq; 304 alpha_mb(); 305 } 306 307 void 308 dec_6600_intr_disable(int irq) 309 { 310 alpha_mb(); 311 STQP(TS_C_DIM0) &= ~(1UL << irq); 312 alpha_mb(); 313 } 314 315 void * 316 dec_6600_pciide_compat_intr_establish(v, dev, pa, chan, func, arg) 317 void *v; 318 struct device *dev; 319 struct pci_attach_args *pa; 320 int chan; 321 int (*func)(void *); 322 void *arg; 323 { 324 pci_chipset_tag_t pc = pa->pa_pc; 325 void *cookie = NULL; 326 int bus, irq; 327 328 pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL); 329 330 /* 331 * If this isn't PCI bus #0 on the TSP that holds the PCI-ISA 332 * bridge, all bets are off. 333 */ 334 if (bus != 0 || pc->pc_intr_v != sioprimary) 335 return (NULL); 336 337 irq = PCIIDE_COMPAT_IRQ(chan); 338 #if NSIO 339 cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO, 340 func, arg); 341 if (cookie == NULL) 342 return (NULL); 343 printf("%s: %s channel interrupting at %s\n", dev->dv_xname, 344 PCIIDE_CHANNEL_NAME(chan), sio_intr_string(NULL /*XXX*/, irq)); 345 #endif 346 return (cookie); 347 } 348