1 /* $NetBSD: pci_550.c,v 1.37 2014/03/21 16:39:29 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center, and by Andrew Gallatin. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 35 * All rights reserved. 36 * 37 * Author: Chris G. Demetriou 38 * 39 * Permission to use, copy, modify and distribute this software and 40 * its documentation is hereby granted, provided that both the copyright 41 * notice and this permission notice appear in all copies of the 42 * software, derivative works or modified versions, and any portions 43 * thereof, and that both notices appear in supporting documentation. 44 * 45 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 46 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 47 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 48 * 49 * Carnegie Mellon requests users of this software to return to 50 * 51 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 52 * School of Computer Science 53 * Carnegie Mellon University 54 * Pittsburgh PA 15213-3890 55 * 56 * any improvements or extensions that they make and grant Carnegie the 57 * rights to redistribute these changes. 58 */ 59 60 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 61 62 __KERNEL_RCSID(0, "$NetBSD: pci_550.c,v 1.37 2014/03/21 16:39:29 christos Exp $"); 63 64 #include <sys/types.h> 65 #include <sys/param.h> 66 #include <sys/time.h> 67 #include <sys/systm.h> 68 #include <sys/errno.h> 69 #include <sys/malloc.h> 70 #include <sys/device.h> 71 #include <sys/syslog.h> 72 73 #include <machine/autoconf.h> 74 #include <machine/rpb.h> 75 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pciidereg.h> 79 #include <dev/pci/pciidevar.h> 80 81 #include <alpha/pci/ciareg.h> 82 #include <alpha/pci/ciavar.h> 83 84 #include <alpha/pci/pci_550.h> 85 86 #include "sio.h" 87 #if NSIO 88 #include <alpha/pci/siovar.h> 89 #endif 90 91 int dec_550_intr_map(const struct pci_attach_args *, 92 pci_intr_handle_t *); 93 const char *dec_550_intr_string(void *, pci_intr_handle_t, char *, size_t); 94 const struct evcnt *dec_550_intr_evcnt(void *, pci_intr_handle_t); 95 void *dec_550_intr_establish(void *, pci_intr_handle_t, 96 int, int (*func)(void *), void *); 97 void dec_550_intr_disestablish(void *, void *); 98 99 void *dec_550_pciide_compat_intr_establish(void *, device_t, 100 const struct pci_attach_args *, int, int (*)(void *), void *); 101 102 #define DEC_550_PCI_IRQ_BEGIN 8 103 #define DEC_550_MAX_IRQ (64 - DEC_550_PCI_IRQ_BEGIN) 104 105 /* 106 * The Miata has a Pyxis, which seems to have problems with stray 107 * interrupts. Work around this by just ignoring strays. 108 */ 109 #define PCI_STRAY_MAX 0 110 111 /* 112 * Some Miata models, notably models with a Cypress PCI-ISA bridge, have 113 * a PCI device (the OHCI USB controller) with interrupts tied to ISA IRQ 114 * lines. This IRQ is encoded as: line = FLAG | isa_irq. Usually FLAG 115 * is 0xe0, however, it can be 0xf0. We don't allow 0xf0 | irq15. 116 */ 117 #define DEC_550_LINE_IS_ISA(line) ((line) >= 0xe0 && (line) <= 0xfe) 118 #define DEC_550_LINE_ISA_IRQ(line) ((line) & 0x0f) 119 120 struct alpha_shared_intr *dec_550_pci_intr; 121 122 void dec_550_iointr(void *arg, unsigned long vec); 123 void dec_550_intr_enable(int irq); 124 void dec_550_intr_disable(int irq); 125 126 void 127 pci_550_pickintr(struct cia_config *ccp) 128 { 129 bus_space_tag_t iot = &ccp->cc_iot; 130 pci_chipset_tag_t pc = &ccp->cc_pc; 131 char *cp; 132 int i; 133 134 pc->pc_intr_v = ccp; 135 pc->pc_intr_map = dec_550_intr_map; 136 pc->pc_intr_string = dec_550_intr_string; 137 pc->pc_intr_evcnt = dec_550_intr_evcnt; 138 pc->pc_intr_establish = dec_550_intr_establish; 139 pc->pc_intr_disestablish = dec_550_intr_disestablish; 140 141 pc->pc_pciide_compat_intr_establish = 142 dec_550_pciide_compat_intr_establish; 143 144 /* 145 * DEC 550's interrupts are enabled via the Pyxis interrupt 146 * mask register. Nothing to map. 147 */ 148 149 for (i = 0; i < DEC_550_MAX_IRQ; i++) 150 dec_550_intr_disable(i); 151 152 #define PCI_550_IRQ_STR 8 153 dec_550_pci_intr = alpha_shared_intr_alloc(DEC_550_MAX_IRQ, 154 PCI_550_IRQ_STR); 155 for (i = 0; i < DEC_550_MAX_IRQ; i++) { 156 alpha_shared_intr_set_maxstrays(dec_550_pci_intr, i, 157 PCI_STRAY_MAX); 158 alpha_shared_intr_set_private(dec_550_pci_intr, i, ccp); 159 160 cp = alpha_shared_intr_string(dec_550_pci_intr, i); 161 snprintf(cp, PCI_550_IRQ_STR, "irq %d", i); 162 evcnt_attach_dynamic(alpha_shared_intr_evcnt( 163 dec_550_pci_intr, i), EVCNT_TYPE_INTR, NULL, 164 "dec_550", cp); 165 } 166 167 #if NSIO 168 sio_intr_setup(pc, iot); 169 #endif 170 } 171 172 int 173 dec_550_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 174 { 175 pcitag_t bustag = pa->pa_intrtag; 176 int buspin = pa->pa_intrpin, line = pa->pa_intrline; 177 pci_chipset_tag_t pc = pa->pa_pc; 178 int bus, device, function; 179 180 if (buspin == 0) { 181 /* No IRQ used. */ 182 return 1; 183 } 184 if (buspin > 4) { 185 printf("dec_550_intr_map: bad interrupt pin %d\n", buspin); 186 return 1; 187 } 188 189 pci_decompose_tag(pc, bustag, &bus, &device, &function); 190 191 /* 192 * There are two main variants of Miata: Miata 1 (Intel SIO) 193 * and Miata {1.5,2} (Cypress). 194 * 195 * The Miata 1 has a CMD PCI IDE wired to compatibility mode at 196 * device 4 of bus 0. This variant apparently also has the 197 * Pyxis DMA bug. 198 * 199 * On the Miata 1.5 and Miata 2, the Cypress PCI-ISA bridge lives 200 * on device 7 of bus 0. This device has PCI IDE wired to 201 * compatibility mode on functions 1 and 2. 202 * 203 * There will be no interrupt mapping for these devices, so just 204 * bail out now. 205 */ 206 if (bus == 0) { 207 if ((hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) { 208 /* Miata 1 */ 209 if (device == 7) 210 panic("dec_550_intr_map: SIO device"); 211 else if (device == 4) 212 return (1); 213 } else { 214 /* Miata 1.5 or Miata 2 */ 215 if (device == 7) { 216 if (function == 0) 217 panic("dec_550_intr_map: SIO device"); 218 if (function == 1 || function == 2) 219 return (1); 220 } 221 } 222 } 223 224 /* 225 * The console places the interrupt mapping in the "line" value. 226 * A value of (char)-1 indicates there is no mapping. 227 */ 228 if (line == 0xff) { 229 printf("dec_550_intr_map: no mapping for %d/%d/%d\n", 230 bus, device, function); 231 return (1); 232 } 233 234 #if NSIO == 0 235 if (DEC_550_LINE_IS_ISA(line)) { 236 printf("dec_550_intr_map: ISA IRQ %d for %d/%d/%d\n", 237 DEC_550_LINE_ISA_IRQ(line), bus, device, function); 238 return (1); 239 } 240 #endif 241 242 if (DEC_550_LINE_IS_ISA(line) == 0 && line >= DEC_550_MAX_IRQ) { 243 printf("dec_550_intr_map: irq %d out of range %d/%d/%d\n", 244 line, bus, device, function); 245 return (1); 246 } 247 *ihp = line; 248 return (0); 249 } 250 251 const char * 252 dec_550_intr_string(void *ccv, pci_intr_handle_t ih, char *buf, size_t len) 253 { 254 #if 0 255 struct cia_config *ccp = ccv; 256 #endif 257 258 #if NSIO 259 if (DEC_550_LINE_IS_ISA(ih)) 260 return sio_intr_string(NULL /*XXX*/, 261 DEC_550_LINE_ISA_IRQ(ih), buf, len); 262 #endif 263 264 if (ih >= DEC_550_MAX_IRQ) 265 panic("%s: bogus 550 IRQ 0x%lx", __func__, ih); 266 snprintf(buf, len, "dec 550 irq %ld", ih); 267 return buf; 268 } 269 270 const struct evcnt * 271 dec_550_intr_evcnt(void *ccv, pci_intr_handle_t ih) 272 { 273 #if 0 274 struct cia_config *ccp = ccv; 275 #endif 276 277 #if NSIO 278 if (DEC_550_LINE_IS_ISA(ih)) 279 return (sio_intr_evcnt(NULL /*XXX*/, 280 DEC_550_LINE_ISA_IRQ(ih))); 281 #endif 282 283 if (ih >= DEC_550_MAX_IRQ) 284 panic("%s: bogus 550 IRQ 0x%lx", __func__, ih); 285 286 return (alpha_shared_intr_evcnt(dec_550_pci_intr, ih)); 287 } 288 289 void * 290 dec_550_intr_establish(void *ccv, pci_intr_handle_t ih, int level, int (*func)(void *), void *arg) 291 { 292 #if 0 293 struct cia_config *ccp = ccv; 294 #endif 295 void *cookie; 296 297 #if NSIO 298 if (DEC_550_LINE_IS_ISA(ih)) 299 return (sio_intr_establish(NULL /*XXX*/, 300 DEC_550_LINE_ISA_IRQ(ih), IST_LEVEL, level, func, arg)); 301 #endif 302 303 if (ih >= DEC_550_MAX_IRQ) 304 panic("dec_550_intr_establish: bogus dec 550 IRQ 0x%lx", ih); 305 306 cookie = alpha_shared_intr_establish(dec_550_pci_intr, ih, IST_LEVEL, 307 level, func, arg, "dec 550 irq"); 308 309 if (cookie != NULL && 310 alpha_shared_intr_firstactive(dec_550_pci_intr, ih)) { 311 scb_set(0x900 + SCB_IDXTOVEC(ih), dec_550_iointr, NULL, 312 level); 313 dec_550_intr_enable(ih); 314 } 315 return (cookie); 316 } 317 318 void 319 dec_550_intr_disestablish(void *ccv, void *cookie) 320 { 321 struct cia_config *ccp = ccv; 322 struct alpha_shared_intrhand *ih = cookie; 323 unsigned int irq = ih->ih_num; 324 int s; 325 326 #if NSIO 327 /* 328 * We have to determine if this is an ISA IRQ or not! We do this 329 * by checking to see if the intrhand points back to an intrhead 330 * that points to our cia_config. If not, it's an ISA IRQ. Pretty 331 * disgusting, eh? 332 */ 333 if (ih->ih_intrhead->intr_private != ccp) { 334 sio_intr_disestablish(NULL /*XXX*/, cookie); 335 return; 336 } 337 #endif 338 339 s = splhigh(); 340 341 alpha_shared_intr_disestablish(dec_550_pci_intr, cookie, 342 "dec 550 irq"); 343 if (alpha_shared_intr_isactive(dec_550_pci_intr, irq) == 0) { 344 dec_550_intr_disable(irq); 345 alpha_shared_intr_set_dfltsharetype(dec_550_pci_intr, irq, 346 IST_NONE); 347 scb_free(0x900 + SCB_IDXTOVEC(irq)); 348 } 349 350 splx(s); 351 } 352 353 void * 354 dec_550_pciide_compat_intr_establish(void *v, device_t dev, 355 const struct pci_attach_args *pa, int chan, int (*func)(void *), void *arg) 356 { 357 pci_chipset_tag_t pc = pa->pa_pc; 358 void *cookie = NULL; 359 int bus, irq; 360 char buf[64]; 361 362 pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL); 363 364 /* 365 * If this isn't PCI bus #0, all bets are off. 366 */ 367 if (bus != 0) 368 return (NULL); 369 370 irq = PCIIDE_COMPAT_IRQ(chan); 371 #if NSIO 372 cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO, 373 func, arg); 374 if (cookie == NULL) 375 return (NULL); 376 aprint_normal_dev(dev, "%s channel interrupting at %s\n", 377 PCIIDE_CHANNEL_NAME(chan), sio_intr_string(NULL /*XXX*/, irq, 378 buf, sizeof(buf))); 379 #endif 380 return (cookie); 381 } 382 383 void 384 dec_550_iointr(void *arg, unsigned long vec) 385 { 386 int irq; 387 388 irq = SCB_VECTOIDX(vec - 0x900); 389 390 if (irq >= DEC_550_MAX_IRQ) 391 panic("550_iointr: vec 0x%lx out of range", vec); 392 393 if (!alpha_shared_intr_dispatch(dec_550_pci_intr, irq)) { 394 alpha_shared_intr_stray(dec_550_pci_intr, irq, 395 "dec 550 irq"); 396 if (ALPHA_SHARED_INTR_DISABLE(dec_550_pci_intr, irq)) 397 dec_550_intr_disable(irq); 398 } else 399 alpha_shared_intr_reset_strays(dec_550_pci_intr, irq); 400 } 401 402 void 403 dec_550_intr_enable(int irq) 404 { 405 406 cia_pyxis_intr_enable(irq + DEC_550_PCI_IRQ_BEGIN, 1); 407 } 408 409 void 410 dec_550_intr_disable(int irq) 411 { 412 413 cia_pyxis_intr_enable(irq + DEC_550_PCI_IRQ_BEGIN, 0); 414 } 415