1 /* $NetBSD: pci_550.c,v 1.19 2000/12/28 22:59:07 sommerfeld Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center, and by Andrew Gallatin. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 68 69 __KERNEL_RCSID(0, "$NetBSD: pci_550.c,v 1.19 2000/12/28 22:59:07 sommerfeld Exp $"); 70 71 #include <sys/types.h> 72 #include <sys/param.h> 73 #include <sys/time.h> 74 #include <sys/systm.h> 75 #include <sys/errno.h> 76 #include <sys/malloc.h> 77 #include <sys/device.h> 78 #include <sys/syslog.h> 79 80 #include <uvm/uvm_extern.h> 81 82 #include <machine/autoconf.h> 83 #include <machine/rpb.h> 84 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcivar.h> 87 #include <dev/pci/pciidereg.h> 88 #include <dev/pci/pciidevar.h> 89 90 #include <alpha/pci/ciareg.h> 91 #include <alpha/pci/ciavar.h> 92 93 #include <alpha/pci/pci_550.h> 94 95 #include "sio.h" 96 #if NSIO 97 #include <alpha/pci/siovar.h> 98 #endif 99 100 int dec_550_intr_map __P((struct pci_attach_args *, 101 pci_intr_handle_t *)); 102 const char *dec_550_intr_string __P((void *, pci_intr_handle_t)); 103 const struct evcnt *dec_550_intr_evcnt __P((void *, pci_intr_handle_t)); 104 void *dec_550_intr_establish __P((void *, pci_intr_handle_t, 105 int, int (*func)(void *), void *)); 106 void dec_550_intr_disestablish __P((void *, void *)); 107 108 void *dec_550_pciide_compat_intr_establish __P((void *, struct device *, 109 struct pci_attach_args *, int, int (*)(void *), void *)); 110 111 #define DEC_550_PCI_IRQ_BEGIN 8 112 #define DEC_550_MAX_IRQ (64 - DEC_550_PCI_IRQ_BEGIN) 113 114 /* 115 * The Miata has a Pyxis, which seems to have problems with stray 116 * interrupts. Work around this by just ignoring strays. 117 */ 118 #define PCI_STRAY_MAX 0 119 120 /* 121 * Some Miata models, notably models with a Cypress PCI-ISA bridge, have 122 * a PCI device (the OHCI USB controller) with interrupts tied to ISA IRQ 123 * lines. This IRQ is encoded as: 124 * 125 * line = 0xe0 | isa_irq; 126 */ 127 #define DEC_550_LINE_IS_ISA(line) ((line) >= 0xe0 && (line) <= 0xef) 128 #define DEC_550_LINE_ISA_IRQ(line) ((line) & 0x0f) 129 130 struct alpha_shared_intr *dec_550_pci_intr; 131 132 void dec_550_iointr __P((void *framep, unsigned long vec)); 133 void dec_550_intr_enable __P((int irq)); 134 void dec_550_intr_disable __P((int irq)); 135 136 void 137 pci_550_pickintr(ccp) 138 struct cia_config *ccp; 139 { 140 bus_space_tag_t iot = &ccp->cc_iot; 141 pci_chipset_tag_t pc = &ccp->cc_pc; 142 char *cp; 143 int i; 144 145 pc->pc_intr_v = ccp; 146 pc->pc_intr_map = dec_550_intr_map; 147 pc->pc_intr_string = dec_550_intr_string; 148 pc->pc_intr_evcnt = dec_550_intr_evcnt; 149 pc->pc_intr_establish = dec_550_intr_establish; 150 pc->pc_intr_disestablish = dec_550_intr_disestablish; 151 152 pc->pc_pciide_compat_intr_establish = 153 dec_550_pciide_compat_intr_establish; 154 155 /* 156 * DEC 550's interrupts are enabled via the Pyxis interrupt 157 * mask register. Nothing to map. 158 */ 159 160 for (i = 0; i < DEC_550_MAX_IRQ; i++) 161 dec_550_intr_disable(i); 162 163 dec_550_pci_intr = alpha_shared_intr_alloc(DEC_550_MAX_IRQ, 8); 164 for (i = 0; i < DEC_550_MAX_IRQ; i++) { 165 alpha_shared_intr_set_maxstrays(dec_550_pci_intr, i, 166 PCI_STRAY_MAX); 167 alpha_shared_intr_set_private(dec_550_pci_intr, i, ccp); 168 169 cp = alpha_shared_intr_string(dec_550_pci_intr, i); 170 sprintf(cp, "irq %d", i); 171 evcnt_attach_dynamic(alpha_shared_intr_evcnt( 172 dec_550_pci_intr, i), EVCNT_TYPE_INTR, NULL, 173 "dec_550", cp); 174 } 175 176 #if NSIO 177 sio_intr_setup(pc, iot); 178 #endif 179 180 set_iointr(dec_550_iointr); 181 } 182 183 int 184 dec_550_intr_map(pa, ihp) 185 struct pci_attach_args *pa; 186 pci_intr_handle_t *ihp; 187 { 188 pcitag_t bustag = pa->pa_intrtag; 189 int buspin = pa->pa_intrpin, line = pa->pa_intrline; 190 pci_chipset_tag_t pc = pa->pa_pc; 191 int bus, device, function; 192 193 if (buspin == 0) { 194 /* No IRQ used. */ 195 return 1; 196 } 197 if (buspin > 4) { 198 printf("dec_550_intr_map: bad interrupt pin %d\n", buspin); 199 return 1; 200 } 201 202 alpha_pci_decompose_tag(pc, bustag, &bus, &device, &function); 203 204 /* 205 * There are two main variants of Miata: Miata 1 (Intel SIO) 206 * and Miata {1.5,2} (Cypress). 207 * 208 * The Miata 1 has a CMD PCI IDE wired to compatibility mode at 209 * device 4 of bus 0. This variant apparently also has the 210 * Pyxis DMA bug. 211 * 212 * On the Miata 1.5 and Miata 2, the Cypress PCI-ISA bridge lives 213 * on device 7 of bus 0. This device has PCI IDE wired to 214 * compatibility mode on functions 1 and 2. 215 * 216 * There will be no interrupt mapping for these devices, so just 217 * bail out now. 218 */ 219 if (bus == 0) { 220 if ((hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) { 221 /* Miata 1 */ 222 if (device == 7) 223 panic("dec_550_intr_map: SIO device"); 224 else if (device == 4) 225 return (1); 226 } else { 227 /* Miata 1.5 or Miata 2 */ 228 if (device == 7) { 229 if (function == 0) 230 panic("dec_550_intr_map: SIO device"); 231 if (function == 1 || function == 2) 232 return (1); 233 } 234 } 235 } 236 237 /* 238 * The console places the interrupt mapping in the "line" value. 239 * A value of (char)-1 indicates there is no mapping. 240 */ 241 if (line == 0xff) { 242 printf("dec_550_intr_map: no mapping for %d/%d/%d\n", 243 bus, device, function); 244 return (1); 245 } 246 247 #if NSIO == 0 248 if (DEC_550_LINE_IS_ISA(line)) { 249 printf("dec_550_intr_map: ISA IRQ %d for %d/%d/%d\n", 250 DEC_550_LINE_ISA_IRQ(line), bus, device, function); 251 return (1); 252 } 253 #endif 254 255 if (DEC_550_LINE_IS_ISA(line) == 0 && line >= DEC_550_MAX_IRQ) 256 panic("dec_550_intr_map: dec 550 irq too large (%d)\n", 257 line); 258 259 *ihp = line; 260 return (0); 261 } 262 263 const char * 264 dec_550_intr_string(ccv, ih) 265 void *ccv; 266 pci_intr_handle_t ih; 267 { 268 #if 0 269 struct cia_config *ccp = ccv; 270 #endif 271 static char irqstr[16]; /* 12 + 2 + NULL + sanity */ 272 273 #if NSIO 274 if (DEC_550_LINE_IS_ISA(ih)) 275 return (sio_intr_string(NULL /*XXX*/, 276 DEC_550_LINE_ISA_IRQ(ih))); 277 #endif 278 279 if (ih >= DEC_550_MAX_IRQ) 280 panic("dec_550_intr_string: bogus 550 IRQ 0x%lx\n", ih); 281 sprintf(irqstr, "dec 550 irq %ld", ih); 282 return (irqstr); 283 } 284 285 const struct evcnt * 286 dec_550_intr_evcnt(ccv, ih) 287 void *ccv; 288 pci_intr_handle_t ih; 289 { 290 #if 0 291 struct cia_config *ccp = ccv; 292 #endif 293 294 #if NSIO 295 if (DEC_550_LINE_IS_ISA(ih)) 296 return (sio_intr_evcnt(NULL /*XXX*/, 297 DEC_550_LINE_ISA_IRQ(ih))); 298 #endif 299 300 if (ih >= DEC_550_MAX_IRQ) 301 panic("dec_550_intr_evcnt: bogus 550 IRQ 0x%lx\n", ih); 302 303 return (alpha_shared_intr_evcnt(dec_550_pci_intr, ih)); 304 } 305 306 void * 307 dec_550_intr_establish(ccv, ih, level, func, arg) 308 void *ccv, *arg; 309 pci_intr_handle_t ih; 310 int level; 311 int (*func) __P((void *)); 312 { 313 #if 0 314 struct cia_config *ccp = ccv; 315 #endif 316 void *cookie; 317 318 #if NSIO 319 if (DEC_550_LINE_IS_ISA(ih)) 320 return (sio_intr_establish(NULL /*XXX*/, 321 DEC_550_LINE_ISA_IRQ(ih), IST_LEVEL, level, func, arg)); 322 #endif 323 324 if (ih >= DEC_550_MAX_IRQ) 325 panic("dec_550_intr_establish: bogus dec 550 IRQ 0x%lx\n", ih); 326 327 cookie = alpha_shared_intr_establish(dec_550_pci_intr, ih, IST_LEVEL, 328 level, func, arg, "dec 550 irq"); 329 330 if (cookie != NULL && alpha_shared_intr_isactive(dec_550_pci_intr, ih)) 331 dec_550_intr_enable(ih); 332 return (cookie); 333 } 334 335 void 336 dec_550_intr_disestablish(ccv, cookie) 337 void *ccv, *cookie; 338 { 339 struct cia_config *ccp = ccv; 340 struct alpha_shared_intrhand *ih = cookie; 341 unsigned int irq = ih->ih_num; 342 int s; 343 344 #if NSIO 345 /* 346 * We have to determine if this is an ISA IRQ or not! We do this 347 * by checking to see if the intrhand points back to an intrhead 348 * that points to our cia_config. If not, it's an ISA IRQ. Pretty 349 * disgusting, eh? 350 */ 351 if (ih->ih_intrhead->intr_private != ccp) { 352 sio_intr_disestablish(NULL /*XXX*/, cookie); 353 return; 354 } 355 #endif 356 357 s = splhigh(); 358 359 alpha_shared_intr_disestablish(dec_550_pci_intr, cookie, 360 "dec 550 irq"); 361 if (alpha_shared_intr_isactive(dec_550_pci_intr, irq) == 0) { 362 dec_550_intr_disable(irq); 363 alpha_shared_intr_set_dfltsharetype(dec_550_pci_intr, irq, 364 IST_NONE); 365 } 366 367 splx(s); 368 } 369 370 void * 371 dec_550_pciide_compat_intr_establish(v, dev, pa, chan, func, arg) 372 void *v; 373 struct device *dev; 374 struct pci_attach_args *pa; 375 int chan; 376 int (*func) __P((void *)); 377 void *arg; 378 { 379 pci_chipset_tag_t pc = pa->pa_pc; 380 void *cookie = NULL; 381 int bus, irq; 382 383 alpha_pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL); 384 385 /* 386 * If this isn't PCI bus #0, all bets are off. 387 */ 388 if (bus != 0) 389 return (NULL); 390 391 irq = PCIIDE_COMPAT_IRQ(chan); 392 #if NSIO 393 cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO, 394 func, arg); 395 if (cookie == NULL) 396 return (NULL); 397 printf("%s: %s channel interrupting at %s\n", dev->dv_xname, 398 PCIIDE_CHANNEL_NAME(chan), sio_intr_string(NULL /*XXX*/, irq)); 399 #endif 400 return (cookie); 401 } 402 403 void 404 dec_550_iointr(framep, vec) 405 void *framep; 406 unsigned long vec; 407 { 408 int irq; 409 410 if (vec >= 0x900) { 411 irq = ((vec - 0x900) >> 4); 412 413 if (irq >= DEC_550_MAX_IRQ) 414 panic("550_iointr: vec 0x%lx out of range\n", vec); 415 416 if (!alpha_shared_intr_dispatch(dec_550_pci_intr, irq)) { 417 alpha_shared_intr_stray(dec_550_pci_intr, irq, 418 "dec 550 irq"); 419 if (ALPHA_SHARED_INTR_DISABLE(dec_550_pci_intr, irq)) 420 dec_550_intr_disable(irq); 421 } 422 return; 423 } 424 #if NSIO 425 if (vec >= 0x800) { 426 sio_iointr(framep, vec); 427 return; 428 } 429 #endif 430 panic("dec_550_iointr: weird vec 0x%lx\n", vec); 431 } 432 433 void 434 dec_550_intr_enable(irq) 435 int irq; 436 { 437 438 cia_pyxis_intr_enable(irq + DEC_550_PCI_IRQ_BEGIN, 1); 439 } 440 441 void 442 dec_550_intr_disable(irq) 443 int irq; 444 { 445 446 cia_pyxis_intr_enable(irq + DEC_550_PCI_IRQ_BEGIN, 0); 447 } 448