1 /* $NetBSD: pci_1000a.c,v 1.25 2011/04/04 20:37:44 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is based on pci_kn20aa.c, written by Chris G. Demetriou at 8 * Carnegie-Mellon University. Platform support for Noritake, Pintake, and 9 * Corelle by Ross Harvey with copyright assignment by permission of Avalon 10 * Computer Systems, Inc. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 36 * All rights reserved. 37 * 38 * Author: Chris G. Demetriou 39 * 40 * Permission to use, copy, modify and distribute this software and 41 * its documentation is hereby granted, provided that both the copyright 42 * notice and this permission notice appear in all copies of the 43 * software, derivative works or modified versions, and any portions 44 * thereof, and that both notices appear in supporting documentation. 45 * 46 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 47 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 48 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 49 * 50 * Carnegie Mellon requests users of this software to return to 51 * 52 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 53 * School of Computer Science 54 * Carnegie Mellon University 55 * Pittsburgh PA 15213-3890 56 * 57 * any improvements or extensions that they make and grant Carnegie the 58 * rights to redistribute these changes. 59 */ 60 61 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 62 63 __KERNEL_RCSID(0, "$NetBSD: pci_1000a.c,v 1.25 2011/04/04 20:37:44 dyoung Exp $"); 64 65 #include <sys/types.h> 66 #include <sys/param.h> 67 #include <sys/time.h> 68 #include <sys/systm.h> 69 #include <sys/errno.h> 70 #include <sys/malloc.h> 71 #include <sys/device.h> 72 #include <sys/syslog.h> 73 74 #include <machine/autoconf.h> 75 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 79 #include <alpha/pci/pci_1000a.h> 80 81 #include "sio.h" 82 #if NSIO > 0 || NPCEB > 0 83 #include <alpha/pci/siovar.h> 84 #endif 85 86 #define PCI_NIRQ 32 87 #define PCI_STRAY_MAX 5 88 89 #define IMR2IRQ(bn) ((bn) - 1) 90 #define IRQ2IMR(irq) ((irq) + 1) 91 92 static bus_space_tag_t mystery_icu_iot; 93 static bus_space_handle_t mystery_icu_ioh[2]; 94 95 int dec_1000a_intr_map(const struct pci_attach_args *, 96 pci_intr_handle_t *); 97 const char *dec_1000a_intr_string(void *, pci_intr_handle_t); 98 const struct evcnt *dec_1000a_intr_evcnt(void *, pci_intr_handle_t); 99 void *dec_1000a_intr_establish(void *, pci_intr_handle_t, 100 int, int (*func)(void *), void *); 101 void dec_1000a_intr_disestablish(void *, void *); 102 103 struct alpha_shared_intr *dec_1000a_pci_intr; 104 105 static void dec_1000a_iointr(void *arg, unsigned long vec); 106 static void dec_1000a_enable_intr(int irq); 107 static void dec_1000a_disable_intr(int irq); 108 static void pci_1000a_imi(void); 109 static pci_chipset_tag_t pc_tag; 110 111 void 112 pci_1000a_pickintr(void *core, bus_space_tag_t iot, bus_space_tag_t memt, pci_chipset_tag_t pc) 113 { 114 char *cp; 115 int i; 116 117 mystery_icu_iot = iot; 118 119 pc_tag = pc; 120 if (bus_space_map(iot, 0x54a, 2, 0, mystery_icu_ioh + 0) 121 || bus_space_map(iot, 0x54c, 2, 0, mystery_icu_ioh + 1)) 122 panic("pci_1000a_pickintr"); 123 pc->pc_intr_v = core; 124 pc->pc_intr_map = dec_1000a_intr_map; 125 pc->pc_intr_string = dec_1000a_intr_string; 126 pc->pc_intr_evcnt = dec_1000a_intr_evcnt; 127 pc->pc_intr_establish = dec_1000a_intr_establish; 128 pc->pc_intr_disestablish = dec_1000a_intr_disestablish; 129 130 pc->pc_pciide_compat_intr_establish = NULL; 131 132 dec_1000a_pci_intr = alpha_shared_intr_alloc(PCI_NIRQ, 8); 133 for (i = 0; i < PCI_NIRQ; i++) { 134 alpha_shared_intr_set_maxstrays(dec_1000a_pci_intr, i, 135 PCI_STRAY_MAX); 136 137 cp = alpha_shared_intr_string(dec_1000a_pci_intr, i); 138 sprintf(cp, "irq %d", i); 139 evcnt_attach_dynamic(alpha_shared_intr_evcnt( 140 dec_1000a_pci_intr, i), EVCNT_TYPE_INTR, NULL, 141 "dec_1000a", cp); 142 } 143 144 pci_1000a_imi(); 145 #if NSIO > 0 || NPCEB > 0 146 sio_intr_setup(pc, iot); 147 #endif 148 } 149 150 int 151 dec_1000a_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 152 { 153 pcitag_t bustag = pa->pa_intrtag; 154 int buspin = pa->pa_intrpin; 155 pci_chipset_tag_t pc = pa->pa_pc; 156 int imrbit, device; 157 /* 158 * Get bit number in mystery ICU imr 159 */ 160 static const signed char imrmap[][4] = { 161 # define IRQSPLIT(o) { (o), (o)+1, (o)+16, (o)+16+1 } 162 # define IRQNONE { 0, 0, 0, 0 } 163 /* 0 */ { 1, 0, 0, 0 }, /* Noritake and Pintake */ 164 /* 1 */ IRQSPLIT(8), 165 /* 2 */ IRQSPLIT(10), 166 /* 3 */ IRQSPLIT(12), 167 /* 4 */ IRQSPLIT(14), 168 /* 5 */ { 1, 0, 0, 0 }, /* Corelle */ 169 /* 6 */ { 10, 0, 0, 0 }, /* Corelle */ 170 /* 7 */ IRQNONE, 171 /* 8 */ { 1, 0, 0, 0 }, /* isp behind ppb */ 172 /* 9 */ IRQNONE, 173 /* 10 */ IRQNONE, 174 /* 11 */ IRQSPLIT(2), 175 /* 12 */ IRQSPLIT(4), 176 /* 13 */ IRQSPLIT(6), 177 /* 14 */ IRQSPLIT(8) /* Corelle */ 178 }; 179 180 if (buspin == 0) /* No IRQ used. */ 181 return 1; 182 if (!(1 <= buspin && buspin <= 4)) 183 goto bad; 184 pci_decompose_tag(pc, bustag, NULL, &device, NULL); 185 if (0 <= device && device < sizeof imrmap / sizeof imrmap[0]) { 186 if (device == 0) 187 printf("dec_1000a_intr_map: ?! UNEXPECTED DEV 0\n"); 188 imrbit = imrmap[device][buspin - 1]; 189 if (imrbit) { 190 *ihp = IMR2IRQ(imrbit); 191 return 0; 192 } 193 } 194 bad: printf("dec_1000a_intr_map: can't map dev %d pin %d\n", device, buspin); 195 return 1; 196 } 197 198 const char * 199 dec_1000a_intr_string(void *ccv, pci_intr_handle_t ih) 200 { 201 static const char irqmsg_fmt[] = "dec_1000a irq %ld"; 202 static char irqstr[sizeof irqmsg_fmt]; 203 204 205 if (ih >= PCI_NIRQ) 206 panic("dec_1000a_intr_string: bogus dec_1000a IRQ 0x%lx", ih); 207 208 snprintf(irqstr, sizeof irqstr, irqmsg_fmt, ih); 209 return (irqstr); 210 } 211 212 const struct evcnt * 213 dec_1000a_intr_evcnt(void *ccv, pci_intr_handle_t ih) 214 { 215 216 if (ih >= PCI_NIRQ) 217 panic("dec_1000a_intr_evcnt: bogus dec_1000a IRQ 0x%lx", ih); 218 219 return (alpha_shared_intr_evcnt(dec_1000a_pci_intr, ih)); 220 } 221 222 void * 223 dec_1000a_intr_establish(ccv, ih, level, func, arg) 224 void *ccv, *arg; 225 pci_intr_handle_t ih; 226 int level; 227 int (*func)(void *); 228 { 229 void *cookie; 230 231 if (ih >= PCI_NIRQ) 232 panic("dec_1000a_intr_establish: IRQ too high, 0x%lx", ih); 233 234 cookie = alpha_shared_intr_establish(dec_1000a_pci_intr, ih, IST_LEVEL, 235 level, func, arg, "dec_1000a irq"); 236 237 if (cookie != NULL && 238 alpha_shared_intr_firstactive(dec_1000a_pci_intr, ih)) { 239 scb_set(0x900 + SCB_IDXTOVEC(ih), dec_1000a_iointr, NULL, 240 level); 241 dec_1000a_enable_intr(ih); 242 } 243 return (cookie); 244 } 245 246 void 247 dec_1000a_intr_disestablish(void *ccv, void *cookie) 248 { 249 struct alpha_shared_intrhand *ih = cookie; 250 unsigned int irq = ih->ih_num; 251 int s; 252 253 s = splhigh(); 254 255 alpha_shared_intr_disestablish(dec_1000a_pci_intr, cookie, 256 "dec_1000a irq"); 257 if (alpha_shared_intr_isactive(dec_1000a_pci_intr, irq) == 0) { 258 dec_1000a_disable_intr(irq); 259 alpha_shared_intr_set_dfltsharetype(dec_1000a_pci_intr, irq, 260 IST_NONE); 261 scb_free(0x900 + SCB_IDXTOVEC(irq)); 262 } 263 264 splx(s); 265 } 266 267 static void 268 dec_1000a_iointr(void *framep, unsigned long vec) 269 { 270 int irq; 271 272 irq = SCB_VECTOIDX(vec - 0x900); 273 274 if (!alpha_shared_intr_dispatch(dec_1000a_pci_intr, irq)) { 275 alpha_shared_intr_stray(dec_1000a_pci_intr, irq, 276 "dec_1000a irq"); 277 if (ALPHA_SHARED_INTR_DISABLE(dec_1000a_pci_intr, irq)) 278 dec_1000a_disable_intr(irq); 279 } else 280 alpha_shared_intr_reset_strays(dec_1000a_pci_intr, irq); 281 } 282 283 /* 284 * Read and write the mystery ICU IMR registers 285 */ 286 287 #define IR(h) bus_space_read_2(mystery_icu_iot, mystery_icu_ioh[h], 0) 288 #define IW(h, v) bus_space_write_2(mystery_icu_iot, mystery_icu_ioh[h], 0, (v)) 289 290 /* 291 * Enable and disable interrupts at the ICU level 292 */ 293 294 static void 295 dec_1000a_enable_intr(int irq) 296 { 297 int imrval = IRQ2IMR(irq); 298 int i = imrval >= 16; 299 300 IW(i, IR(i) | 1 << (imrval & 0xf)); 301 } 302 303 static void 304 dec_1000a_disable_intr(int irq) 305 { 306 int imrval = IRQ2IMR(irq); 307 int i = imrval >= 16; 308 309 IW(i, IR(i) & ~(1 << (imrval & 0xf))); 310 } 311 /* 312 * Initialize mystery ICU 313 */ 314 static void 315 pci_1000a_imi() 316 { 317 IW(0, IR(0) & 1); 318 IW(1, IR(0) & 3); 319 } 320