1 /* $NetBSD: dwlpx_pci.c,v 1.19 2015/10/02 05:22:49 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997 by Matthew Jacob 5 * NASA AMES Research Center. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice immediately at the beginning of the file, without modification, 13 * this list of conditions, and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 34 35 __KERNEL_RCSID(0, "$NetBSD: dwlpx_pci.c,v 1.19 2015/10/02 05:22:49 msaitoh Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/device.h> 41 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcivar.h> 44 #include <alpha/tlsb/tlsbreg.h> 45 #include <alpha/pci/dwlpxreg.h> 46 #include <alpha/pci/dwlpxvar.h> 47 48 #define KV(_addr) ((void *)ALPHA_PHYS_TO_K0SEG((_addr))) 49 50 void dwlpx_attach_hook(device_t, device_t, 51 struct pcibus_attach_args *); 52 int dwlpx_bus_maxdevs(void *, int); 53 pcitag_t dwlpx_make_tag(void *, int, int, int); 54 void dwlpx_decompose_tag(void *, pcitag_t, int *, int *, 55 int *); 56 pcireg_t dwlpx_conf_read(void *, pcitag_t, int); 57 void dwlpx_conf_write(void *, pcitag_t, int, pcireg_t); 58 59 void 60 dwlpx_pci_init(pci_chipset_tag_t pc, void *v) 61 { 62 pc->pc_conf_v = v; 63 pc->pc_attach_hook = dwlpx_attach_hook; 64 pc->pc_bus_maxdevs = dwlpx_bus_maxdevs; 65 pc->pc_make_tag = dwlpx_make_tag; 66 pc->pc_decompose_tag = dwlpx_decompose_tag; 67 pc->pc_conf_read = dwlpx_conf_read; 68 pc->pc_conf_write = dwlpx_conf_write; 69 } 70 71 void 72 dwlpx_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 73 { 74 #if 0 75 struct dwlpx_config *ccp = pba->pba_pc->pc_conf_v; 76 printf("dwlpx_attach_hook for %s\n", device_xname(ccp->cc_sc->dwlpx_dev)); 77 #endif 78 } 79 80 int 81 dwlpx_bus_maxdevs(void *cpv, int busno) 82 { 83 return DWLPX_MAXDEV; 84 } 85 86 pcitag_t 87 dwlpx_make_tag(void *cpv, int b, int d, int f) 88 { 89 pcitag_t tag; 90 int hpcdev, pci_idsel; 91 92 pci_idsel = (1 << ((d & 0x3) + 2)); 93 hpcdev = d >> 2; 94 tag = (b << 24) | (hpcdev << 22) | (pci_idsel << 16) | (f << 13); 95 return (tag); 96 } 97 98 void 99 dwlpx_decompose_tag(void *cpv, pcitag_t tag, int *bp, int *dp, int *fp) 100 { 101 102 if (bp != NULL) 103 *bp = (tag >> 24) & 0xff; 104 if (dp != NULL) { 105 int j, i = (tag >> 18) & 0xf; 106 j = -1; 107 while (i != 0) { 108 j++; 109 i >>= 1; 110 } 111 j += (((tag >> 22) & 3) << 2); 112 *dp = j; 113 } 114 if (fp != NULL) 115 *fp = (tag >> 13) & 0x7; 116 } 117 118 pcireg_t 119 dwlpx_conf_read(void *cpv, pcitag_t tag, int offset) 120 { 121 struct dwlpx_config *ccp = cpv; 122 struct dwlpx_softc *sc; 123 pcireg_t *dp, data = (pcireg_t) -1; 124 unsigned long paddr; 125 int secondary, i, s = 0; 126 uint32_t rvp; 127 128 if ((unsigned int)offset >= PCI_CONF_SIZE) 129 return (data); 130 131 if (ccp == NULL) { 132 panic("NULL ccp in dwlpx_conf_read"); 133 } 134 sc = ccp->cc_sc; 135 secondary = tag >> 24; 136 if (secondary) { 137 tag &= 0x1fffff; 138 tag |= (secondary << 21); 139 140 #if 0 141 printf("read secondary %d reg %x (tag %x)", 142 secondary, offset, tag); 143 #endif 144 145 alpha_pal_draina(); 146 s = splhigh(); 147 /* 148 * Set up HPCs for type 1 cycles. 149 */ 150 for (i = 0; i < sc->dwlpx_nhpc; i++) { 151 rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) | 152 PCIA_CTL_T1CYC; 153 alpha_mb(); 154 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp; 155 alpha_mb(); 156 } 157 } 158 paddr = (unsigned long) tag; 159 paddr |= DWLPX_PCI_CONF; 160 paddr |= ((unsigned long) ((offset >> 2) << 7)); 161 paddr |= (((unsigned long) sc->dwlpx_hosenum) << 34); 162 paddr |= (((u_long) sc->dwlpx_node - 4) << 36); 163 paddr |= (1LL << 39); 164 paddr |= (3LL << 3); /* 32 Bit PCI byte enables */ 165 166 dp = (pcireg_t *)KV(paddr); 167 if (badaddr(dp, sizeof (*dp)) == 0) { 168 data = *dp; 169 } 170 if (secondary) { 171 alpha_pal_draina(); 172 for (i = 0; i < sc->dwlpx_nhpc; i++) { 173 rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) & 174 ~PCIA_CTL_T1CYC; 175 alpha_mb(); 176 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp; 177 alpha_mb(); 178 } 179 (void) splx(s); 180 #if 0 181 printf("=%x\n", data); 182 #endif 183 } 184 return (data); 185 } 186 187 void 188 dwlpx_conf_write(void *cpv, pcitag_t tag, int offset, pcireg_t data) 189 { 190 struct dwlpx_config *ccp = cpv; 191 struct dwlpx_softc *sc; 192 pcireg_t *dp; 193 unsigned long paddr; 194 int secondary, i, s = 0; 195 uint32_t rvp; 196 197 if ((unsigned int)offset >= PCI_CONF_SIZE) 198 return; 199 200 if (ccp == NULL) { 201 panic("NULL ccp in dwlpx_conf_write"); 202 } 203 sc = ccp->cc_sc; 204 secondary = tag >> 24; 205 if (secondary) { 206 tag &= 0x1fffff; 207 tag |= (secondary << 21); 208 #if 0 209 printf("write secondary %d reg %x (tag %x) with %x\n", 210 secondary, offset, tag, data); 211 #endif 212 213 alpha_pal_draina(); 214 s = splhigh(); 215 /* 216 * Set up HPCs for type 1 cycles. 217 */ 218 for (i = 0; i < sc->dwlpx_nhpc; i++) { 219 rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) | 220 PCIA_CTL_T1CYC; 221 alpha_mb(); 222 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp; 223 alpha_mb(); 224 } 225 } 226 paddr = (unsigned long) tag; 227 paddr |= DWLPX_PCI_CONF; 228 paddr |= ((unsigned long) ((offset >> 2) << 7)); 229 paddr |= (((unsigned long) sc->dwlpx_hosenum) << 34); 230 paddr |= (((u_long) sc->dwlpx_node - 4) << 36); 231 paddr |= (1LL << 39); 232 paddr |= (3LL << 3); /* 32 bit PCI byte enables */ 233 234 dp = (pcireg_t *)KV(paddr); 235 *dp = data; 236 alpha_mb(); 237 if (secondary) { 238 alpha_pal_draina(); 239 for (i = 0; i < sc->dwlpx_nhpc; i++) { 240 rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) & 241 ~PCIA_CTL_T1CYC; 242 alpha_mb(); 243 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp; 244 alpha_mb(); 245 } 246 (void) splx(s); 247 } 248 } 249