1 /* $NetBSD: dwlpx.c,v 1.32 2007/03/04 05:59:11 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1997 by Matthew Jacob 5 * NASA AMES Research Center. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice immediately at the beginning of the file, without modification, 13 * this list of conditions, and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 34 35 __KERNEL_RCSID(0, "$NetBSD: dwlpx.c,v 1.32 2007/03/04 05:59:11 christos Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/device.h> 41 42 #include <uvm/uvm_extern.h> 43 44 #include <machine/autoconf.h> 45 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcivar.h> 48 49 #include <alpha/tlsb/tlsbreg.h> 50 #include <alpha/tlsb/kftxxvar.h> 51 #include <alpha/tlsb/kftxxreg.h> 52 #include <alpha/pci/dwlpxreg.h> 53 #include <alpha/pci/dwlpxvar.h> 54 #include <alpha/pci/pci_kn8ae.h> 55 56 #define KV(_addr) ((void *)ALPHA_PHYS_TO_K0SEG((_addr))) 57 #define DWLPX_SYSBASE(sc) \ 58 ((((unsigned long)((sc)->dwlpx_node - 4)) << 36) | \ 59 (((unsigned long) (sc)->dwlpx_hosenum) << 34) | \ 60 (1LL << 39)) 61 #define DWLPX_SYSBASE1(node, hosenum) \ 62 ((((unsigned long)(node - 4)) << 36) | \ 63 (((unsigned long) hosenum) << 34) | \ 64 (1LL << 39)) 65 66 67 static int dwlpxmatch __P((struct device *, struct cfdata *, void *)); 68 static void dwlpxattach __P((struct device *, struct device *, void *)); 69 CFATTACH_DECL(dwlpx, sizeof(struct dwlpx_softc), 70 dwlpxmatch, dwlpxattach, NULL, NULL); 71 72 extern struct cfdriver dwlpx_cd; 73 74 void dwlpx_errintr(void *, u_long vec); 75 76 static int 77 dwlpxmatch(parent, cf, aux) 78 struct device *parent; 79 struct cfdata *cf; 80 void *aux; 81 { 82 struct kft_dev_attach_args *ka = aux; 83 unsigned long ls; 84 u_int32_t ctl; 85 86 if (strcmp(ka->ka_name, dwlpx_cd.cd_name) != 0) 87 return (0); 88 89 ls = DWLPX_SYSBASE1(ka->ka_node, ka->ka_hosenum); 90 91 /* 92 * Probe the first HPC to make sure this really is a dwlpx and 93 * nothing else. 94 */ 95 if (badaddr(KV(PCIA_CTL(1) + ls), sizeof (ctl)) != 0) { 96 /* 97 * If we are here something went wrong. One reason 98 * could be that this is a dwlma and not a dwlpx. 99 * 100 * We can not clear potential illegal CSR errors here 101 * since it is unknown hardware. 102 */ 103 return (0); 104 } 105 106 return (1); 107 } 108 109 static void 110 dwlpxattach(parent, self, aux) 111 struct device *parent; 112 struct device *self; 113 void *aux; 114 { 115 static int once = 0; 116 struct dwlpx_softc *sc = (struct dwlpx_softc *)self; 117 struct dwlpx_config *ccp = &sc->dwlpx_cc; 118 struct kft_dev_attach_args *ka = aux; 119 struct pcibus_attach_args pba; 120 u_int32_t pcia_present; 121 122 sc->dwlpx_node = ka->ka_node; 123 sc->dwlpx_dtype = ka->ka_dtype; 124 sc->dwlpx_hosenum = ka->ka_hosenum; 125 126 dwlpx_init(sc); 127 dwlpx_dma_init(ccp); 128 129 pcia_present = REGVAL(PCIA_PRESENT + ccp->cc_sysbase); 130 printf(": PCIA rev. %d, STD I/O %spresent, %dK S/G entries\n", 131 (pcia_present >> PCIA_PRESENT_REVSHIFT) & PCIA_PRESENT_REVMASK, 132 (pcia_present & PCIA_PRESENT_STDIO) == 0 ? "not " : "", 133 sc->dwlpx_sgmapsz == DWLPX_SG128K ? 128 : 32); 134 135 #if 0 136 { 137 int hpc, slot, slotval; 138 const char *str; 139 for (hpc = 0; hpc < sc->dwlpx_nhpc; hpc++) { 140 for (slot = 0; slot < 4; slot++) { 141 slotval = (pcia_present >> 142 PCIA_PRESENT_SLOTSHIFT(hpc, slot)) & 143 PCIA_PRESENT_SLOT_MASK; 144 if (slotval == PCIA_PRESENT_SLOT_NONE) 145 continue; 146 switch (slotval) { 147 case PCIA_PRESENT_SLOT_25W: 148 str = "25"; 149 break; 150 case PCIA_PRESENT_SLOT_15W: 151 str = "15"; 152 break; 153 case PCIA_PRESENT_SLOW_7W: 154 default: /* XXX gcc */ 155 str = "7.5"; 156 break; 157 } 158 printf("%s: hpc %d slot %d: %s watt module\n", 159 sc->dwlpx_dev.dv_xname, hpc, slot, str); 160 } 161 } 162 } 163 #endif 164 165 if (once == 0) { 166 /* 167 * Set up interrupts 168 */ 169 pci_kn8ae_pickintr(&sc->dwlpx_cc, 1); 170 once++; 171 } else { 172 pci_kn8ae_pickintr(&sc->dwlpx_cc, 0); 173 } 174 175 /* 176 * Attach PCI bus 177 */ 178 pba.pba_iot = &sc->dwlpx_cc.cc_iot; 179 pba.pba_memt = &sc->dwlpx_cc.cc_memt; 180 pba.pba_dmat = /* start with direct, may change... */ 181 alphabus_dma_get_tag(&sc->dwlpx_cc.cc_dmat_direct, ALPHA_BUS_PCI); 182 pba.pba_dmat64 = NULL; 183 pba.pba_pc = &sc->dwlpx_cc.cc_pc; 184 pba.pba_bus = 0; 185 pba.pba_bridgetag = NULL; 186 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 187 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 188 config_found_ia(self, "pcibus", &pba, pcibusprint); 189 } 190 191 void 192 dwlpx_init(sc) 193 struct dwlpx_softc *sc; 194 { 195 u_int32_t ctl; 196 struct dwlpx_config *ccp = &sc->dwlpx_cc; 197 unsigned long vec, ls = DWLPX_SYSBASE(sc); 198 int i; 199 200 if (ccp->cc_initted == 0) { 201 /* 202 * On reads, you get a fault if you read a nonexisted HPC. 203 * We know the internal KFTIA hose (hose 0) has only 2 HPCs, 204 * but we can also actually probe for HPCs. 205 * Assume at least one. 206 */ 207 for (sc->dwlpx_nhpc = 1; sc->dwlpx_nhpc < NHPC; 208 sc->dwlpx_nhpc++) { 209 if (badaddr(KV(PCIA_CTL(sc->dwlpx_nhpc) + ls), 210 sizeof (ctl)) != 0) { 211 break; 212 } 213 } 214 if (sc->dwlpx_nhpc != NHPC) { 215 /* clear (potential) Illegal CSR Address Error */ 216 REGVAL(PCIA_ERR(0) + DWLPX_SYSBASE(sc)) = 217 PCIA_ERR_ALLERR; 218 } 219 220 dwlpx_bus_io_init(&ccp->cc_iot, ccp); 221 dwlpx_bus_mem_init(&ccp->cc_memt, ccp); 222 } 223 dwlpx_pci_init(&ccp->cc_pc, ccp); 224 ccp->cc_sc = sc; 225 226 /* 227 * Establish a precalculated base for convenience's sake. 228 */ 229 ccp->cc_sysbase = ls; 230 231 /* 232 * If there are only 2 HPCs, then the 'present' register is not 233 * implemented, so there will only ever be 32K SG entries. Otherwise 234 * any revision greater than zero will have 128K entries. 235 */ 236 ctl = REGVAL(PCIA_PRESENT + ccp->cc_sysbase); 237 if (sc->dwlpx_nhpc == 2) { 238 sc->dwlpx_sgmapsz = DWLPX_SG32K; 239 #if 0 240 /* 241 * As of 2/25/98- When I enable SG128K, and then have to flip 242 * TBIT below, I get bad SGRAM errors. We'll fix this later 243 * if this gets important. 244 */ 245 } else if ((ctl >> PCIA_PRESENT_REVSHIFT) & PCIA_PRESENT_REVMASK) { 246 sc->dwlpx_sgmapsz = DWLPX_SG128K; 247 #endif 248 } else { 249 sc->dwlpx_sgmapsz = DWLPX_SG32K; 250 } 251 252 /* 253 * Set up interrupt stuff for this DWLPX. 254 * 255 * Note that all PCI interrupt pins are disabled at this time. 256 * 257 * Do this even for all HPCs- even for the nonexistent 258 * one on hose zero of a KFTIA. 259 */ 260 vec = scb_alloc(dwlpx_errintr, sc); 261 if (vec == SCB_ALLOC_FAILED) 262 panic("%s: unable to allocate error vector", 263 sc->dwlpx_dev.dv_xname); 264 printf("%s: error interrupt at vector 0x%lx\n", 265 sc->dwlpx_dev.dv_xname, vec); 266 for (i = 0; i < NHPC; i++) { 267 REGVAL(PCIA_IMASK(i) + ccp->cc_sysbase) = DWLPX_IMASK_DFLT; 268 REGVAL(PCIA_ERRVEC(i) + ccp->cc_sysbase) = vec; 269 } 270 271 /* 272 * Establish HAE values, as well as make sure of sanity elsewhere. 273 */ 274 for (i = 0; i < sc->dwlpx_nhpc; i++) { 275 ctl = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase); 276 ctl &= 0x0fffffff; 277 ctl &= ~(PCIA_CTL_MHAE(0x1f) | PCIA_CTL_IHAE(0x1f)); 278 /* 279 * I originally also had it or'ing in 3, which makes no sense. 280 */ 281 282 ctl |= PCIA_CTL_RMMENA | PCIA_CTL_RMMARB; 283 284 /* 285 * Only valid if we're attached to a KFTIA or a KTHA. 286 */ 287 ctl |= PCIA_CTL_3UP; 288 289 ctl |= PCIA_CTL_CUTENA; 290 291 /* 292 * Fit in appropriate S/G Map Ram size. 293 */ 294 if (sc->dwlpx_sgmapsz == DWLPX_SG32K) 295 ctl |= PCIA_CTL_SG32K; 296 else if (sc->dwlpx_sgmapsz == DWLPX_SG128K) 297 ctl |= PCIA_CTL_SG128K; 298 else 299 ctl |= PCIA_CTL_SG32K; 300 301 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = ctl; 302 } 303 /* 304 * Enable TBIT if required 305 */ 306 if (sc->dwlpx_sgmapsz == DWLPX_SG128K) 307 REGVAL(PCIA_TBIT + ccp->cc_sysbase) = 1; 308 alpha_mb(); 309 ccp->cc_initted = 1; 310 } 311 312 void 313 dwlpx_errintr(arg, vec) 314 void *arg; 315 unsigned long vec; 316 { 317 struct dwlpx_softc *sc = arg; 318 struct dwlpx_config *ccp = &sc->dwlpx_cc; 319 int i; 320 struct { 321 u_int32_t err; 322 u_int32_t addr; 323 } hpcs[NHPC]; 324 325 for (i = 0; i < sc->dwlpx_nhpc; i++) { 326 hpcs[i].err = REGVAL(PCIA_ERR(i) + ccp->cc_sysbase); 327 hpcs[i].addr = REGVAL(PCIA_FADR(i) + ccp->cc_sysbase); 328 } 329 printf("%s: node %d hose %d error interrupt\n", 330 sc->dwlpx_dev.dv_xname, sc->dwlpx_node, sc->dwlpx_hosenum); 331 332 for (i = 0; i < sc->dwlpx_nhpc; i++) { 333 if ((hpcs[i].err & PCIA_ERR_ERROR) == 0) 334 continue; 335 printf("\tHPC %d: ERR=0x%08x; DMA %s Memory, " 336 "Failing Address 0x%x\n", 337 i, hpcs[i].err, hpcs[i].addr & 0x1? "write to" : 338 "read from", hpcs[i].addr & ~3); 339 if (hpcs[i].err & PCIA_ERR_SERR_L) 340 printf("\t PCI device asserted SERR_L\n"); 341 if (hpcs[i].err & PCIA_ERR_ILAT) 342 printf("\t Incremental Latency Exceeded\n"); 343 if (hpcs[i].err & PCIA_ERR_SGPRTY) 344 printf("\t CPU access of SG RAM Parity Error\n"); 345 if (hpcs[i].err & PCIA_ERR_ILLCSR) 346 printf("\t Illegal CSR Address Error\n"); 347 if (hpcs[i].err & PCIA_ERR_PCINXM) 348 printf("\t Nonexistent PCI Address Error\n"); 349 if (hpcs[i].err & PCIA_ERR_DSCERR) 350 printf("\t PCI Target Disconnect Error\n"); 351 if (hpcs[i].err & PCIA_ERR_ABRT) 352 printf("\t PCI Target Abort Error\n"); 353 if (hpcs[i].err & PCIA_ERR_WPRTY) 354 printf("\t PCI Write Parity Error\n"); 355 if (hpcs[i].err & PCIA_ERR_DPERR) 356 printf("\t PCI Data Parity Error\n"); 357 if (hpcs[i].err & PCIA_ERR_APERR) 358 printf("\t PCI Address Parity Error\n"); 359 if (hpcs[i].err & PCIA_ERR_DFLT) 360 printf("\t SG Map RAM Invalid Entry Error\n"); 361 if (hpcs[i].err & PCIA_ERR_DPRTY) 362 printf("\t DMA access of SG RAM Parity Error\n"); 363 if (hpcs[i].err & PCIA_ERR_DRPERR) 364 printf("\t DMA Read Return Parity Error\n"); 365 if (hpcs[i].err & PCIA_ERR_MABRT) 366 printf("\t PCI Master Abort Error\n"); 367 if (hpcs[i].err & PCIA_ERR_CPRTY) 368 printf("\t CSR Parity Error\n"); 369 if (hpcs[i].err & PCIA_ERR_COVR) 370 printf("\t CSR Overrun Error\n"); 371 if (hpcs[i].err & PCIA_ERR_MBPERR) 372 printf("\t Mailbox Parity Error\n"); 373 if (hpcs[i].err & PCIA_ERR_MBILI) 374 printf("\t Mailbox Illegal Length Error\n"); 375 REGVAL(PCIA_ERR(i) + ccp->cc_sysbase) = hpcs[i].err; 376 } 377 } 378