1 /* $NetBSD: ciareg.h,v 1.8 1997/04/07 01:59:54 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 /* 31 * 21171 Chipset registers and constants. 32 * 33 * Taken from XXX 34 */ 35 36 #define REGVAL(r) (*(int32_t *)ALPHA_PHYS_TO_K0SEG(r)) 37 38 /* 39 * Base addresses 40 */ 41 #define CIA_PCI_SMEM1 0x8000000000UL 42 #define CIA_PCI_SMEM2 0x8400000000UL 43 #define CIA_PCI_SMEM3 0x8500000000UL 44 #define CIA_PCI_SIO1 0x8580000000UL 45 #define CIA_PCI_SIO2 0x85c0000000UL 46 #define CIA_PCI_DENSE 0x8600000000UL 47 #define CIA_PCI_CONF 0x8700000000UL 48 #define CIA_PCI_IACK 0x8720000000UL 49 #define CIA_CSRS 0x8740000000UL 50 #define CIA_PCI_MC_CSRS 0x8750000000UL 51 #define CIA_PCI_ATRANS 0x8760000000UL 52 53 /* 54 * General CSRs 55 */ 56 57 #define CIA_CSR_HAE_MEM (CIA_CSRS + 0x400) 58 59 #define HAE_MEM_REG1_START(x) (((u_int32_t)(x) & 0xe0000000UL) << 0) 60 #define HAE_MEM_REG1_MASK 0x1fffffffUL 61 #define HAE_MEM_REG2_START(x) (((u_int32_t)(x) & 0x0000f800UL) << 16) 62 #define HAE_MEM_REG2_MASK 0x07ffffffUL 63 #define HAE_MEM_REG3_START(x) (((u_int32_t)(x) & 0x000000fcUL) << 24) 64 #define HAE_MEM_REG3_MASK 0x03ffffffUL 65 66 #define CIA_CSR_HAE_IO (CIA_CSRS + 0x440) 67 68 #define HAE_IO_REG1_START(x) 0UL 69 #define HAE_IO_REG1_MASK 0x01ffffffUL 70 #define HAE_IO_REG2_START(x) (((u_int32_t)(x) & 0xfe000000UL) << 0) 71 #define HAE_IO_REG2_MASK 0x01ffffffUL 72 73 #define CIA_CSR_CIA_ERR (CIA_CSRS + 0x8200) 74