1 /* $NetBSD: cia_dma.c,v 1.28 2012/02/06 02:14:14 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 34 35 __KERNEL_RCSID(0, "$NetBSD: cia_dma.c,v 1.28 2012/02/06 02:14:14 matt Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/device.h> 41 #include <sys/malloc.h> 42 43 #define _ALPHA_BUS_DMA_PRIVATE 44 #include <sys/bus.h> 45 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcivar.h> 48 #include <alpha/pci/ciareg.h> 49 #include <alpha/pci/ciavar.h> 50 51 bus_dma_tag_t cia_dma_get_tag(bus_dma_tag_t, alpha_bus_t); 52 53 int cia_bus_dmamap_create_direct(bus_dma_tag_t, bus_size_t, int, 54 bus_size_t, bus_size_t, int, bus_dmamap_t *); 55 56 int cia_bus_dmamap_load_sgmap(bus_dma_tag_t, bus_dmamap_t, void *, 57 bus_size_t, struct proc *, int); 58 59 int cia_bus_dmamap_load_mbuf_sgmap(bus_dma_tag_t, bus_dmamap_t, 60 struct mbuf *, int); 61 62 int cia_bus_dmamap_load_uio_sgmap(bus_dma_tag_t, bus_dmamap_t, 63 struct uio *, int); 64 65 int cia_bus_dmamap_load_raw_sgmap(bus_dma_tag_t, bus_dmamap_t, 66 bus_dma_segment_t *, int, bus_size_t, int); 67 68 void cia_bus_dmamap_unload_sgmap(bus_dma_tag_t, bus_dmamap_t); 69 70 /* 71 * Direct-mapped window: 1G at 1G 72 */ 73 #define CIA_DIRECT_MAPPED_BASE (1*1024*1024*1024) 74 #define CIA_DIRECT_MAPPED_SIZE (1*1024*1024*1024) 75 76 /* 77 * SGMAP window: 8M at 8M 78 */ 79 #define CIA_SGMAP_MAPPED_BASE (8*1024*1024) 80 #define CIA_SGMAP_MAPPED_SIZE (8*1024*1024) 81 82 /* ALCOR/ALGOR2/PYXIS have a 256-byte out-bound DMA prefetch threshold. */ 83 #define CIA_SGMAP_PFTHRESH 256 84 85 void cia_tlb_invalidate(void); 86 void cia_broken_pyxis_tlb_invalidate(void); 87 88 void (*cia_tlb_invalidate_fn)(void); 89 90 #define CIA_TLB_INVALIDATE() (*cia_tlb_invalidate_fn)() 91 92 struct alpha_sgmap cia_pyxis_bug_sgmap; 93 #define CIA_PYXIS_BUG_BASE (128*1024*1024) 94 #define CIA_PYXIS_BUG_SIZE (2*1024*1024) 95 96 void 97 cia_dma_init(struct cia_config *ccp) 98 { 99 bus_addr_t tbase; 100 bus_dma_tag_t t; 101 102 /* 103 * Initialize the DMA tag used for direct-mapped DMA. 104 */ 105 t = &ccp->cc_dmat_direct; 106 t->_cookie = ccp; 107 t->_wbase = CIA_DIRECT_MAPPED_BASE; 108 t->_wsize = CIA_DIRECT_MAPPED_SIZE; 109 t->_next_window = &ccp->cc_dmat_sgmap; 110 t->_boundary = 0; 111 t->_sgmap = NULL; 112 t->_get_tag = cia_dma_get_tag; 113 t->_dmamap_create = cia_bus_dmamap_create_direct; 114 t->_dmamap_destroy = _bus_dmamap_destroy; 115 t->_dmamap_load = _bus_dmamap_load_direct; 116 t->_dmamap_load_mbuf = _bus_dmamap_load_mbuf_direct; 117 t->_dmamap_load_uio = _bus_dmamap_load_uio_direct; 118 t->_dmamap_load_raw = _bus_dmamap_load_raw_direct; 119 t->_dmamap_unload = _bus_dmamap_unload; 120 t->_dmamap_sync = _bus_dmamap_sync; 121 122 t->_dmamem_alloc = _bus_dmamem_alloc; 123 t->_dmamem_free = _bus_dmamem_free; 124 t->_dmamem_map = _bus_dmamem_map; 125 t->_dmamem_unmap = _bus_dmamem_unmap; 126 t->_dmamem_mmap = _bus_dmamem_mmap; 127 128 /* 129 * Initialize the DMA tag used for sgmap-mapped DMA. 130 */ 131 t = &ccp->cc_dmat_sgmap; 132 t->_cookie = ccp; 133 t->_wbase = CIA_SGMAP_MAPPED_BASE; 134 t->_wsize = CIA_SGMAP_MAPPED_SIZE; 135 t->_next_window = NULL; 136 t->_boundary = 0; 137 t->_sgmap = &ccp->cc_sgmap; 138 t->_pfthresh = CIA_SGMAP_PFTHRESH; 139 t->_get_tag = cia_dma_get_tag; 140 t->_dmamap_create = alpha_sgmap_dmamap_create; 141 t->_dmamap_destroy = alpha_sgmap_dmamap_destroy; 142 t->_dmamap_load = cia_bus_dmamap_load_sgmap; 143 t->_dmamap_load_mbuf = cia_bus_dmamap_load_mbuf_sgmap; 144 t->_dmamap_load_uio = cia_bus_dmamap_load_uio_sgmap; 145 t->_dmamap_load_raw = cia_bus_dmamap_load_raw_sgmap; 146 t->_dmamap_unload = cia_bus_dmamap_unload_sgmap; 147 t->_dmamap_sync = _bus_dmamap_sync; 148 149 t->_dmamem_alloc = _bus_dmamem_alloc; 150 t->_dmamem_free = _bus_dmamem_free; 151 t->_dmamem_map = _bus_dmamem_map; 152 t->_dmamem_unmap = _bus_dmamem_unmap; 153 t->_dmamem_mmap = _bus_dmamem_mmap; 154 155 /* 156 * The firmware has set up window 1 as a 1G direct-mapped DMA 157 * window beginning at 1G. We leave it alone. Leave window 158 * 0 alone until we reconfigure it for SGMAP-mapped DMA. 159 * Windows 2 and 3 are already disabled. 160 */ 161 162 /* 163 * Initialize the SGMAP. Must align page table to 32k 164 * (hardware bug?). 165 */ 166 alpha_sgmap_init(t, &ccp->cc_sgmap, "cia_sgmap", 167 CIA_SGMAP_MAPPED_BASE, 0, CIA_SGMAP_MAPPED_SIZE, 168 sizeof(uint64_t), NULL, (32*1024)); 169 170 /* 171 * Set up window 0 as an 8MB SGMAP-mapped window 172 * starting at 8MB. 173 */ 174 REGVAL(CIA_PCI_W0BASE) = CIA_SGMAP_MAPPED_BASE | 175 CIA_PCI_WnBASE_SG_EN | CIA_PCI_WnBASE_W_EN; 176 alpha_mb(); 177 178 REGVAL(CIA_PCI_W0MASK) = CIA_PCI_WnMASK_8M; 179 alpha_mb(); 180 181 tbase = ccp->cc_sgmap.aps_ptpa >> CIA_PCI_TnBASE_SHIFT; 182 if ((tbase & CIA_PCI_TnBASE_MASK) != tbase) 183 panic("cia_dma_init: bad page table address"); 184 REGVAL(CIA_PCI_T0BASE) = tbase; 185 alpha_mb(); 186 187 /* 188 * Pass 1 and 2 (i.e. revision <= 1) of the Pyxis have a 189 * broken scatter/gather TLB; it cannot be invalidated. To 190 * work around this problem, we configure window 2 as an SG 191 * 2M window at 128M, which we use in DMA loopback mode to 192 * read a spill page. This works by causing TLB misses, 193 * causing the old entries to be purged to make room for 194 * the new entries coming in for the spill page. 195 */ 196 if ((ccp->cc_flags & CCF_ISPYXIS) != 0 && ccp->cc_rev <= 1) { 197 uint64_t *page_table; 198 int i; 199 200 cia_tlb_invalidate_fn = 201 cia_broken_pyxis_tlb_invalidate; 202 203 alpha_sgmap_init(t, &cia_pyxis_bug_sgmap, 204 "pyxis_bug_sgmap", CIA_PYXIS_BUG_BASE, 0, 205 CIA_PYXIS_BUG_SIZE, sizeof(uint64_t), NULL, 206 (32*1024)); 207 208 REGVAL(CIA_PCI_W2BASE) = CIA_PYXIS_BUG_BASE | 209 CIA_PCI_WnBASE_SG_EN | CIA_PCI_WnBASE_W_EN; 210 alpha_mb(); 211 212 REGVAL(CIA_PCI_W2MASK) = CIA_PCI_WnMASK_2M; 213 alpha_mb(); 214 215 tbase = cia_pyxis_bug_sgmap.aps_ptpa >> 216 CIA_PCI_TnBASE_SHIFT; 217 if ((tbase & CIA_PCI_TnBASE_MASK) != tbase) 218 panic("cia_dma_init: bad page table address"); 219 REGVAL(CIA_PCI_T2BASE) = tbase; 220 alpha_mb(); 221 222 /* 223 * Initialize the page table to point at the spill 224 * page. Leave the last entry invalid. 225 */ 226 pci_sgmap_pte64_init_spill_page_pte(); 227 for (i = 0, page_table = cia_pyxis_bug_sgmap.aps_pt; 228 i < (CIA_PYXIS_BUG_SIZE / PAGE_SIZE) - 1; i++) { 229 page_table[i] = 230 pci_sgmap_pte64_prefetch_spill_page_pte; 231 } 232 alpha_mb(); 233 } else 234 cia_tlb_invalidate_fn = cia_tlb_invalidate; 235 236 CIA_TLB_INVALIDATE(); 237 238 /* XXX XXX BEGIN XXX XXX */ 239 { /* XXX */ 240 extern paddr_t alpha_XXX_dmamap_or; /* XXX */ 241 alpha_XXX_dmamap_or = CIA_DIRECT_MAPPED_BASE; /* XXX */ 242 } /* XXX */ 243 /* XXX XXX END XXX XXX */ 244 } 245 246 /* 247 * Return the bus dma tag to be used for the specified bus type. 248 * INTERNAL USE ONLY! 249 */ 250 bus_dma_tag_t 251 cia_dma_get_tag(bus_dma_tag_t t, alpha_bus_t bustype) 252 { 253 struct cia_config *ccp = t->_cookie; 254 255 switch (bustype) { 256 case ALPHA_BUS_PCI: 257 case ALPHA_BUS_EISA: 258 /* 259 * Systems with a CIA can only support 1G 260 * of memory, so we use the direct-mapped window 261 * on busses that have 32-bit DMA. 262 * 263 * Ahem: I have a PWS 500au with 1.5G of memory, and it 264 * had problems doing DMA because it was not falling back 265 * to using SGMAPs. I've fixed that and my PWS now works with 266 * 1.5G. There have been other reports about failures with 267 * more than 1.0G of memory. Michael Hitch 268 */ 269 return (&ccp->cc_dmat_direct); 270 271 case ALPHA_BUS_ISA: 272 /* 273 * ISA doesn't have enough address bits to use 274 * the direct-mapped DMA window, so we must use 275 * SGMAPs. 276 */ 277 return (&ccp->cc_dmat_sgmap); 278 279 default: 280 panic("cia_dma_get_tag: shouldn't be here, really..."); 281 } 282 } 283 284 /* 285 * Create a CIA direct-mapped DMA map. 286 */ 287 int 288 cia_bus_dmamap_create_direct( 289 bus_dma_tag_t t, 290 bus_size_t size, 291 int nsegments, 292 bus_size_t maxsegsz, 293 bus_size_t boundary, 294 int flags, 295 bus_dmamap_t *dmamp) 296 { 297 struct cia_config *ccp = t->_cookie; 298 bus_dmamap_t map; 299 int error; 300 301 error = _bus_dmamap_create(t, size, nsegments, maxsegsz, 302 boundary, flags, dmamp); 303 if (error) 304 return (error); 305 306 map = *dmamp; 307 308 if ((ccp->cc_flags & CCF_PYXISBUG) != 0 && 309 map->_dm_segcnt > 1) { 310 /* 311 * We have a Pyxis with the DMA page crossing bug, make 312 * sure we don't coalesce adjacent DMA segments. 313 * 314 * NOTE: We can only do this if the max segment count 315 * is greater than 1. This is because many network 316 * drivers allocate large contiguous blocks of memory 317 * for control data structures, even though they won't 318 * do any single DMA that crosses a page coundary. 319 * -- thorpej@NetBSD.org, 2/5/2000 320 */ 321 map->_dm_flags |= DMAMAP_NO_COALESCE; 322 } 323 324 return (0); 325 } 326 327 /* 328 * Load a CIA SGMAP-mapped DMA map with a linear buffer. 329 */ 330 int 331 cia_bus_dmamap_load_sgmap(bus_dma_tag_t t, bus_dmamap_t map, void *buf, bus_size_t buflen, struct proc *p, int flags) 332 { 333 int error; 334 335 error = pci_sgmap_pte64_load(t, map, buf, buflen, p, flags, 336 t->_sgmap); 337 if (error == 0) 338 CIA_TLB_INVALIDATE(); 339 340 return (error); 341 } 342 343 /* 344 * Load a CIA SGMAP-mapped DMA map with an mbuf chain. 345 */ 346 int 347 cia_bus_dmamap_load_mbuf_sgmap(bus_dma_tag_t t, bus_dmamap_t map, struct mbuf *m, int flags) 348 { 349 int error; 350 351 error = pci_sgmap_pte64_load_mbuf(t, map, m, flags, t->_sgmap); 352 if (error == 0) 353 CIA_TLB_INVALIDATE(); 354 355 return (error); 356 } 357 358 /* 359 * Load a CIA SGMAP-mapped DMA map with a uio. 360 */ 361 int 362 cia_bus_dmamap_load_uio_sgmap(bus_dma_tag_t t, bus_dmamap_t map, struct uio *uio, int flags) 363 { 364 int error; 365 366 error = pci_sgmap_pte64_load_uio(t, map, uio, flags, t->_sgmap); 367 if (error == 0) 368 CIA_TLB_INVALIDATE(); 369 370 return (error); 371 } 372 373 /* 374 * Load a CIA SGMAP-mapped DMA map with raw memory. 375 */ 376 int 377 cia_bus_dmamap_load_raw_sgmap(bus_dma_tag_t t, bus_dmamap_t map, bus_dma_segment_t *segs, int nsegs, bus_size_t size, int flags) 378 { 379 int error; 380 381 error = pci_sgmap_pte64_load_raw(t, map, segs, nsegs, size, flags, 382 t->_sgmap); 383 if (error == 0) 384 CIA_TLB_INVALIDATE(); 385 386 return (error); 387 } 388 389 /* 390 * Unload a CIA DMA map. 391 */ 392 void 393 cia_bus_dmamap_unload_sgmap(bus_dma_tag_t t, bus_dmamap_t map) 394 { 395 396 /* 397 * Invalidate any SGMAP page table entries used by this 398 * mapping. 399 */ 400 pci_sgmap_pte64_unload(t, map, t->_sgmap); 401 CIA_TLB_INVALIDATE(); 402 403 /* 404 * Do the generic bits of the unload. 405 */ 406 _bus_dmamap_unload(t, map); 407 } 408 409 /* 410 * Flush the CIA scatter/gather TLB. 411 */ 412 void 413 cia_tlb_invalidate(void) 414 { 415 416 alpha_mb(); 417 REGVAL(CIA_PCI_TBIA) = CIA_PCI_TBIA_ALL; 418 alpha_mb(); 419 } 420 421 /* 422 * Flush the scatter/gather TLB on broken Pyxis chips. 423 */ 424 void 425 cia_broken_pyxis_tlb_invalidate(void) 426 { 427 volatile uint64_t dummy; 428 uint32_t ctrl; 429 int i, s; 430 431 s = splhigh(); 432 433 /* 434 * Put the Pyxis into PCI loopback mode. 435 */ 436 alpha_mb(); 437 ctrl = REGVAL(CIA_CSR_CTRL); 438 REGVAL(CIA_CSR_CTRL) = ctrl | CTRL_PCI_LOOP_EN; 439 alpha_mb(); 440 441 /* 442 * Now, read from PCI dense memory space at offset 128M (our 443 * target window base), skipping 64k on each read. This forces 444 * S/G TLB misses. 445 * 446 * XXX Looks like the TLB entries are `not quite LRU'. We need 447 * XXX to read more times than there are actual tags! 448 */ 449 for (i = 0; i < CIA_TLB_NTAGS + 4; i++) { 450 dummy = *((volatile uint64_t *) 451 ALPHA_PHYS_TO_K0SEG(CIA_PCI_DENSE + CIA_PYXIS_BUG_BASE + 452 (i * 65536))); 453 } 454 455 /* 456 * Restore normal PCI operation. 457 */ 458 alpha_mb(); 459 REGVAL(CIA_CSR_CTRL) = ctrl; 460 alpha_mb(); 461 462 splx(s); 463 } 464