1 /* $NetBSD: cia.c,v 1.72 2011/06/14 15:34:22 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 35 * All rights reserved. 36 * 37 * Author: Chris G. Demetriou 38 * 39 * Permission to use, copy, modify and distribute this software and 40 * its documentation is hereby granted, provided that both the copyright 41 * notice and this permission notice appear in all copies of the 42 * software, derivative works or modified versions, and any portions 43 * thereof, and that both notices appear in supporting documentation. 44 * 45 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 46 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 47 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 48 * 49 * Carnegie Mellon requests users of this software to return to 50 * 51 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 52 * School of Computer Science 53 * Carnegie Mellon University 54 * Pittsburgh PA 15213-3890 55 * 56 * any improvements or extensions that they make and grant Carnegie the 57 * rights to redistribute these changes. 58 */ 59 60 #include "opt_dec_eb164.h" 61 #include "opt_dec_kn20aa.h" 62 #include "opt_dec_550.h" 63 #include "opt_dec_1000a.h" 64 #include "opt_dec_1000.h" 65 66 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 67 68 __KERNEL_RCSID(0, "$NetBSD: cia.c,v 1.72 2011/06/14 15:34:22 matt Exp $"); 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/kernel.h> 73 #include <sys/malloc.h> 74 #include <sys/device.h> 75 76 #include <machine/autoconf.h> 77 #include <machine/rpb.h> 78 #include <machine/sysarch.h> 79 #include <machine/alpha.h> 80 81 #include <dev/isa/isareg.h> 82 #include <dev/isa/isavar.h> 83 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <alpha/pci/ciareg.h> 87 #include <alpha/pci/ciavar.h> 88 89 #ifdef DEC_KN20AA 90 #include <alpha/pci/pci_kn20aa.h> 91 #endif 92 #ifdef DEC_EB164 93 #include <alpha/pci/pci_eb164.h> 94 #endif 95 #ifdef DEC_550 96 #include <alpha/pci/pci_550.h> 97 #endif 98 #ifdef DEC_1000A 99 #include <alpha/pci/pci_1000a.h> 100 #endif 101 #ifdef DEC_1000 102 #include <alpha/pci/pci_1000.h> 103 #endif 104 105 int ciamatch(device_t, cfdata_t, void *); 106 void ciaattach(device_t, device_t, void *); 107 108 CFATTACH_DECL_NEW(cia, sizeof(struct cia_softc), 109 ciamatch, ciaattach, NULL, NULL); 110 111 extern struct cfdriver cia_cd; 112 113 int cia_bus_get_window(int, int, struct alpha_bus_space_translation *); 114 115 /* There can be only one. */ 116 int ciafound; 117 struct cia_config cia_configuration; 118 119 /* 120 * This determines if we attempt to use BWX for PCI bus and config space 121 * access. Some systems, notably with Pyxis, don't fare so well unless 122 * BWX is used. 123 * 124 * EXCEPT! Some devices have a really hard time if BWX is used (WHY?!). 125 * So, we decouple the uses for PCI config space and PCI bus space. 126 * 127 * FURTHERMORE! The Pyxis, most notably earlier revs, really don't 128 * do so well if you don't use BWX for bus access. So we default to 129 * forcing BWX on those chips. 130 * 131 * Geez. 132 */ 133 134 #ifndef CIA_PCI_USE_BWX 135 #define CIA_PCI_USE_BWX 1 136 #endif 137 138 #ifndef CIA_BUS_USE_BWX 139 #define CIA_BUS_USE_BWX 0 140 #endif 141 142 #ifndef CIA_PYXIS_FORCE_BWX 143 #define CIA_PYXIS_FORCE_BWX 0 144 #endif 145 146 int cia_pci_use_bwx = CIA_PCI_USE_BWX; 147 int cia_bus_use_bwx = CIA_BUS_USE_BWX; 148 int cia_pyxis_force_bwx = CIA_PYXIS_FORCE_BWX; 149 150 int 151 ciamatch(device_t parent, cfdata_t match, void *aux) 152 { 153 struct mainbus_attach_args *ma = aux; 154 155 /* Make sure that we're looking for a CIA. */ 156 if (strcmp(ma->ma_name, cia_cd.cd_name) != 0) 157 return (0); 158 159 if (ciafound) 160 return (0); 161 162 return (1); 163 } 164 165 /* 166 * Set up the chipset's function pointers. 167 */ 168 void 169 cia_init(struct cia_config *ccp, int mallocsafe) 170 { 171 int pci_use_bwx = cia_pci_use_bwx; 172 int bus_use_bwx = cia_bus_use_bwx; 173 174 ccp->cc_hae_mem = REGVAL(CIA_CSR_HAE_MEM); 175 ccp->cc_hae_io = REGVAL(CIA_CSR_HAE_IO); 176 ccp->cc_rev = REGVAL(CIA_CSR_REV) & REV_MASK; 177 178 /* 179 * Determine if we have a Pyxis. Only two systypes can 180 * have this: the EB164 systype (AlphaPC164LX and AlphaPC164SX) 181 * and the DEC_550 systype (Miata). 182 */ 183 if ((cputype == ST_EB164 && 184 (hwrpb->rpb_variation & SV_ST_MASK) >= SV_ST_ALPHAPC164LX_400) || 185 cputype == ST_DEC_550) { 186 ccp->cc_flags |= CCF_ISPYXIS; 187 if (cia_pyxis_force_bwx) 188 pci_use_bwx = bus_use_bwx = 1; 189 } 190 191 /* 192 * ALCOR/ALCOR2 Revisions >= 2 and Pyxis have the CNFG register. 193 */ 194 if (ccp->cc_rev >= 2 || (ccp->cc_flags & CCF_ISPYXIS) != 0) 195 ccp->cc_cnfg = REGVAL(CIA_CSR_CNFG); 196 else 197 ccp->cc_cnfg = 0; 198 199 /* 200 * Use BWX iff: 201 * 202 * - It hasn't been disbled by the user, 203 * - it's enabled in CNFG, 204 * - we're implementation version ev5, 205 * - BWX is enabled in the CPU's capabilities mask 206 */ 207 if ((pci_use_bwx || bus_use_bwx) && 208 (ccp->cc_cnfg & CNFG_BWEN) != 0 && 209 (cpu_amask & ALPHA_AMASK_BWX) != 0) { 210 u_int32_t ctrl; 211 212 if (pci_use_bwx) 213 ccp->cc_flags |= CCF_PCI_USE_BWX; 214 if (bus_use_bwx) 215 ccp->cc_flags |= CCF_BUS_USE_BWX; 216 217 /* 218 * For whatever reason, the firmware seems to enable PCI 219 * loopback mode if it also enables BWX. Make sure it's 220 * enabled if we have an old, buggy firmware rev. 221 */ 222 alpha_mb(); 223 ctrl = REGVAL(CIA_CSR_CTRL); 224 if ((ctrl & CTRL_PCI_LOOP_EN) == 0) { 225 REGVAL(CIA_CSR_CTRL) = ctrl | CTRL_PCI_LOOP_EN; 226 alpha_mb(); 227 } 228 } 229 230 if (!ccp->cc_initted) { 231 /* don't do these twice since they set up extents */ 232 if (ccp->cc_flags & CCF_BUS_USE_BWX) { 233 cia_bwx_bus_io_init(&ccp->cc_iot, ccp); 234 cia_bwx_bus_mem_init(&ccp->cc_memt, ccp); 235 236 /* 237 * We have one window for both PCI I/O and MEM 238 * in BWX mode. 239 */ 240 alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_IO] = 1; 241 alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_MEM] = 1; 242 } else { 243 cia_swiz_bus_io_init(&ccp->cc_iot, ccp); 244 cia_swiz_bus_mem_init(&ccp->cc_memt, ccp); 245 246 /* 247 * We have two I/O windows and 4 MEM windows in 248 * SWIZ mode. 249 */ 250 alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_IO] = 2; 251 alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_MEM] = 4; 252 } 253 alpha_bus_get_window = cia_bus_get_window; 254 } 255 ccp->cc_mallocsafe = mallocsafe; 256 257 cia_pci_init(&ccp->cc_pc, ccp); 258 alpha_pci_chipset = &ccp->cc_pc; 259 260 ccp->cc_initted = 1; 261 } 262 263 void 264 ciaattach(device_t parent, device_t self, void *aux) 265 { 266 struct cia_softc *sc = device_private(self); 267 struct cia_config *ccp; 268 struct pcibus_attach_args pba; 269 char bits[64]; 270 const char *name; 271 int pass; 272 273 /* note that we've attached the chipset; can't have 2 CIAs. */ 274 ciafound = 1; 275 sc->sc_dev = self; 276 277 /* 278 * set up the chipset's info; done once at console init time 279 * (maybe), but we must do it here as well to take care of things 280 * that need to use memory allocation. 281 */ 282 ccp = sc->sc_ccp = &cia_configuration; 283 cia_init(ccp, 1); 284 285 if (ccp->cc_flags & CCF_ISPYXIS) { 286 name = "Pyxis"; 287 pass = ccp->cc_rev; 288 } else { 289 name = "ALCOR/ALCOR2"; 290 pass = ccp->cc_rev + 1; 291 } 292 293 aprint_normal(": DECchip 2117x Core Logic Chipset (%s), pass %d\n", 294 name, pass); 295 if (ccp->cc_cnfg) { 296 snprintb(bits, sizeof(bits), CIA_CSR_CNFG_BITS, ccp->cc_cnfg); 297 aprint_normal_dev(self, "extended capabilities: %s\n", bits); 298 } 299 300 switch (ccp->cc_flags & (CCF_PCI_USE_BWX|CCF_BUS_USE_BWX)) { 301 case CCF_PCI_USE_BWX|CCF_BUS_USE_BWX: 302 name = "PCI config and bus"; 303 break; 304 case CCF_PCI_USE_BWX: 305 name = "PCI config"; 306 break; 307 case CCF_BUS_USE_BWX: 308 name = "bus"; 309 break; 310 default: 311 name = NULL; 312 break; 313 } 314 if (name != NULL) 315 aprint_normal_dev(self, "using BWX for %s access\n", name); 316 317 #ifdef DEC_550 318 if (cputype == ST_DEC_550 && 319 (hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) { 320 /* 321 * Miata 1 systems have a bug: DMA cannot cross 322 * an 8k boundary! Make sure PCI read prefetching 323 * is disabled on these chips. Note that secondary 324 * PCI busses don't have this problem, because of 325 * the way PPBs handle PCI read requests. 326 * 327 * In the 21174 Technical Reference Manual, this is 328 * actually documented as "Pyxis Pass 1", but apparently 329 * there are chips that report themselves as "Pass 1" 330 * which do not have the bug! Miatas with the Cypress 331 * PCI-ISA bridge (i.e. Miata 1.5 and Miata 2) do not 332 * have the bug, so we use this check. 333 * 334 * NOTE: This bug is actually worked around in cia_dma.c, 335 * when direct-mapped DMA maps are created. 336 * 337 * XXX WE NEED TO THINK ABOUT HOW TO HANDLE THIS FOR 338 * XXX SGMAP DMA MAPPINGS! 339 */ 340 u_int32_t ctrl; 341 342 /* XXX no bets... */ 343 aprint_error_dev(self, 344 "WARNING: Pyxis pass 1 DMA bug; no bets...\n"); 345 346 ccp->cc_flags |= CCF_PYXISBUG; 347 348 alpha_mb(); 349 ctrl = REGVAL(CIA_CSR_CTRL); 350 ctrl &= ~(CTRL_RD_TYPE|CTRL_RL_TYPE|CTRL_RM_TYPE); 351 REGVAL(CIA_CSR_CTRL) = ctrl; 352 alpha_mb(); 353 } 354 #endif /* DEC_550 */ 355 356 cia_dma_init(ccp); 357 358 switch (cputype) { 359 #ifdef DEC_KN20AA 360 case ST_DEC_KN20AA: 361 pci_kn20aa_pickintr(ccp); 362 break; 363 #endif 364 365 #ifdef DEC_EB164 366 case ST_EB164: 367 pci_eb164_pickintr(ccp); 368 break; 369 #endif 370 371 #ifdef DEC_550 372 case ST_DEC_550: 373 pci_550_pickintr(ccp); 374 break; 375 #endif 376 377 #ifdef DEC_1000A 378 case ST_DEC_1000A: 379 pci_1000a_pickintr(ccp, &ccp->cc_iot, &ccp->cc_memt, 380 &ccp->cc_pc); 381 break; 382 #endif 383 384 #ifdef DEC_1000 385 case ST_DEC_1000: 386 pci_1000_pickintr(ccp, &ccp->cc_iot, &ccp->cc_memt, 387 &ccp->cc_pc); 388 break; 389 #endif 390 391 default: 392 panic("ciaattach: shouldn't be here, really..."); 393 } 394 395 pba.pba_iot = &ccp->cc_iot; 396 pba.pba_memt = &ccp->cc_memt; 397 pba.pba_dmat = 398 alphabus_dma_get_tag(&ccp->cc_dmat_direct, ALPHA_BUS_PCI); 399 pba.pba_dmat64 = NULL; 400 pba.pba_pc = &ccp->cc_pc; 401 pba.pba_bus = 0; 402 pba.pba_bridgetag = NULL; 403 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY; 404 if ((ccp->cc_flags & CCF_PYXISBUG) == 0) 405 pba.pba_flags |= PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | 406 PCI_FLAGS_MWI_OKAY; 407 config_found_ia(self, "pcibus", &pba, pcibusprint); 408 } 409 410 int 411 cia_bus_get_window(int type, int window, struct alpha_bus_space_translation *abst) 412 { 413 struct cia_config *ccp = &cia_configuration; 414 bus_space_tag_t st; 415 416 switch (type) { 417 case ALPHA_BUS_TYPE_PCI_IO: 418 st = &ccp->cc_iot; 419 break; 420 421 case ALPHA_BUS_TYPE_PCI_MEM: 422 st = &ccp->cc_memt; 423 break; 424 425 default: 426 panic("cia_bus_get_window"); 427 } 428 429 return (alpha_bus_space_get_window(st, window, abst)); 430 } 431 432 void 433 cia_pyxis_intr_enable(int irq, int onoff) 434 { 435 u_int64_t imask; 436 int s; 437 438 #if 0 439 printf("cia_pyxis_intr_enable: %s %d\n", 440 onoff ? "enabling" : "disabling", irq); 441 #endif 442 443 s = splhigh(); 444 alpha_mb(); 445 imask = REGVAL64(PYXIS_INT_MASK); 446 if (onoff) 447 imask |= (1UL << irq); 448 else 449 imask &= ~(1UL << irq); 450 REGVAL64(PYXIS_INT_MASK) = imask; 451 alpha_mb(); 452 splx(s); 453 } 454