1 /* $NetBSD: alpha_cpu.h,v 1.49 2010/10/07 19:55:02 hans Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #ifndef __ALPHA_ALPHA_CPU_H__ 31 #define __ALPHA_ALPHA_CPU_H__ 32 33 /* 34 * Alpha CPU + OSF/1 PALcode definitions for use by the kernel. 35 * 36 * Definitions for: 37 * 38 * Process Control Block 39 * Interrupt/Exception/Syscall Stack Frame 40 * Processor Status Register 41 * Machine Check Error Summary Register 42 * Machine Check Logout Area 43 * Per CPU state Management of Machine Check Handling 44 * Virtual Memory Management 45 * Kernel Entry Vectors 46 * MMCSR Fault Type Codes 47 * Translation Buffer Invalidation 48 * 49 * and miscellaneous PALcode operations. 50 */ 51 52 53 /* 54 * Process Control Block definitions [OSF/1 PALcode Specific] 55 */ 56 57 struct alpha_pcb { 58 unsigned long apcb_ksp; /* kernel stack ptr */ 59 unsigned long apcb_usp; /* user stack ptr */ 60 unsigned long apcb_ptbr; /* page table base reg */ 61 unsigned int apcb_cpc; /* charged process cycles */ 62 unsigned int apcb_asn; /* address space number */ 63 unsigned long apcb_unique; /* process unique value */ 64 #define apcb_backup_ksp apcb_unique /* backup kernel stack ptr */ 65 unsigned long apcb_flags; /* flags; see below */ 66 unsigned long apcb_decrsv0; /* DEC reserved */ 67 unsigned long apcb_decrsv1; /* DEC reserved */ 68 }; 69 70 #define ALPHA_PCB_FLAGS_FEN 0x0000000000000001 71 #define ALPHA_PCB_FLAGS_PME 0x4000000000000000 72 73 /* 74 * Interrupt/Exception/Syscall "Hardware" (really PALcode) 75 * Stack Frame definitions 76 * 77 * These are quadword offsets from the sp on kernel entry, i.e. 78 * to get to the value in question you access (sp + (offset * 8)). 79 * 80 * On syscall entry, A0-A2 aren't written to memory but space 81 * _is_ reserved for them. 82 */ 83 84 #define ALPHA_HWFRAME_PS 0 /* processor status register */ 85 #define ALPHA_HWFRAME_PC 1 /* program counter */ 86 #define ALPHA_HWFRAME_GP 2 /* global pointer */ 87 #define ALPHA_HWFRAME_A0 3 /* a0 */ 88 #define ALPHA_HWFRAME_A1 4 /* a1 */ 89 #define ALPHA_HWFRAME_A2 5 /* a2 */ 90 91 #define ALPHA_HWFRAME_SIZE 6 /* 6 8-byte words */ 92 93 /* 94 * Processor Status Register [OSF/1 PALcode Specific] 95 * 96 * Includes user/kernel mode bit, interrupt priority levels, etc. 97 */ 98 99 #define ALPHA_PSL_USERMODE 0x0008 /* set -> user mode */ 100 #define ALPHA_PSL_IPL_MASK 0x0007 /* interrupt level mask */ 101 102 #define ALPHA_PSL_IPL_0 0x0000 /* all interrupts enabled */ 103 #define ALPHA_PSL_IPL_SOFT 0x0001 /* software ints disabled */ 104 #define ALPHA_PSL_IPL_IO 0x0004 /* I/O dev ints disabled */ 105 #define ALPHA_PSL_IPL_CLOCK 0x0005 /* clock ints disabled */ 106 #define ALPHA_PSL_IPL_HIGH 0x0006 /* all but mchecks disabled */ 107 108 #define ALPHA_PSL_MUST_BE_ZERO 0xfffffffffffffff0 109 110 /* Convenience constants: what must be set/clear in user mode */ 111 #define ALPHA_PSL_USERSET ALPHA_PSL_USERMODE 112 #define ALPHA_PSL_USERCLR (ALPHA_PSL_MUST_BE_ZERO | ALPHA_PSL_IPL_MASK) 113 114 /* 115 * Interrupt Type Code Definitions [OSF/1 PALcode Specific] 116 */ 117 118 #define ALPHA_INTR_XPROC 0 /* interprocessor interrupt */ 119 #define ALPHA_INTR_CLOCK 1 /* clock interrupt */ 120 #define ALPHA_INTR_ERROR 2 /* correctable error or mcheck */ 121 #define ALPHA_INTR_DEVICE 3 /* device interrupt */ 122 #define ALPHA_INTR_PERF 4 /* performance counter */ 123 #define ALPHA_INTR_PASSIVE 5 /* passive release */ 124 125 /* 126 * Machine Check Error Summary Register definitions [OSF/1 PALcode Specific] 127 * 128 * The following bits are values as read. On write, _PCE, _SCE, and 129 * _MIP are "write 1 to clear." 130 */ 131 132 #define ALPHA_MCES_IMP \ 133 0xffffffff00000000 /* impl. dependent */ 134 #define ALPHA_MCES_RSVD \ 135 0x00000000ffffffe0 /* reserved */ 136 #define ALPHA_MCES_DSC \ 137 0x0000000000000010 /* disable system correctable error reporting */ 138 #define ALPHA_MCES_DPC \ 139 0x0000000000000008 /* disable processor correctable error reporting */ 140 #define ALPHA_MCES_PCE \ 141 0x0000000000000004 /* processor correctable error in progress */ 142 #define ALPHA_MCES_SCE \ 143 0x0000000000000002 /* system correctable error in progress */ 144 #define ALPHA_MCES_MIP \ 145 0x0000000000000001 /* machine check in progress */ 146 147 /* 148 * Machine Check Error Summary Register definitions [OSF/1 PALcode Specific] 149 * 150 * Note that these are *generic* OSF/1 PALcode specific defines. There are 151 * platform variations to these entities. 152 */ 153 154 struct alpha_logout_area { 155 unsigned int la_frame_size; /* frame size */ 156 unsigned int la_flags; /* flags; see below */ 157 unsigned int la_cpu_offset; /* offset to cpu area */ 158 unsigned int la_system_offset; /* offset to system area */ 159 }; 160 161 #define ALPHA_LOGOUT_FLAGS_RETRY 0x80000000 /* OK to continue */ 162 #define ALPHA_LOGOUT_FLAGS_SE 0x40000000 /* second error */ 163 #define ALPHA_LOGOUT_FLAGS_SBZ 0x3fffffff /* should be zero */ 164 165 #define ALPHA_LOGOUT_NOT_BUILT \ 166 (struct alpha_logout_area *)0xffffffffffffffff) 167 168 #define ALPHA_LOGOUT_PAL_AREA(lap) \ 169 (unsigned long *)((unsigned char *)(lap) + 16) 170 #define ALPHA_LOGOUT_PAL_SIZE(lap) \ 171 ((lap)->la_cpu_offset - 16) 172 #define ALPHA_LOGOUT_CPU_AREA(lap) \ 173 (unsigned long *)((unsigned char *)(lap) + (lap)->la_cpu_offset) 174 #define ALPHA_LOGOUT_CPU_SIZE(lap) \ 175 ((lap)->la_system_offset - (lap)->la_cpu_offset) 176 #define ALPHA_LOGOUT_SYSTEM_AREA(lap) \ 177 (unsigned long *)((unsigned char *)(lap) + (lap)->la_system_offset) 178 #define ALPHA_LOGOUT_SYSTEM_SIZE(lap) \ 179 ((lap)->la_frame_size - (lap)->la_system_offset) 180 181 /* types of machine checks */ 182 #define ALPHA_SYS_ERROR 0x620 /* System correctable error */ 183 #define ALPHA_PROC_ERROR 0x630 /* Processor correctable error */ 184 #define ALPHA_SYS_MCHECK 0x660 /* System machine check */ 185 #define ALPHA_PROC_MCHECK 0x670 /* Processor machine check */ 186 #define ALPHA_ENV_MCHECK 0x680 /* Environmental error */ 187 188 /* 189 * Virtual Memory Management definitions [OSF/1 PALcode Specific] 190 * 191 * Includes user and kernel space addresses and information, 192 * page table entry definitions, etc. 193 * 194 * NOTE THAT THESE DEFINITIONS MAY CHANGE IN FUTURE ALPHA CPUS! 195 */ 196 197 #define ALPHA_PGSHIFT 13 198 #define ALPHA_PGBYTES (1 << ALPHA_PGSHIFT) 199 200 #define ALPHA_USEG_BASE 0 /* virtual */ 201 #define ALPHA_USEG_END 0x000003ffffffffff 202 203 #define ALPHA_K0SEG_BASE 0xfffffc0000000000 /* direct-mapped */ 204 #define ALPHA_K0SEG_END 0xfffffdffffffffff 205 #define ALPHA_K1SEG_BASE 0xfffffe0000000000 /* virtual */ 206 #define ALPHA_K1SEG_END 0xffffffffffffffff 207 208 #define ALPHA_K0SEG_TO_PHYS(x) ((x) & ~ALPHA_K0SEG_BASE) 209 #define ALPHA_PHYS_TO_K0SEG(x) ((x) | ALPHA_K0SEG_BASE) 210 211 #define ALPHA_PTE_VALID 0x0001 212 213 #define ALPHA_PTE_FAULT_ON_READ 0x0002 214 #define ALPHA_PTE_FAULT_ON_WRITE 0x0004 215 #define ALPHA_PTE_FAULT_ON_EXECUTE 0x0008 216 217 #define ALPHA_PTE_ASM 0x0010 /* addr. space match */ 218 #define ALPHA_PTE_GRANULARITY 0x0060 /* granularity hint */ 219 220 #define ALPHA_PTE_PROT 0xff00 221 #define ALPHA_PTE_KR 0x0100 222 #define ALPHA_PTE_UR 0x0200 223 #define ALPHA_PTE_KW 0x1000 224 #define ALPHA_PTE_UW 0x2000 225 226 #define ALPHA_PTE_WRITE (ALPHA_PTE_KW | ALPHA_PTE_UW) 227 228 #define ALPHA_PTE_SOFTWARE 0x00000000ffff0000 229 #define ALPHA_PTE_PALCODE (~ALPHA_PTE_SOFTWARE) /* shorthand */ 230 231 #define ALPHA_PTE_PFN 0xffffffff00000000 232 233 #define ALPHA_PTE_TO_PFN(pte) ((pte) >> 32) 234 #define ALPHA_PTE_FROM_PFN(pfn) ((pfn) << 32) 235 236 typedef unsigned long alpha_pt_entry_t; 237 238 /* 239 * Kernel Entry Vectors. [OSF/1 PALcode Specific] 240 */ 241 242 #define ALPHA_KENTRY_INT 0 243 #define ALPHA_KENTRY_ARITH 1 244 #define ALPHA_KENTRY_MM 2 245 #define ALPHA_KENTRY_IF 3 246 #define ALPHA_KENTRY_UNA 4 247 #define ALPHA_KENTRY_SYS 5 248 249 /* 250 * MMCSR Fault Type Codes. [OSF/1 PALcode Specific] 251 */ 252 253 #define ALPHA_MMCSR_INVALTRANS 0 254 #define ALPHA_MMCSR_ACCESS 1 255 #define ALPHA_MMCSR_FOR 2 256 #define ALPHA_MMCSR_FOE 3 257 #define ALPHA_MMCSR_FOW 4 258 259 /* 260 * Instruction Fault Type Codes. [OSF/1 PALcode Specific] 261 */ 262 263 #define ALPHA_IF_CODE_BPT 0 264 #define ALPHA_IF_CODE_BUGCHK 1 265 #define ALPHA_IF_CODE_GENTRAP 2 266 #define ALPHA_IF_CODE_FEN 3 267 #define ALPHA_IF_CODE_OPDEC 4 268 269 #ifdef _KERNEL 270 271 /* 272 * Translation Buffer Invalidation definitions [OSF/1 PALcode Specific] 273 */ 274 275 #define ALPHA_TBIA() alpha_pal_tbi(-2, 0) /* all TB entries */ 276 #define ALPHA_TBIAP() alpha_pal_tbi(-1, 0) /* all per-process */ 277 #define ALPHA_TBISI(va) alpha_pal_tbi(1, (va)) /* ITB entry for va */ 278 #define ALPHA_TBISD(va) alpha_pal_tbi(2, (va)) /* DTB entry for va */ 279 #define ALPHA_TBIS(va) alpha_pal_tbi(3, (va)) /* all for va */ 280 281 #endif /* _KERNEL */ 282 283 /* 284 * Bits used in the amask instruction [EV56 and later] 285 */ 286 287 #define ALPHA_AMASK_BWX 0x0001 /* byte/word extension */ 288 #define ALPHA_AMASK_FIX 0x0002 /* floating point conv. ext. */ 289 #define ALPHA_AMASK_CIX 0x0004 /* count extension */ 290 #define ALPHA_AMASK_MVI 0x0100 /* multimedia extension */ 291 #define ALPHA_AMASK_PAT 0x0200 /* precise arith. traps */ 292 #define ALPHA_AMASK_PMI 0x1000 /* prefetch w/ modify intent */ 293 294 #define ALPHA_AMASK_ALL (ALPHA_AMASK_BWX|ALPHA_AMASK_FIX| \ 295 ALPHA_AMASK_CIX|ALPHA_AMASK_MVI| \ 296 ALPHA_AMASK_PAT|ALPHA_AMASK_PMI) 297 298 #define ALPHA_AMASK_BITS \ 299 "\20\17PMI\12PAT\11MVI\3CIX\2FIX\1BWX" 300 301 /* 302 * Chip family IDs returned by implver instruction 303 */ 304 305 #define ALPHA_IMPLVER_EV4 0 /* LCA/EV4/EV45 */ 306 #define ALPHA_IMPLVER_EV5 1 /* EV5/EV56/PCA56 */ 307 #define ALPHA_IMPLVER_EV6 2 /* EV6 */ 308 #define ALPHA_IMPLVER_EV7 3 /* EV7/EV79 */ 309 310 #ifdef _KERNEL 311 312 /* 313 * Maximum processor ID we allow from `whami', and related constants. 314 * 315 * XXX This is not really processor or PALcode specific, but this is 316 * a convenient place to put these definitions. 317 * 318 * XXX This is clipped at 63 so that we can use `long's for proc bitmasks. 319 */ 320 321 #define ALPHA_WHAMI_MAXID 63 322 #define ALPHA_MAXPROCS (ALPHA_WHAMI_MAXID + 1) 323 324 /* 325 * Misc. support routines. 326 */ 327 const char *alpha_dsr_sysname(void); 328 329 /* 330 * Stubs for Alpha instructions normally inaccessible from C. 331 */ 332 unsigned long alpha_amask(unsigned long); 333 unsigned long alpha_implver(void); 334 335 #endif /* _KERNEL */ 336 337 /* XXX Expose the insn wrappers to userspace, for now. */ 338 339 static __inline unsigned long 340 alpha_rpcc(void) 341 { 342 unsigned long v0; 343 344 __asm volatile("rpcc %0" : "=r" (v0)); 345 return (v0); 346 } 347 348 #define alpha_mb() __asm volatile("mb" : : : "memory") 349 #define alpha_wmb() __asm volatile("mb" : : : "memory") /* XXX */ 350 351 #if defined(_KERNEL) || defined(_STANDALONE) 352 353 /* 354 * Stubs for OSF/1 PALcode operations. 355 */ 356 #include <machine/pal.h> 357 358 void alpha_pal_cflush(unsigned long); 359 void alpha_pal_halt(void) __attribute__((__noreturn__)); 360 unsigned long _alpha_pal_swpipl(unsigned long); /* for profiling */ 361 void alpha_pal_wrent(void *, unsigned long); 362 void alpha_pal_wrvptptr(unsigned long); 363 364 #define alpha_pal_draina() __asm volatile("call_pal %0 # PAL_draina" \ 365 : : "i" (PAL_draina) : "memory") 366 367 #define alpha_pal_imb() __asm volatile("call_pal %0 # PAL_imb" \ 368 : : "i" (PAL_imb) : "memory") 369 370 static __inline unsigned long 371 alpha_pal_rdmces(void) 372 { 373 register unsigned long v0 __asm("$0"); 374 375 __asm volatile("call_pal %1 # PAL_OSF1_rdmces" 376 : "=r" (v0) 377 : "i" (PAL_OSF1_rdmces) 378 /* clobbers t0, t8..t11 */ 379 : "$1", "$22", "$23", "$24", "$25"); 380 381 return (v0); 382 } 383 384 static __inline unsigned long 385 alpha_pal_rdps(void) 386 { 387 register unsigned long v0 __asm("$0"); 388 389 __asm volatile("call_pal %1 # PAL_OSF1_rdps" 390 : "=r" (v0) 391 : "i" (PAL_OSF1_rdps) 392 /* clobbers t0, t8..t11 */ 393 : "$1", "$22", "$23", "$24", "$25"); 394 395 return (v0); 396 } 397 398 static __inline unsigned long 399 alpha_pal_rdunique(void) 400 { 401 register unsigned long v0 __asm("$0"); 402 403 __asm volatile("call_pal %1 # PAL_rdunique" 404 : "=r" (v0) 405 : "i" (PAL_rdunique)); 406 407 return (v0); 408 } 409 410 static __inline unsigned long 411 alpha_pal_rdusp(void) 412 { 413 register unsigned long v0 __asm("$0"); 414 415 __asm volatile("call_pal %1 # PAL_OSF1_rdusp" 416 : "=r" (v0) 417 : "i" (PAL_OSF1_rdusp) 418 /* clobbers t0, t8..t11 */ 419 : "$1", "$22", "$23", "$24", "$25"); 420 421 return (v0); 422 } 423 424 static __inline unsigned long 425 alpha_pal_rdval(void) 426 { 427 register unsigned long v0 __asm("$0"); 428 429 __asm volatile("call_pal %1 # PAL_OSF1_rdval" 430 : "=r" (v0) 431 : "i" (PAL_OSF1_rdval) 432 /* clobbers t0, t8..t11 */ 433 : "$1", "$22", "$23", "$24", "$25"); 434 435 return (v0); 436 } 437 438 static __inline unsigned long 439 alpha_pal_swpctx(unsigned long ctx) 440 { 441 register unsigned long a0 __asm("$16") = ctx; 442 register unsigned long v0 __asm("$0"); 443 444 __asm volatile("call_pal %2 # PAL_OSF1_swpctx" 445 : "=r" (a0), "=r" (v0) 446 : "i" (PAL_OSF1_swpctx), "0" (a0) 447 /* clobbers t0, t8..t11, a0 (above) */ 448 : "$1", "$22", "$23", "$24", "$25", "memory"); 449 450 return (v0); 451 } 452 453 static __inline unsigned long 454 alpha_pal_swpipl(unsigned long ipl) 455 { 456 register unsigned long a0 __asm("$16") = ipl; 457 register unsigned long v0 __asm("$0"); 458 459 __asm volatile("call_pal %2 # PAL_OSF1_swpipl" 460 : "=r" (a0), "=r" (v0) 461 : "i" (PAL_OSF1_swpipl), "0" (a0) 462 /* clobbers t0, t8..t11, a0 (above) */ 463 : "$1", "$22", "$23", "$24", "$25", "memory"); 464 465 return (v0); 466 } 467 468 static __inline void 469 alpha_pal_tbi(unsigned long op, vaddr_t va) 470 { 471 register unsigned long a0 __asm("$16") = op; 472 register unsigned long a1 __asm("$17") = va; 473 474 __asm volatile("call_pal %2 # PAL_OSF1_tbi" 475 : "=r" (a0), "=r" (a1) 476 : "i" (PAL_OSF1_tbi), "0" (a0), "1" (a1) 477 /* clobbers t0, t8..t11, a0 (above), a1 (above) */ 478 : "$1", "$22", "$23", "$24", "$25"); 479 } 480 481 static __inline unsigned long 482 alpha_pal_whami(void) 483 { 484 register unsigned long v0 __asm("$0"); 485 486 __asm volatile("call_pal %1 # PAL_OSF1_whami" 487 : "=r" (v0) 488 : "i" (PAL_OSF1_whami) 489 /* clobbers t0, t8..t11 */ 490 : "$1", "$22", "$23", "$24", "$25"); 491 492 return (v0); 493 } 494 495 static __inline void 496 alpha_pal_wrfen(unsigned long onoff) 497 { 498 register unsigned long a0 __asm("$16") = onoff; 499 500 __asm volatile("call_pal %1 # PAL_OSF1_wrfen" 501 : "=r" (a0) 502 : "i" (PAL_OSF1_wrfen), "0" (a0) 503 /* clobbers t0, t8..t11, a0 (above) */ 504 : "$1", "$22", "$23", "$24", "$25"); 505 } 506 507 static __inline void 508 alpha_pal_wripir(unsigned long cpu_id) 509 { 510 register unsigned long a0 __asm("$16") = cpu_id; 511 512 __asm volatile("call_pal %1 # PAL_ipir" 513 : "=r" (a0) 514 : "i" (PAL_ipir), "0" (a0) 515 /* clobbers t0, t8..t11, a0 (above) */ 516 : "$1", "$22", "$23", "$24", "$25"); 517 } 518 519 static __inline void 520 alpha_pal_wrunique(unsigned long unique) 521 { 522 register unsigned long a0 __asm("$16") = unique; 523 524 __asm volatile("call_pal %1 # PAL_wrunique" 525 : "=r" (a0) 526 : "i" (PAL_wrunique), "0" (a0)); 527 } 528 529 static __inline void 530 alpha_pal_wrusp(unsigned long usp) 531 { 532 register unsigned long a0 __asm("$16") = usp; 533 534 __asm volatile("call_pal %1 # PAL_OSF1_wrusp" 535 : "=r" (a0) 536 : "i" (PAL_OSF1_wrusp), "0" (a0) 537 /* clobbers t0, t8..t11, a0 (above) */ 538 : "$1", "$22", "$23", "$24", "$25"); 539 } 540 541 static __inline void 542 alpha_pal_wrmces(unsigned long mces) 543 { 544 register unsigned long a0 __asm("$16") = mces; 545 546 __asm volatile("call_pal %1 # PAL_OSF1_wrmces" 547 : "=r" (a0) 548 : "i" (PAL_OSF1_wrmces), "0" (a0) 549 /* clobbers t0, t8..t11 */ 550 : "$1", "$22", "$23", "$24", "$25"); 551 } 552 553 static __inline void 554 alpha_pal_wrval(unsigned long val) 555 { 556 register unsigned long a0 __asm("$16") = val; 557 558 __asm volatile("call_pal %1 # PAL_OSF1_wrval" 559 : "=r" (a0) 560 : "i" (PAL_OSF1_wrval), "0" (a0) 561 /* clobbers t0, t8..t11, a0 (above) */ 562 : "$1", "$22", "$23", "$24", "$25"); 563 } 564 565 #endif /* _KERNEL */ 566 567 #endif /* __ALPHA_ALPHA_CPU_H__ */ 568