1*605f564fSmsaitoh /* $NetBSD: vtpbc.c,v 1.10 2015/10/02 05:22:49 msaitoh Exp $ */
216b9c606Sthorpej
316b9c606Sthorpej /*-
416b9c606Sthorpej * Copyright (c) 2001 The NetBSD Foundation, Inc.
516b9c606Sthorpej * All rights reserved.
616b9c606Sthorpej *
716b9c606Sthorpej * This code is derived from software contributed to The NetBSD Foundation
816b9c606Sthorpej * by Jason R. Thorpe.
916b9c606Sthorpej *
1016b9c606Sthorpej * Redistribution and use in source and binary forms, with or without
1116b9c606Sthorpej * modification, are permitted provided that the following conditions
1216b9c606Sthorpej * are met:
1316b9c606Sthorpej * 1. Redistributions of source code must retain the above copyright
1416b9c606Sthorpej * notice, this list of conditions and the following disclaimer.
1516b9c606Sthorpej * 2. Redistributions in binary form must reproduce the above copyright
1616b9c606Sthorpej * notice, this list of conditions and the following disclaimer in the
1716b9c606Sthorpej * documentation and/or other materials provided with the distribution.
1816b9c606Sthorpej *
1916b9c606Sthorpej * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
2016b9c606Sthorpej * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
2116b9c606Sthorpej * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
2216b9c606Sthorpej * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
2316b9c606Sthorpej * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
2416b9c606Sthorpej * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
2516b9c606Sthorpej * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
2616b9c606Sthorpej * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
2716b9c606Sthorpej * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
2816b9c606Sthorpej * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
2916b9c606Sthorpej * POSSIBILITY OF SUCH DAMAGE.
3016b9c606Sthorpej */
3116b9c606Sthorpej
3216b9c606Sthorpej /*
3316b9c606Sthorpej * Support for the V3 Semiconductor i960 PCI bus controller. This appears
3416b9c606Sthorpej * on some MIPS boards (notably Algorithmics P-4032 and P-5064).
3516b9c606Sthorpej *
3616b9c606Sthorpej * Some help was provided by the Algorithmics PMON sources.
3716b9c606Sthorpej */
3816b9c606Sthorpej
396fdfc66cSlukem #include <sys/cdefs.h>
40*605f564fSmsaitoh __KERNEL_RCSID(0, "$NetBSD: vtpbc.c,v 1.10 2015/10/02 05:22:49 msaitoh Exp $");
416fdfc66cSlukem
4216b9c606Sthorpej #include <sys/param.h>
4316b9c606Sthorpej #include <sys/systm.h>
4416b9c606Sthorpej #include <sys/device.h>
4516b9c606Sthorpej
46e265f67bSdyoung #include <sys/bus.h>
4716b9c606Sthorpej #include <machine/intr.h>
4816b9c606Sthorpej #include <machine/locore.h>
4916b9c606Sthorpej
5016b9c606Sthorpej #include <dev/pci/pcireg.h>
5116b9c606Sthorpej #include <dev/pci/pcivar.h>
5216b9c606Sthorpej
5316b9c606Sthorpej #include <algor/pci/vtpbcreg.h>
5416b9c606Sthorpej #include <algor/pci/vtpbcvar.h>
5516b9c606Sthorpej
5616b9c606Sthorpej struct vtpbc_config vtpbc_configuration;
5716b9c606Sthorpej
5816b9c606Sthorpej #define PCI_CONF_LOCK(s) (s) = splhigh()
5916b9c606Sthorpej #define PCI_CONF_UNLOCK(s) splx((s))
6016b9c606Sthorpej
6116b9c606Sthorpej const char *vtpbc_revs[] = {
6216b9c606Sthorpej "A",
6316b9c606Sthorpej "B0",
6416b9c606Sthorpej "B1",
6516b9c606Sthorpej "B2",
6616b9c606Sthorpej "C0",
6716b9c606Sthorpej };
6816b9c606Sthorpej const int vtpbc_nrevs = sizeof(vtpbc_revs) / sizeof(vtpbc_revs[0]);
6916b9c606Sthorpej
70cbab9cadSchs void vtpbc_attach_hook(device_t, device_t,
7116b9c606Sthorpej struct pcibus_attach_args *);
7216b9c606Sthorpej int vtpbc_bus_maxdevs(void *, int);
7316b9c606Sthorpej pcitag_t vtpbc_make_tag(void *, int, int, int);
7416b9c606Sthorpej void vtpbc_decompose_tag(void *, pcitag_t, int *, int *, int *);
7516b9c606Sthorpej pcireg_t vtpbc_conf_read(void *, pcitag_t, int);
7616b9c606Sthorpej void vtpbc_conf_write(void *, pcitag_t, int, pcireg_t);
7716b9c606Sthorpej
7816b9c606Sthorpej /*
7916b9c606Sthorpej * vtpbc_init:
8016b9c606Sthorpej *
8116b9c606Sthorpej * Initialize the V3 PCI controller's software state. We
8216b9c606Sthorpej * simply use the existing windows that the firmware has
8316b9c606Sthorpej * set up for us.
8416b9c606Sthorpej */
8516b9c606Sthorpej void
vtpbc_init(pci_chipset_tag_t pc,struct vtpbc_config * vt)8616b9c606Sthorpej vtpbc_init(pci_chipset_tag_t pc, struct vtpbc_config *vt)
8716b9c606Sthorpej {
8816b9c606Sthorpej
8916b9c606Sthorpej pc->pc_conf_v = vt;
9016b9c606Sthorpej pc->pc_attach_hook = vtpbc_attach_hook;
9116b9c606Sthorpej pc->pc_bus_maxdevs = vtpbc_bus_maxdevs;
9216b9c606Sthorpej pc->pc_make_tag = vtpbc_make_tag;
9316b9c606Sthorpej pc->pc_decompose_tag = vtpbc_decompose_tag;
9416b9c606Sthorpej pc->pc_conf_read = vtpbc_conf_read;
9516b9c606Sthorpej pc->pc_conf_write = vtpbc_conf_write;
9616b9c606Sthorpej
9716b9c606Sthorpej vt->vt_rev = V96X_PCI_CC_REV(vt) & V96X_PCI_CC_REV_VREV;
9880dfaa3eSthorpej
9980dfaa3eSthorpej /*
100fe87c9aaSthorpej * Determine the PCI I/O space base that our PCI
101fe87c9aaSthorpej * I/O window maps to. NOTE: We disable this on
102fe87c9aaSthorpej * PBC rev < B2.
103fe87c9aaSthorpej *
104fe87c9aaSthorpej * Also note that PMON has disabled the I/O space
105fe87c9aaSthorpej * if the old-style PCI address map is in-use.
106fe87c9aaSthorpej */
107fe87c9aaSthorpej if (vt->vt_rev < V96X_VREV_B2)
108fe87c9aaSthorpej vt->vt_pci_iobase = (bus_addr_t) -1;
109fe87c9aaSthorpej else {
110fe87c9aaSthorpej if ((V96X_LB_BASE2(vt) & V96X_LB_BASEx_ENABLE) == 0)
111fe87c9aaSthorpej vt->vt_pci_iobase = (bus_addr_t) -1;
112fe87c9aaSthorpej else
113fe87c9aaSthorpej vt->vt_pci_iobase =
114fe87c9aaSthorpej (V96X_LB_MAP2(vt) & V96X_LB_MAPx_MAP_ADR) << 16;
115fe87c9aaSthorpej }
116fe87c9aaSthorpej
117fe87c9aaSthorpej /*
11880dfaa3eSthorpej * Determine the PCI memory space base that our PCI
11980dfaa3eSthorpej * memory window maps to.
12080dfaa3eSthorpej */
12180dfaa3eSthorpej vt->vt_pci_membase = (V96X_LB_MAP1(vt) & V96X_LB_MAPx_MAP_ADR) << 16;
12280dfaa3eSthorpej
12380dfaa3eSthorpej /*
12480dfaa3eSthorpej * Determine the PCI window base that maps host RAM for
12580dfaa3eSthorpej * DMA.
12680dfaa3eSthorpej */
12780dfaa3eSthorpej vt->vt_dma_winbase = V96X_PCI_BASE1(vt) & 0xfffffff0;
12816b9c606Sthorpej }
12916b9c606Sthorpej
13016b9c606Sthorpej void
vtpbc_attach_hook(device_t parent,device_t self,struct pcibus_attach_args * pba)131cbab9cadSchs vtpbc_attach_hook(device_t parent, device_t self,
13216b9c606Sthorpej struct pcibus_attach_args *pba)
13316b9c606Sthorpej {
13416b9c606Sthorpej }
13516b9c606Sthorpej
13616b9c606Sthorpej int
vtpbc_bus_maxdevs(void * v,int busno)13716b9c606Sthorpej vtpbc_bus_maxdevs(void *v, int busno)
13816b9c606Sthorpej {
13916b9c606Sthorpej
14016b9c606Sthorpej return (32);
14116b9c606Sthorpej }
14216b9c606Sthorpej
14316b9c606Sthorpej pcitag_t
vtpbc_make_tag(void * v,int b,int d,int f)14416b9c606Sthorpej vtpbc_make_tag(void *v, int b, int d, int f)
14516b9c606Sthorpej {
14616b9c606Sthorpej
14716b9c606Sthorpej return ((b << 16) | (d << 11) | (f << 8));
14816b9c606Sthorpej }
14916b9c606Sthorpej
15016b9c606Sthorpej void
vtpbc_decompose_tag(void * v,pcitag_t tag,int * bp,int * dp,int * fp)15116b9c606Sthorpej vtpbc_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
15216b9c606Sthorpej {
15316b9c606Sthorpej
15416b9c606Sthorpej if (bp != NULL)
15516b9c606Sthorpej *bp = (tag >> 16) & 0xff;
15616b9c606Sthorpej if (dp != NULL)
15716b9c606Sthorpej *dp = (tag >> 11) & 0x1f;
15816b9c606Sthorpej if (fp != NULL)
15916b9c606Sthorpej *fp = (tag >> 8) & 0x7;
16016b9c606Sthorpej }
16116b9c606Sthorpej
16216b9c606Sthorpej static int
vtpbc_conf_addr(struct vtpbc_config * vt,pcitag_t tag,int offset,u_int32_t * cfgoff,u_int32_t * ad_low)16316b9c606Sthorpej vtpbc_conf_addr(struct vtpbc_config *vt, pcitag_t tag, int offset,
16416b9c606Sthorpej u_int32_t *cfgoff, u_int32_t *ad_low)
16516b9c606Sthorpej {
16616b9c606Sthorpej int b, d, f;
16716b9c606Sthorpej
168*605f564fSmsaitoh if ((unsigned int)offset >= PCI_CONF_SIZE)
169*605f564fSmsaitoh return (1);
170*605f564fSmsaitoh
17116b9c606Sthorpej vtpbc_decompose_tag(vt, tag, &b, &d, &f);
17216b9c606Sthorpej
17316b9c606Sthorpej if (b == 0) {
17416b9c606Sthorpej if (d > (31 - vt->vt_adbase))
17516b9c606Sthorpej return (1);
17616b9c606Sthorpej *cfgoff = (1UL << (d + vt->vt_adbase)) | (f << 8) |
17716b9c606Sthorpej offset;
17816b9c606Sthorpej *ad_low = 0;
17916b9c606Sthorpej } else if (vt->vt_rev >= V96X_VREV_C0) {
18016b9c606Sthorpej *cfgoff = tag | offset;
18116b9c606Sthorpej *ad_low = V96X_LB_MAPx_AD_LOW_EN;
18216b9c606Sthorpej } else
18316b9c606Sthorpej return (1);
18416b9c606Sthorpej
18516b9c606Sthorpej return (0);
18616b9c606Sthorpej }
18716b9c606Sthorpej
18816b9c606Sthorpej pcireg_t
vtpbc_conf_read(void * v,pcitag_t tag,int offset)18916b9c606Sthorpej vtpbc_conf_read(void *v, pcitag_t tag, int offset)
19016b9c606Sthorpej {
19116b9c606Sthorpej struct vtpbc_config *vt = v;
19216b9c606Sthorpej pcireg_t data;
19316b9c606Sthorpej u_int32_t cfgoff, ad_low;
19416b9c606Sthorpej int s;
19516b9c606Sthorpej u_int16_t errbits;
19616b9c606Sthorpej
19716b9c606Sthorpej if (vtpbc_conf_addr(vt, tag, offset, &cfgoff, &ad_low))
19816b9c606Sthorpej return ((pcireg_t) -1);
19916b9c606Sthorpej
20016b9c606Sthorpej PCI_CONF_LOCK(s);
20116b9c606Sthorpej
20216b9c606Sthorpej /* high 12 bits of address go into map register */
20316b9c606Sthorpej V96X_LB_MAP0(vt) = ((cfgoff >> 16) & V96X_LB_MAPx_MAP_ADR) |
20416b9c606Sthorpej ad_low | V96X_LB_TYPE_CONF;
20516b9c606Sthorpej
20616b9c606Sthorpej /* clear aborts */
20716b9c606Sthorpej V96X_PCI_STAT(vt) |= V96X_PCI_STAT_M_ABORT | V96X_PCI_STAT_T_ABORT;
20816b9c606Sthorpej
20916b9c606Sthorpej wbflush();
21016b9c606Sthorpej
21116b9c606Sthorpej /* low 20 bits of address are offset into config space */
2125f1c88d7Sperry data = *(volatile u_int32_t *) (vt->vt_cfgbase + (cfgoff & 0xfffff));
21316b9c606Sthorpej
21416b9c606Sthorpej errbits = V96X_PCI_STAT(vt) &
21516b9c606Sthorpej (V96X_PCI_STAT_M_ABORT|V96X_PCI_STAT_T_ABORT);
21616b9c606Sthorpej if (errbits) {
21716b9c606Sthorpej V96X_PCI_STAT(vt) |= errbits;
21816b9c606Sthorpej data = (pcireg_t) -1;
21916b9c606Sthorpej }
22016b9c606Sthorpej
22116b9c606Sthorpej PCI_CONF_UNLOCK(s);
22216b9c606Sthorpej
22316b9c606Sthorpej return (data);
22416b9c606Sthorpej }
22516b9c606Sthorpej
22616b9c606Sthorpej void
vtpbc_conf_write(void * v,pcitag_t tag,int offset,pcireg_t data)22716b9c606Sthorpej vtpbc_conf_write(void *v, pcitag_t tag, int offset, pcireg_t data)
22816b9c606Sthorpej {
22916b9c606Sthorpej struct vtpbc_config *vt = v;
23016b9c606Sthorpej u_int32_t cfgoff, ad_low;
23116b9c606Sthorpej int s;
23216b9c606Sthorpej
23316b9c606Sthorpej if (vtpbc_conf_addr(vt, tag, offset, &cfgoff, &ad_low))
23416b9c606Sthorpej panic("vtpbc_conf_write");
23516b9c606Sthorpej
23616b9c606Sthorpej PCI_CONF_LOCK(s);
23716b9c606Sthorpej
23816b9c606Sthorpej /* high 12 bits of address go into map register */
23916b9c606Sthorpej V96X_LB_MAP0(vt) = ((cfgoff >> 16) & V96X_LB_MAPx_MAP_ADR) |
24016b9c606Sthorpej ad_low | V96X_LB_TYPE_CONF;
24116b9c606Sthorpej
24216b9c606Sthorpej /* clear aborts */
24316b9c606Sthorpej V96X_PCI_STAT(vt) |= V96X_PCI_STAT_M_ABORT | V96X_PCI_STAT_T_ABORT;
24416b9c606Sthorpej
24516b9c606Sthorpej wbflush();
24616b9c606Sthorpej
24716b9c606Sthorpej /* low 20 bits of address are offset into config space */
2485f1c88d7Sperry *(volatile u_int32_t *) (vt->vt_cfgbase + (cfgoff & 0xfffff)) = data;
24916b9c606Sthorpej
25016b9c606Sthorpej /* wait for FIFO to drain */
25116b9c606Sthorpej while (V96X_FIFO_STAT(vt) & V96X_FIFO_STAT_L2P_WR)
25216b9c606Sthorpej /* spin */ ;
25316b9c606Sthorpej
25416b9c606Sthorpej PCI_CONF_UNLOCK(s);
25516b9c606Sthorpej }
256