1 /* $NetBSD: algor_p4032_intr.c,v 1.20 2008/05/26 15:59:29 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Platform-specific interrupt support for the Algorithmics P-4032. 34 * 35 * The Algorithmics P-4032 has an interrupt controller that is pretty 36 * flexible -- it can take an interrupt source and route it to an 37 * arbitrary MIPS CPU hardware interrupt pin. 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: algor_p4032_intr.c,v 1.20 2008/05/26 15:59:29 tsutsui Exp $"); 42 43 #include "opt_ddb.h" 44 45 #include <sys/param.h> 46 #include <sys/queue.h> 47 #include <sys/malloc.h> 48 #include <sys/systm.h> 49 #include <sys/device.h> 50 #include <sys/kernel.h> 51 #include <sys/cpu.h> 52 53 #include <machine/bus.h> 54 #include <machine/autoconf.h> 55 #include <machine/intr.h> 56 57 #include <mips/locore.h> 58 59 #include <dev/ic/mc146818reg.h> 60 61 #include <algor/algor/algor_p4032reg.h> 62 #include <algor/algor/algor_p4032var.h> 63 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcivar.h> 66 67 #define REGVAL(x) *((volatile u_int32_t *)(MIPS_PHYS_TO_KSEG1((x)))) 68 69 struct p4032_irqreg { 70 bus_addr_t addr; 71 u_int32_t val; 72 }; 73 74 #define IRQREG_8BIT 0 75 #define IRQREG_ERROR 1 76 #define IRQREG_PCI 2 77 #define NIRQREG 3 78 79 struct p4032_irqreg p4032_irqregs[NIRQREG] = { 80 { P4032_IRR0, 0 }, 81 { P4032_IRR1, 0 }, 82 { P4032_IRR2, 0 }, 83 }; 84 85 #define NSTEERREG 3 86 87 struct p4032_irqreg p4032_irqsteer[NSTEERREG] = { 88 { P4032_XBAR0, 0 }, 89 { P4032_XBAR1, 0 }, 90 { P4032_XBAR2, 0 }, 91 }; 92 93 #define NPCIIRQS 4 94 95 /* See algor_p4032var.h */ 96 #define N8BITIRQS 8 97 98 #define IRQMAP_PCIBASE 0 99 #define IRQMAP_8BITBASE NPCIIRQS 100 #define NIRQMAPS (IRQMAP_8BITBASE + N8BITIRQS) 101 102 const char *p4032_intrnames[NIRQMAPS] = { 103 /* 104 * PCI INTERRUPTS 105 */ 106 "PCIIRQ 0", 107 "PCIIRQ 1", 108 "PCIIRQ 2", 109 "PCIIRQ 3", 110 111 /* 112 * 8-BIT DEVICE INTERRUPTS 113 */ 114 "PCI ctlr", 115 "floppy", 116 "pckbc", 117 "com 1", 118 "com 2", 119 "centronics", 120 "gpio", 121 "mcclock", 122 }; 123 124 struct p4032_irqmap { 125 int irqidx; 126 int cpuintr; 127 int irqreg; 128 int irqbit; 129 int xbarreg; 130 int xbarshift; 131 }; 132 133 const struct p4032_irqmap p4032_irqmap[NIRQMAPS] = { 134 /* 135 * PCI INTERRUPTS 136 */ 137 /* PCIIRQ 0 */ 138 { 0, 0, 139 IRQREG_PCI, IRR2_PCIIRQ0, 140 2, 0 }, 141 142 /* PCIIRQ 1 */ 143 { 1, 0, 144 IRQREG_PCI, IRR2_PCIIRQ1, 145 2, 2 }, 146 147 /* PCIIRQ 2 */ 148 { 2, 0, 149 IRQREG_PCI, IRR2_PCIIRQ2, 150 2, 4 }, 151 152 /* PCIIRQ 3 */ 153 { 3, 0, 154 IRQREG_PCI, IRR2_PCIIRQ3, 155 2, 6 }, 156 157 /* 158 * 8-BIT DEVICE INTERRUPTS 159 */ 160 { P4032_IRQ_PCICTLR, 1, 161 IRQREG_8BIT, IRR0_PCICTLR, 162 0, 0 }, 163 164 { P4032_IRQ_FLOPPY, 1, 165 IRQREG_8BIT, IRR0_FLOPPY, 166 0, 2 }, 167 168 { P4032_IRQ_PCKBC, 1, 169 IRQREG_8BIT, IRR0_PCKBC, 170 0, 4 }, 171 172 { P4032_IRQ_COM1, 1, 173 IRQREG_8BIT, IRR0_COM1, 174 0, 6 }, 175 176 { P4032_IRQ_COM2, 1, 177 IRQREG_8BIT, IRR0_COM2, 178 1, 0 }, 179 180 { P4032_IRQ_LPT, 1, 181 IRQREG_8BIT, IRR0_LPT, 182 1, 2 }, 183 184 { P4032_IRQ_GPIO, 1, 185 IRQREG_8BIT, IRR0_GPIO, 186 1, 4 }, 187 188 { P4032_IRQ_RTC, 1, 189 IRQREG_8BIT, IRR0_RTC, 190 1, 6 }, 191 }; 192 193 struct p4032_intrhead { 194 struct evcnt intr_count; 195 int intr_refcnt; 196 }; 197 struct p4032_intrhead p4032_intrtab[NIRQMAPS]; 198 199 #define NINTRS 2 /* MIPS INT0 - INT1 */ 200 201 202 struct p4032_cpuintr { 203 LIST_HEAD(, algor_intrhand) cintr_list; 204 struct evcnt cintr_count; 205 }; 206 207 struct p4032_cpuintr p4032_cpuintrs[NINTRS]; 208 const char *p4032_cpuintrnames[NINTRS] = { 209 "int 0 (pci)", 210 "int 1 (8-bit)", 211 }; 212 213 const char *p4032_intrgroups[NINTRS] = { 214 "pci", 215 "8-bit", 216 }; 217 218 void *algor_p4032_intr_establish(int, int (*)(void *), void *); 219 void algor_p4032_intr_disestablish(void *); 220 221 int algor_p4032_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 222 const char *algor_p4032_pci_intr_string(void *, pci_intr_handle_t); 223 const struct evcnt *algor_p4032_pci_intr_evcnt(void *, pci_intr_handle_t); 224 void *algor_p4032_pci_intr_establish(void *, pci_intr_handle_t, int, 225 int (*)(void *), void *); 226 void algor_p4032_pci_intr_disestablish(void *, void *); 227 void algor_p4032_pci_conf_interrupt(void *, int, int, int, int, int *); 228 229 void algor_p4032_iointr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 230 231 void 232 algor_p4032_intr_init(struct p4032_config *acp) 233 { 234 const struct p4032_irqmap *irqmap; 235 int i; 236 237 for (i = 0; i < NIRQREG; i++) 238 REGVAL(p4032_irqregs[i].addr) = p4032_irqregs[i].val; 239 240 for (i = 0; i < NINTRS; i++) { 241 LIST_INIT(&p4032_cpuintrs[i].cintr_list); 242 evcnt_attach_dynamic(&p4032_cpuintrs[i].cintr_count, 243 EVCNT_TYPE_INTR, NULL, "mips", p4032_cpuintrnames[i]); 244 } 245 evcnt_attach_static(&mips_int5_evcnt); 246 247 for (i = 0; i < NIRQMAPS; i++) { 248 irqmap = &p4032_irqmap[i]; 249 250 p4032_irqsteer[irqmap->xbarreg].val |= 251 irqmap->cpuintr << irqmap->xbarshift; 252 253 evcnt_attach_dynamic(&p4032_intrtab[i].intr_count, 254 EVCNT_TYPE_INTR, NULL, p4032_intrgroups[irqmap->cpuintr], 255 p4032_intrnames[i]); 256 } 257 258 for (i = 0; i < NSTEERREG; i++) 259 REGVAL(p4032_irqsteer[i].addr) = p4032_irqsteer[i].val; 260 261 acp->ac_pc.pc_intr_v = NULL; 262 acp->ac_pc.pc_intr_map = algor_p4032_pci_intr_map; 263 acp->ac_pc.pc_intr_string = algor_p4032_pci_intr_string; 264 acp->ac_pc.pc_intr_evcnt = algor_p4032_pci_intr_evcnt; 265 acp->ac_pc.pc_intr_establish = algor_p4032_pci_intr_establish; 266 acp->ac_pc.pc_intr_disestablish = algor_p4032_pci_intr_disestablish; 267 acp->ac_pc.pc_conf_interrupt = algor_p4032_pci_conf_interrupt; 268 acp->ac_pc.pc_pciide_compat_intr_establish = NULL; 269 270 algor_intr_establish = algor_p4032_intr_establish; 271 algor_intr_disestablish = algor_p4032_intr_disestablish; 272 algor_iointr = algor_p4032_iointr; 273 } 274 275 void 276 algor_p4032_cal_timer(bus_space_tag_t st, bus_space_handle_t sh) 277 { 278 u_long ctrdiff[4], startctr, endctr, cps; 279 u_int32_t irr; 280 int i; 281 282 /* Disable interrupts first. */ 283 bus_space_write_1(st, sh, 0, MC_REGB); 284 bus_space_write_1(st, sh, 1, MC_REGB_SQWE | MC_REGB_BINARY | 285 MC_REGB_24HR); 286 287 /* Initialize for 16Hz. */ 288 bus_space_write_1(st, sh, 0, MC_REGA); 289 bus_space_write_1(st, sh, 1, MC_BASE_32_KHz | MC_RATE_16_Hz); 290 291 REGVAL(P4032_IRR0) = IRR0_RTC; 292 293 /* Run the loop an extra time to prime the cache. */ 294 for (i = 0; i < 4; i++) { 295 led_display('h', 'z', '0' + i, ' '); 296 297 /* Enable the interrupt. */ 298 bus_space_write_1(st, sh, 0, MC_REGB); 299 bus_space_write_1(st, sh, 1, MC_REGB_PIE | MC_REGB_SQWE | 300 MC_REGB_BINARY | MC_REGB_24HR); 301 302 /* Wait for it to happen. */ 303 startctr = mips3_cp0_count_read(); 304 do { 305 irr = REGVAL(P4032_IRR0); 306 endctr = mips3_cp0_count_read(); 307 } while ((irr & IRR0_RTC) == 0); 308 309 /* ACK. */ 310 bus_space_write_1(st, sh, 0, MC_REGC); 311 (void) bus_space_read_1(st, sh, 1); 312 313 /* Disable. */ 314 bus_space_write_1(st, sh, 0, MC_REGB); 315 bus_space_write_1(st, sh, 1, MC_REGB_SQWE | MC_REGB_BINARY | 316 MC_REGB_24HR); 317 318 ctrdiff[i] = endctr - startctr; 319 } 320 321 REGVAL(P4032_IRR0) = 0; 322 323 /* Update CPU frequency values */ 324 cps = ((ctrdiff[2] + ctrdiff[3]) / 2) * 16; 325 /* XXX mips_cpu_flags isn't set here; assume CPU_MIPS_DOUBLE_COUNT */ 326 curcpu()->ci_cpu_freq = cps * 2; 327 curcpu()->ci_cycles_per_hz = (curcpu()->ci_cpu_freq + hz / 2) / hz; 328 curcpu()->ci_divisor_delay = 329 ((curcpu()->ci_cpu_freq + (1000000 / 2)) / 1000000); 330 /* XXX assume CPU_MIPS_DOUBLE_COUNT */ 331 curcpu()->ci_cycles_per_hz /= 2; 332 curcpu()->ci_divisor_delay /= 2; 333 334 printf("Timer calibration: %lu cycles/sec [(%lu, %lu) * 16]\n", 335 cps, ctrdiff[2], ctrdiff[3]); 336 printf("CPU clock speed = %lu.%02luMHz " 337 "(hz cycles = %lu, delay divisor = %lu)\n", 338 curcpu()->ci_cpu_freq / 1000000, 339 (curcpu()->ci_cpu_freq % 1000000) / 10000, 340 curcpu()->ci_cycles_per_hz, curcpu()->ci_divisor_delay); 341 } 342 343 void * 344 algor_p4032_intr_establish(int irq, int (*func)(void *), void *arg) 345 { 346 const struct p4032_irqmap *irqmap; 347 struct algor_intrhand *ih; 348 int s; 349 350 irqmap = &p4032_irqmap[irq]; 351 352 KASSERT(irq == irqmap->irqidx); 353 354 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 355 if (ih == NULL) 356 return (NULL); 357 358 ih->ih_func = func; 359 ih->ih_arg = arg; 360 ih->ih_irq = 0; 361 ih->ih_irqmap = irqmap; 362 363 s = splhigh(); 364 365 /* 366 * First, link it into the tables. 367 */ 368 LIST_INSERT_HEAD(&p4032_cpuintrs[irqmap->cpuintr].cintr_list, 369 ih, ih_q); 370 371 /* 372 * Now enable it. 373 */ 374 if (p4032_intrtab[irqmap->irqidx].intr_refcnt++ == 0) { 375 p4032_irqregs[irqmap->irqreg].val |= irqmap->irqbit; 376 REGVAL(p4032_irqregs[irqmap->irqreg].addr) = 377 p4032_irqregs[irqmap->irqreg].val; 378 } 379 380 splx(s); 381 382 return (ih); 383 } 384 385 void 386 algor_p4032_intr_disestablish(void *cookie) 387 { 388 const struct p4032_irqmap *irqmap; 389 struct algor_intrhand *ih = cookie; 390 int s; 391 392 irqmap = ih->ih_irqmap; 393 394 s = splhigh(); 395 396 /* 397 * First, remove it from the table. 398 */ 399 LIST_REMOVE(ih, ih_q); 400 401 /* 402 * Now, disable it, if there is nothing remaining on the 403 * list. 404 */ 405 if (p4032_intrtab[irqmap->irqidx].intr_refcnt-- == 1) { 406 p4032_irqregs[irqmap->irqreg].val &= ~irqmap->irqbit; 407 REGVAL(p4032_irqregs[irqmap->irqreg].addr) = 408 p4032_irqregs[irqmap->irqreg].val; 409 } 410 411 splx(s); 412 413 free(ih, M_DEVBUF); 414 } 415 416 void 417 algor_p4032_iointr(u_int32_t status, u_int32_t cause, u_int32_t pc, 418 u_int32_t ipending) 419 { 420 const struct p4032_irqmap *irqmap; 421 struct algor_intrhand *ih; 422 int level, i; 423 u_int32_t irr[NIRQREG]; 424 425 /* Check for ERROR interrupts. */ 426 if (ipending & MIPS_INT_MASK_4) { 427 irr[IRQREG_ERROR] = REGVAL(p4032_irqregs[IRQREG_ERROR].addr); 428 if (irr[IRQREG_ERROR] & IRR1_BUSERR) 429 printf("WARNING: Bus error\n"); 430 if (irr[IRQREG_ERROR] & IRR1_POWERFAIL) 431 printf("WARNING: Power failure\n"); 432 if (irr[IRQREG_ERROR] & IRR1_DEBUG) { 433 #ifdef DDB 434 printf("Debug switch -- entering debugger\n"); 435 led_display('D','D','B',' '); 436 Debugger(); 437 led_display('N','B','S','D'); 438 #else 439 printf("Debug switch ignored -- " 440 "no debugger configured\n"); 441 #endif 442 } 443 444 /* Clear them. */ 445 REGVAL(p4032_irqregs[IRQREG_ERROR].addr) = irr[IRQREG_ERROR]; 446 } 447 448 /* Do floppy DMA request interrupts. */ 449 if (ipending & MIPS_INT_MASK_3) { 450 /* 451 * XXX Hi, um, yah, we need to deal with 452 * XXX the floppy interrupt here. 453 */ 454 455 cause &= ~MIPS_INT_MASK_3; 456 _splset(MIPS_SR_INT_IE | 457 ((status & ~cause) & MIPS_HARD_INT_MASK)); 458 } 459 460 /* 461 * Read the interrupt pending registers, mask them with the 462 * ones we have enabled, and service them in order of decreasing 463 * priority. 464 */ 465 for (i = 0; i < NIRQREG; i++) { 466 if (i == IRQREG_ERROR) 467 continue; 468 irr[i] = REGVAL(p4032_irqregs[i].addr) & p4032_irqregs[i].val; 469 } 470 471 for (level = (NINTRS - 1); level >= 0; level--) { 472 if ((ipending & (MIPS_INT_MASK_0 << level)) == 0) 473 continue; 474 p4032_cpuintrs[level].cintr_count.ev_count++; 475 for (ih = LIST_FIRST(&p4032_cpuintrs[level].cintr_list); 476 ih != NULL; ih = LIST_NEXT(ih, ih_q)) { 477 irqmap = ih->ih_irqmap; 478 if (irr[irqmap->irqreg] & irqmap->irqbit) { 479 p4032_intrtab[ 480 irqmap->irqidx].intr_count.ev_count++; 481 (*ih->ih_func)(ih->ih_arg); 482 } 483 } 484 cause &= ~(MIPS_INT_MASK_0 << level); 485 } 486 487 /* Re-enable anything that we have processed. */ 488 _splset(MIPS_SR_INT_IE | ((status & ~cause) & MIPS_HARD_INT_MASK)); 489 } 490 491 /***************************************************************************** 492 * PCI interrupt support 493 *****************************************************************************/ 494 495 int 496 algor_p4032_pci_intr_map(struct pci_attach_args *pa, 497 pci_intr_handle_t *ihp) 498 { 499 static const int pciirqmap[6/*device*/][4/*pin*/] = { 500 { 1, -1, -1, -1 }, /* 5: Ethernet */ 501 { 2, 3, 0, 1 }, /* 6: PCI slot 1 */ 502 { 3, 0, 1, 2 }, /* 7: PCI slot 2 */ 503 { 0, -1, -1, -1 }, /* 8: SCSI */ 504 { -1, -1, -1, -1 }, /* 9: not used */ 505 { 0, 1, 2, 3 }, /* 10: custom connector */ 506 }; 507 pcitag_t bustag = pa->pa_intrtag; 508 int buspin = pa->pa_intrpin; 509 pci_chipset_tag_t pc = pa->pa_pc; 510 int device, irq; 511 512 if (buspin == 0) { 513 /* No IRQ used. */ 514 return (1); 515 } 516 517 if (buspin > 4) { 518 printf("algor_p4032_pci_intr_map: bad interrupt pin %d\n", 519 buspin); 520 return (1); 521 } 522 523 pci_decompose_tag(pc, bustag, NULL, &device, NULL); 524 if (device < 5 || device > 10) { 525 printf("algor_p4032_pci_intr_map: bad device %d\n", 526 device); 527 return (1); 528 } 529 530 irq = pciirqmap[device - 5][buspin - 1]; 531 if (irq == -1) { 532 printf("algor_p4032_pci_intr_map: no mapping for " 533 "device %d pin %d\n", device, buspin); 534 return (1); 535 } 536 537 *ihp = irq; 538 return (0); 539 } 540 541 const char * 542 algor_p4032_pci_intr_string(void *v, pci_intr_handle_t ih) 543 { 544 545 if (ih >= NPCIIRQS) 546 panic("algor_p4032_intr_string: bogus IRQ %ld", ih); 547 548 return (p4032_intrnames[ih]); 549 } 550 551 const struct evcnt * 552 algor_p4032_pci_intr_evcnt(void *v, pci_intr_handle_t ih) 553 { 554 555 return (&p4032_intrtab[ih].intr_count); 556 } 557 558 void * 559 algor_p4032_pci_intr_establish(void *v, pci_intr_handle_t ih, int level, 560 int (*func)(void *), void *arg) 561 { 562 563 if (ih >= NPCIIRQS) 564 panic("algor_p4032_intr_establish: bogus IRQ %ld", ih); 565 566 return (algor_p4032_intr_establish(ih, func, arg)); 567 } 568 569 void 570 algor_p4032_pci_intr_disestablish(void *v, void *cookie) 571 { 572 573 return (algor_p4032_intr_disestablish(cookie)); 574 } 575 576 void 577 algor_p4032_pci_conf_interrupt(void *v, int bus, int dev, int pin, int swiz, 578 int *iline) 579 { 580 581 /* 582 * We actually don't need to do anything; everything is handled 583 * in pci_intr_map(). 584 */ 585 *iline = 0; 586 } 587