1 /* $NetBSD: algor_p4032_intr.c,v 1.14 2007/12/03 15:33:03 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Platform-specific interrupt support for the Algorithmics P-4032. 41 * 42 * The Algorithmics P-4032 has an interrupt controller that is pretty 43 * flexible -- it can take an interrupt source and route it to an 44 * arbitrary MIPS CPU hardware interrupt pin. 45 */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: algor_p4032_intr.c,v 1.14 2007/12/03 15:33:03 ad Exp $"); 49 50 #include "opt_ddb.h" 51 52 #include <sys/param.h> 53 #include <sys/queue.h> 54 #include <sys/malloc.h> 55 #include <sys/systm.h> 56 #include <sys/device.h> 57 #include <sys/kernel.h> 58 59 #include <machine/bus.h> 60 #include <machine/autoconf.h> 61 #include <machine/intr.h> 62 63 #include <mips/locore.h> 64 65 #include <dev/ic/mc146818reg.h> 66 67 #include <algor/algor/algor_p4032reg.h> 68 #include <algor/algor/algor_p4032var.h> 69 70 #include <dev/pci/pcireg.h> 71 #include <dev/pci/pcivar.h> 72 73 #define REGVAL(x) *((volatile u_int32_t *)(MIPS_PHYS_TO_KSEG1((x)))) 74 75 struct p4032_irqreg { 76 bus_addr_t addr; 77 u_int32_t val; 78 }; 79 80 #define IRQREG_8BIT 0 81 #define IRQREG_ERROR 1 82 #define IRQREG_PCI 2 83 #define NIRQREG 3 84 85 struct p4032_irqreg p4032_irqregs[NIRQREG] = { 86 { P4032_IRR0, 0 }, 87 { P4032_IRR1, 0 }, 88 { P4032_IRR2, 0 }, 89 }; 90 91 #define NSTEERREG 3 92 93 struct p4032_irqreg p4032_irqsteer[NSTEERREG] = { 94 { P4032_XBAR0, 0 }, 95 { P4032_XBAR1, 0 }, 96 { P4032_XBAR2, 0 }, 97 }; 98 99 #define NPCIIRQS 4 100 101 /* See algor_p4032var.h */ 102 #define N8BITIRQS 8 103 104 #define IRQMAP_PCIBASE 0 105 #define IRQMAP_8BITBASE NPCIIRQS 106 #define NIRQMAPS (IRQMAP_8BITBASE + N8BITIRQS) 107 108 const char *p4032_intrnames[NIRQMAPS] = { 109 /* 110 * PCI INTERRUPTS 111 */ 112 "PCIIRQ 0", 113 "PCIIRQ 1", 114 "PCIIRQ 2", 115 "PCIIRQ 3", 116 117 /* 118 * 8-BIT DEVICE INTERRUPTS 119 */ 120 "PCI ctlr", 121 "floppy", 122 "pckbc", 123 "com 1", 124 "com 2", 125 "centronics", 126 "gpio", 127 "mcclock", 128 }; 129 130 struct p4032_irqmap { 131 int irqidx; 132 int cpuintr; 133 int irqreg; 134 int irqbit; 135 int xbarreg; 136 int xbarshift; 137 }; 138 139 const struct p4032_irqmap p4032_irqmap[NIRQMAPS] = { 140 /* 141 * PCI INTERRUPTS 142 */ 143 /* PCIIRQ 0 */ 144 { 0, 0, 145 IRQREG_PCI, IRR2_PCIIRQ0, 146 2, 0 }, 147 148 /* PCIIRQ 1 */ 149 { 1, 0, 150 IRQREG_PCI, IRR2_PCIIRQ1, 151 2, 2 }, 152 153 /* PCIIRQ 2 */ 154 { 2, 0, 155 IRQREG_PCI, IRR2_PCIIRQ2, 156 2, 4 }, 157 158 /* PCIIRQ 3 */ 159 { 3, 0, 160 IRQREG_PCI, IRR2_PCIIRQ3, 161 2, 6 }, 162 163 /* 164 * 8-BIT DEVICE INTERRUPTS 165 */ 166 { P4032_IRQ_PCICTLR, 1, 167 IRQREG_8BIT, IRR0_PCICTLR, 168 0, 0 }, 169 170 { P4032_IRQ_FLOPPY, 1, 171 IRQREG_8BIT, IRR0_FLOPPY, 172 0, 2 }, 173 174 { P4032_IRQ_PCKBC, 1, 175 IRQREG_8BIT, IRR0_PCKBC, 176 0, 4 }, 177 178 { P4032_IRQ_COM1, 1, 179 IRQREG_8BIT, IRR0_COM1, 180 0, 6 }, 181 182 { P4032_IRQ_COM2, 1, 183 IRQREG_8BIT, IRR0_COM2, 184 1, 0 }, 185 186 { P4032_IRQ_LPT, 1, 187 IRQREG_8BIT, IRR0_LPT, 188 1, 2 }, 189 190 { P4032_IRQ_GPIO, 1, 191 IRQREG_8BIT, IRR0_GPIO, 192 1, 4 }, 193 194 { P4032_IRQ_RTC, 1, 195 IRQREG_8BIT, IRR0_RTC, 196 1, 6 }, 197 }; 198 199 struct p4032_intrhead { 200 struct evcnt intr_count; 201 int intr_refcnt; 202 }; 203 struct p4032_intrhead p4032_intrtab[NIRQMAPS]; 204 205 #define NINTRS 2 /* MIPS INT0 - INT1 */ 206 207 208 struct p4032_cpuintr { 209 LIST_HEAD(, algor_intrhand) cintr_list; 210 struct evcnt cintr_count; 211 }; 212 213 struct p4032_cpuintr p4032_cpuintrs[NINTRS]; 214 const char *p4032_cpuintrnames[NINTRS] = { 215 "int 0 (pci)", 216 "int 1 (8-bit)", 217 }; 218 219 const char *p4032_intrgroups[NINTRS] = { 220 "pci", 221 "8-bit", 222 }; 223 224 void *algor_p4032_intr_establish(int, int (*)(void *), void *); 225 void algor_p4032_intr_disestablish(void *); 226 227 int algor_p4032_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 228 const char *algor_p4032_pci_intr_string(void *, pci_intr_handle_t); 229 const struct evcnt *algor_p4032_pci_intr_evcnt(void *, pci_intr_handle_t); 230 void *algor_p4032_pci_intr_establish(void *, pci_intr_handle_t, int, 231 int (*)(void *), void *); 232 void algor_p4032_pci_intr_disestablish(void *, void *); 233 void algor_p4032_pci_conf_interrupt(void *, int, int, int, int, int *); 234 235 void algor_p4032_iointr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 236 237 void 238 algor_p4032_intr_init(struct p4032_config *acp) 239 { 240 const struct p4032_irqmap *irqmap; 241 int i; 242 243 for (i = 0; i < NIRQREG; i++) 244 REGVAL(p4032_irqregs[i].addr) = p4032_irqregs[i].val; 245 246 for (i = 0; i < NINTRS; i++) { 247 LIST_INIT(&p4032_cpuintrs[i].cintr_list); 248 evcnt_attach_dynamic(&p4032_cpuintrs[i].cintr_count, 249 EVCNT_TYPE_INTR, NULL, "mips", p4032_cpuintrnames[i]); 250 } 251 evcnt_attach_static(&mips_int5_evcnt); 252 253 for (i = 0; i < NIRQMAPS; i++) { 254 irqmap = &p4032_irqmap[i]; 255 256 p4032_irqsteer[irqmap->xbarreg].val |= 257 irqmap->cpuintr << irqmap->xbarshift; 258 259 evcnt_attach_dynamic(&p4032_intrtab[i].intr_count, 260 EVCNT_TYPE_INTR, NULL, p4032_intrgroups[irqmap->cpuintr], 261 p4032_intrnames[i]); 262 } 263 264 for (i = 0; i < NSTEERREG; i++) 265 REGVAL(p4032_irqsteer[i].addr) = p4032_irqsteer[i].val; 266 267 acp->ac_pc.pc_intr_v = NULL; 268 acp->ac_pc.pc_intr_map = algor_p4032_pci_intr_map; 269 acp->ac_pc.pc_intr_string = algor_p4032_pci_intr_string; 270 acp->ac_pc.pc_intr_evcnt = algor_p4032_pci_intr_evcnt; 271 acp->ac_pc.pc_intr_establish = algor_p4032_pci_intr_establish; 272 acp->ac_pc.pc_intr_disestablish = algor_p4032_pci_intr_disestablish; 273 acp->ac_pc.pc_conf_interrupt = algor_p4032_pci_conf_interrupt; 274 acp->ac_pc.pc_pciide_compat_intr_establish = NULL; 275 276 algor_intr_establish = algor_p4032_intr_establish; 277 algor_intr_disestablish = algor_p4032_intr_disestablish; 278 algor_iointr = algor_p4032_iointr; 279 } 280 281 void 282 algor_p4032_cal_timer(bus_space_tag_t st, bus_space_handle_t sh) 283 { 284 u_long ctrdiff[4], startctr, endctr, cps; 285 u_int32_t irr; 286 int i; 287 288 /* Disable interrupts first. */ 289 bus_space_write_1(st, sh, 0, MC_REGB); 290 bus_space_write_1(st, sh, 1, MC_REGB_SQWE | MC_REGB_BINARY | 291 MC_REGB_24HR); 292 293 /* Initialize for 16Hz. */ 294 bus_space_write_1(st, sh, 0, MC_REGA); 295 bus_space_write_1(st, sh, 1, MC_BASE_32_KHz | MC_RATE_16_Hz); 296 297 REGVAL(P4032_IRR0) = IRR0_RTC; 298 299 /* Run the loop an extra time to prime the cache. */ 300 for (cps = 0, i = 0; i < 4; i++) { 301 led_display('h', 'z', '0' + i, ' '); 302 303 /* Enable the interrupt. */ 304 bus_space_write_1(st, sh, 0, MC_REGB); 305 bus_space_write_1(st, sh, 1, MC_REGB_PIE | MC_REGB_SQWE | 306 MC_REGB_BINARY | MC_REGB_24HR); 307 308 /* Wait for it to happen. */ 309 startctr = mips3_cp0_count_read(); 310 do { 311 irr = REGVAL(P4032_IRR0); 312 endctr = mips3_cp0_count_read(); 313 } while ((irr & IRR0_RTC) == 0); 314 315 /* ACK. */ 316 bus_space_write_1(st, sh, 0, MC_REGC); 317 (void) bus_space_read_1(st, sh, 1); 318 319 /* Disable. */ 320 bus_space_write_1(st, sh, 0, MC_REGB); 321 bus_space_write_1(st, sh, 1, MC_REGB_SQWE | MC_REGB_BINARY | 322 MC_REGB_24HR); 323 324 ctrdiff[i] = endctr - startctr; 325 } 326 327 REGVAL(P4032_IRR0) = 0; 328 329 /* Compute the number of cycles per second. */ 330 cps = ((ctrdiff[2] + ctrdiff[3]) / 2) * 16; 331 332 /* Compute the number of ticks for hz. */ 333 cycles_per_hz = cps / hz; 334 335 /* Compute the delay divisor. */ 336 delay_divisor = (cps / 1000000) / 2; 337 338 printf("Timer calibration: %lu cycles/sec [(%lu, %lu) * 16]\n", 339 cps, ctrdiff[2], ctrdiff[3]); 340 printf("CPU clock speed = %lu.%02luMHz " 341 "(hz cycles = %lu, delay divisor = %u)\n", 342 cps / 1000000, (cps % 1000000) / 10000, 343 cycles_per_hz, delay_divisor); 344 } 345 346 void * 347 algor_p4032_intr_establish(int irq, int (*func)(void *), void *arg) 348 { 349 const struct p4032_irqmap *irqmap; 350 struct algor_intrhand *ih; 351 int s; 352 353 irqmap = &p4032_irqmap[irq]; 354 355 KASSERT(irq == irqmap->irqidx); 356 357 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 358 if (ih == NULL) 359 return (NULL); 360 361 ih->ih_func = func; 362 ih->ih_arg = arg; 363 ih->ih_irq = 0; 364 ih->ih_irqmap = irqmap; 365 366 s = splhigh(); 367 368 /* 369 * First, link it into the tables. 370 */ 371 LIST_INSERT_HEAD(&p4032_cpuintrs[irqmap->cpuintr].cintr_list, 372 ih, ih_q); 373 374 /* 375 * Now enable it. 376 */ 377 if (p4032_intrtab[irqmap->irqidx].intr_refcnt++ == 0) { 378 p4032_irqregs[irqmap->irqreg].val |= irqmap->irqbit; 379 REGVAL(p4032_irqregs[irqmap->irqreg].addr) = 380 p4032_irqregs[irqmap->irqreg].val; 381 } 382 383 splx(s); 384 385 return (ih); 386 } 387 388 void 389 algor_p4032_intr_disestablish(void *cookie) 390 { 391 const struct p4032_irqmap *irqmap; 392 struct algor_intrhand *ih = cookie; 393 int s; 394 395 irqmap = ih->ih_irqmap; 396 397 s = splhigh(); 398 399 /* 400 * First, remove it from the table. 401 */ 402 LIST_REMOVE(ih, ih_q); 403 404 /* 405 * Now, disable it, if there is nothing remaining on the 406 * list. 407 */ 408 if (p4032_intrtab[irqmap->irqidx].intr_refcnt-- == 1) { 409 p4032_irqregs[irqmap->irqreg].val &= ~irqmap->irqbit; 410 REGVAL(p4032_irqregs[irqmap->irqreg].addr) = 411 p4032_irqregs[irqmap->irqreg].val; 412 } 413 414 splx(s); 415 416 free(ih, M_DEVBUF); 417 } 418 419 void 420 algor_p4032_iointr(u_int32_t status, u_int32_t cause, u_int32_t pc, 421 u_int32_t ipending) 422 { 423 const struct p4032_irqmap *irqmap; 424 struct algor_intrhand *ih; 425 int level, i; 426 u_int32_t irr[NIRQREG]; 427 428 /* Check for ERROR interrupts. */ 429 if (ipending & MIPS_INT_MASK_4) { 430 irr[IRQREG_ERROR] = REGVAL(p4032_irqregs[IRQREG_ERROR].addr); 431 if (irr[IRQREG_ERROR] & IRR1_BUSERR) 432 printf("WARNING: Bus error\n"); 433 if (irr[IRQREG_ERROR] & IRR1_POWERFAIL) 434 printf("WARNING: Power failure\n"); 435 if (irr[IRQREG_ERROR] & IRR1_DEBUG) { 436 #ifdef DDB 437 printf("Debug switch -- entering debugger\n"); 438 led_display('D','D','B',' '); 439 Debugger(); 440 led_display('N','B','S','D'); 441 #else 442 printf("Debug switch ignored -- " 443 "no debugger configured\n"); 444 #endif 445 } 446 447 /* Clear them. */ 448 REGVAL(p4032_irqregs[IRQREG_ERROR].addr) = irr[IRQREG_ERROR]; 449 } 450 451 /* Do floppy DMA request interrupts. */ 452 if (ipending & MIPS_INT_MASK_3) { 453 /* 454 * XXX Hi, um, yah, we need to deal with 455 * XXX the floppy interrupt here. 456 */ 457 458 cause &= ~MIPS_INT_MASK_3; 459 _splset(MIPS_SR_INT_IE | 460 ((status & ~cause) & MIPS_HARD_INT_MASK)); 461 } 462 463 /* 464 * Read the interrupt pending registers, mask them with the 465 * ones we have enabled, and service them in order of decreasing 466 * priority. 467 */ 468 for (i = 0; i < NIRQREG; i++) { 469 if (i == IRQREG_ERROR) 470 continue; 471 irr[i] = REGVAL(p4032_irqregs[i].addr) & p4032_irqregs[i].val; 472 } 473 474 for (level = (NINTRS - 1); level >= 0; level--) { 475 if ((ipending & (MIPS_INT_MASK_0 << level)) == 0) 476 continue; 477 p4032_cpuintrs[level].cintr_count.ev_count++; 478 for (ih = LIST_FIRST(&p4032_cpuintrs[level].cintr_list); 479 ih != NULL; ih = LIST_NEXT(ih, ih_q)) { 480 irqmap = ih->ih_irqmap; 481 if (irr[irqmap->irqreg] & irqmap->irqbit) { 482 p4032_intrtab[ 483 irqmap->irqidx].intr_count.ev_count++; 484 (*ih->ih_func)(ih->ih_arg); 485 } 486 } 487 cause &= ~(MIPS_INT_MASK_0 << level); 488 } 489 490 /* Re-enable anything that we have processed. */ 491 _splset(MIPS_SR_INT_IE | ((status & ~cause) & MIPS_HARD_INT_MASK)); 492 } 493 494 /***************************************************************************** 495 * PCI interrupt support 496 *****************************************************************************/ 497 498 int 499 algor_p4032_pci_intr_map(struct pci_attach_args *pa, 500 pci_intr_handle_t *ihp) 501 { 502 static const int pciirqmap[6/*device*/][4/*pin*/] = { 503 { 1, -1, -1, -1 }, /* 5: Ethernet */ 504 { 2, 3, 0, 1 }, /* 6: PCI slot 1 */ 505 { 3, 0, 1, 2 }, /* 7: PCI slot 2 */ 506 { 0, -1, -1, -1 }, /* 8: SCSI */ 507 { -1, -1, -1, -1 }, /* 9: not used */ 508 { 0, 1, 2, 3 }, /* 10: custom connector */ 509 }; 510 pcitag_t bustag = pa->pa_intrtag; 511 int buspin = pa->pa_intrpin; 512 pci_chipset_tag_t pc = pa->pa_pc; 513 int device, irq; 514 515 if (buspin == 0) { 516 /* No IRQ used. */ 517 return (1); 518 } 519 520 if (buspin > 4) { 521 printf("algor_p4032_pci_intr_map: bad interrupt pin %d\n", 522 buspin); 523 return (1); 524 } 525 526 pci_decompose_tag(pc, bustag, NULL, &device, NULL); 527 if (device < 5 || device > 10) { 528 printf("algor_p4032_pci_intr_map: bad device %d\n", 529 device); 530 return (1); 531 } 532 533 irq = pciirqmap[device - 5][buspin - 1]; 534 if (irq == -1) { 535 printf("algor_p4032_pci_intr_map: no mapping for " 536 "device %d pin %d\n", device, buspin); 537 return (1); 538 } 539 540 *ihp = irq; 541 return (0); 542 } 543 544 const char * 545 algor_p4032_pci_intr_string(void *v, pci_intr_handle_t ih) 546 { 547 548 if (ih >= NPCIIRQS) 549 panic("algor_p4032_intr_string: bogus IRQ %ld", ih); 550 551 return (p4032_intrnames[ih]); 552 } 553 554 const struct evcnt * 555 algor_p4032_pci_intr_evcnt(void *v, pci_intr_handle_t ih) 556 { 557 558 return (&p4032_intrtab[ih].intr_count); 559 } 560 561 void * 562 algor_p4032_pci_intr_establish(void *v, pci_intr_handle_t ih, int level, 563 int (*func)(void *), void *arg) 564 { 565 566 if (ih >= NPCIIRQS) 567 panic("algor_p4032_intr_establish: bogus IRQ %ld", ih); 568 569 return (algor_p4032_intr_establish(ih, func, arg)); 570 } 571 572 void 573 algor_p4032_pci_intr_disestablish(void *v, void *cookie) 574 { 575 576 return (algor_p4032_intr_disestablish(cookie)); 577 } 578 579 void 580 algor_p4032_pci_conf_interrupt(void *v, int bus, int dev, int pin, int swiz, 581 int *iline) 582 { 583 584 /* 585 * We actually don't need to do anything; everything is handled 586 * in pci_intr_map(). 587 */ 588 *iline = 0; 589 } 590