1 /* $NetBSD: cpufunc.h,v 1.23 2022/01/31 09:16:09 ryo Exp $ */ 2 3 /* 4 * Copyright (c) 2017 Ryo Shimizu <ryo@nerv.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _AARCH64_CPUFUNC_H_ 30 #define _AARCH64_CPUFUNC_H_ 31 32 #ifdef _KERNEL 33 34 #include <arm/armreg.h> 35 #include <sys/device_if.h> 36 37 38 extern u_int aarch64_cache_vindexsize; /* cachesize/way (VIVT/VIPT) */ 39 extern u_int aarch64_cache_prefer_mask; 40 extern u_int cputype; /* compat arm */ 41 42 extern int aarch64_bti_enabled; 43 extern int aarch64_hafdbs_enabled; 44 extern int aarch64_pan_enabled; 45 extern int aarch64_pac_enabled; 46 47 void aarch64_hafdbs_init(int); 48 void aarch64_pan_init(int); 49 int aarch64_pac_init(int); 50 51 int set_cpufuncs(void); 52 int aarch64_setcpufuncs(struct cpu_info *); 53 void aarch64_getcacheinfo(struct cpu_info *); 54 void aarch64_parsecacheinfo(struct cpu_info *); 55 void aarch64_printcacheinfo(device_t, struct cpu_info *); 56 57 void aarch64_dcache_wbinv_all(void); 58 void aarch64_dcache_inv_all(void); 59 void aarch64_dcache_wb_all(void); 60 void aarch64_icache_inv_all(void); 61 62 /* cache op in cpufunc_asm_armv8.S */ 63 void aarch64_nullop(void); 64 uint32_t aarch64_cpuid(void); 65 void aarch64_icache_sync_range(vaddr_t, vsize_t); 66 void aarch64_icache_inv_range(vaddr_t, vsize_t); 67 void aarch64_icache_barrier_range(vaddr_t, vsize_t); 68 void aarch64_idcache_wbinv_range(vaddr_t, vsize_t); 69 void aarch64_dcache_wbinv_range(vaddr_t, vsize_t); 70 void aarch64_dcache_inv_range(vaddr_t, vsize_t); 71 void aarch64_dcache_wb_range(vaddr_t, vsize_t); 72 void aarch64_icache_inv_all(void); 73 void aarch64_drain_writebuf(void); 74 75 /* tlb op in cpufunc_asm_armv8.S */ 76 #define cpu_set_ttbr0(t) curcpu()->ci_cpufuncs.cf_set_ttbr0((t)) 77 void aarch64_set_ttbr0(uint64_t); 78 void aarch64_set_ttbr0_thunderx(uint64_t); 79 void aarch64_tlbi_all(void); /* all ASID, all VA */ 80 void aarch64_tlbi_by_asid(int); /* an ASID, all VA */ 81 void aarch64_tlbi_by_va(vaddr_t); /* all ASID, a VA */ 82 void aarch64_tlbi_by_va_ll(vaddr_t); /* all ASID, a VA, lastlevel */ 83 void aarch64_tlbi_by_asid_va(int, vaddr_t); /* an ASID, a VA */ 84 void aarch64_tlbi_by_asid_va_ll(int, vaddr_t); /* an ASID, a VA, lastlevel */ 85 86 /* misc */ 87 #define cpu_idnum() aarch64_cpuid() 88 89 /* cache op */ 90 #define cpu_dcache_wbinv_all() aarch64_dcache_wbinv_all() 91 #define cpu_dcache_inv_all() aarch64_dcache_inv_all() 92 #define cpu_dcache_wb_all() aarch64_dcache_wb_all() 93 #define cpu_idcache_wbinv_all() \ 94 (aarch64_dcache_wbinv_all(), aarch64_icache_inv_all()) 95 #define cpu_icache_sync_all() \ 96 (aarch64_dcache_wb_all(), aarch64_icache_inv_all()) 97 #define cpu_icache_inv_all() aarch64_icache_inv_all() 98 99 #define cpu_dcache_wbinv_range(v,s) aarch64_dcache_wbinv_range((v),(s)) 100 #define cpu_dcache_inv_range(v,s) aarch64_dcache_inv_range((v),(s)) 101 #define cpu_dcache_wb_range(v,s) aarch64_dcache_wb_range((v),(s)) 102 #define cpu_idcache_wbinv_range(v,s) aarch64_idcache_wbinv_range((v),(s)) 103 #define cpu_icache_sync_range(v,s) \ 104 curcpu()->ci_cpufuncs.cf_icache_sync_range((v),(s)) 105 106 #define cpu_sdcache_wbinv_range(v,p,s) ((void)0) 107 #define cpu_sdcache_inv_range(v,p,s) ((void)0) 108 #define cpu_sdcache_wb_range(v,p,s) ((void)0) 109 110 /* others */ 111 #define cpu_drain_writebuf() aarch64_drain_writebuf() 112 113 extern u_int arm_dcache_align; 114 extern u_int arm_dcache_align_mask; 115 116 static inline bool 117 cpu_gtmr_exists_p(void) 118 { 119 120 return true; 121 } 122 123 static inline u_int 124 cpu_clusterid(void) 125 { 126 127 return __SHIFTOUT(reg_mpidr_el1_read(), MPIDR_AFF1); 128 } 129 130 static inline bool 131 cpu_earlydevice_va_p(void) 132 { 133 extern bool pmap_devmap_bootstrap_done; /* in pmap.c */ 134 135 /* This function may be called before enabling MMU, or mapping KVA */ 136 if ((reg_sctlr_el1_read() & SCTLR_M) == 0) 137 return false; 138 139 /* device mapping will be availabled after pmap_devmap_bootstrap() */ 140 if (!pmap_devmap_bootstrap_done) 141 return false; 142 143 return true; 144 } 145 146 #endif /* _KERNEL */ 147 148 /* definitions of TAG and PAC in pointers */ 149 #define AARCH64_ADDRTOP_TAG_BIT 55 150 #define AARCH64_ADDRTOP_TAG __BIT(55) /* ECR_EL1.TBI[01]=1 */ 151 #define AARCH64_ADDRTOP_MSB __BIT(63) /* ECR_EL1.TBI[01]=0 */ 152 #define AARCH64_ADDRESS_TAG_MASK __BITS(63,56) /* if TCR.TBI[01]=1 */ 153 #define AARCH64_ADDRESS_PAC_MASK __BITS(54,48) /* depend on VIRT_BIT */ 154 #define AARCH64_ADDRESS_TAGPAC_MASK \ 155 (AARCH64_ADDRESS_TAG_MASK|AARCH64_ADDRESS_PAC_MASK) 156 157 #ifdef _KERNEL 158 /* 159 * Which is the address space of this VA? 160 * return the space considering TBI. (PAC is not yet) 161 * 162 * return value: AARCH64_ADDRSPACE_{LOWER,UPPER}{_OUTOFRANGE}? 163 */ 164 #define AARCH64_ADDRSPACE_LOWER 0 /* -> TTBR0 */ 165 #define AARCH64_ADDRSPACE_UPPER 1 /* -> TTBR1 */ 166 #define AARCH64_ADDRSPACE_LOWER_OUTOFRANGE -1 /* certainly fault */ 167 #define AARCH64_ADDRSPACE_UPPER_OUTOFRANGE -2 /* certainly fault */ 168 static inline int 169 aarch64_addressspace(vaddr_t va) 170 { 171 uint64_t addrtop, tbi; 172 173 addrtop = va & AARCH64_ADDRTOP_TAG; 174 tbi = addrtop ? TCR_TBI1 : TCR_TBI0; 175 if (reg_tcr_el1_read() & tbi) { 176 if (addrtop == 0) { 177 /* lower address, and TBI0 enabled */ 178 if ((va & AARCH64_ADDRESS_PAC_MASK) != 0) 179 return AARCH64_ADDRSPACE_LOWER_OUTOFRANGE; 180 return AARCH64_ADDRSPACE_LOWER; 181 } 182 /* upper address, and TBI1 enabled */ 183 if ((va & AARCH64_ADDRESS_PAC_MASK) != AARCH64_ADDRESS_PAC_MASK) 184 return AARCH64_ADDRSPACE_UPPER_OUTOFRANGE; 185 return AARCH64_ADDRSPACE_UPPER; 186 } 187 188 addrtop = va & AARCH64_ADDRTOP_MSB; 189 if (addrtop == 0) { 190 /* lower address, and TBI0 disabled */ 191 if ((va & AARCH64_ADDRESS_TAGPAC_MASK) != 0) 192 return AARCH64_ADDRSPACE_LOWER_OUTOFRANGE; 193 return AARCH64_ADDRSPACE_LOWER; 194 } 195 /* upper address, and TBI1 disabled */ 196 if ((va & AARCH64_ADDRESS_TAGPAC_MASK) != AARCH64_ADDRESS_TAGPAC_MASK) 197 return AARCH64_ADDRSPACE_UPPER_OUTOFRANGE; 198 return AARCH64_ADDRSPACE_UPPER; 199 } 200 201 static inline vaddr_t 202 aarch64_untag_address(vaddr_t va) 203 { 204 uint64_t addrtop, tbi; 205 206 addrtop = va & AARCH64_ADDRTOP_TAG; 207 tbi = addrtop ? TCR_TBI1 : TCR_TBI0; 208 if (reg_tcr_el1_read() & tbi) { 209 if (addrtop == 0) { 210 /* lower address, and TBI0 enabled */ 211 return va & ~AARCH64_ADDRESS_TAG_MASK; 212 } 213 /* upper address, and TBI1 enabled */ 214 return va | AARCH64_ADDRESS_TAG_MASK; 215 } 216 217 /* TBI[01] is disabled, nothing to do */ 218 return va; 219 } 220 221 #endif /* _KERNEL */ 222 223 static __inline uint64_t 224 aarch64_strip_pac(uint64_t __val) 225 { 226 if (__val & AARCH64_ADDRTOP_TAG) 227 return __val | AARCH64_ADDRESS_TAGPAC_MASK; 228 return __val & ~AARCH64_ADDRESS_TAGPAC_MASK; 229 } 230 231 #endif /* _AARCH64_CPUFUNC_H_ */ 232