1.\" $NetBSD: pci_configure_bus.9,v 1.5 2002/02/13 08:18:47 ross Exp $ 2.\" 3.\" Copyright 2001 Wasabi Systems, Inc. 4.\" All rights reserved. 5.\" 6.\" Written by Allen Briggs for Wasabi Systems, Inc. 7.\" 8.\" Redistribution and use in source and binary forms, with or without 9.\" modification, are permitted provided that the following conditions 10.\" are met: 11.\" 1. Redistributions of source code must retain the above copyright 12.\" notice, this list of conditions and the following disclaimer. 13.\" 2. Redistributions in binary form must reproduce the above copyright 14.\" notice, this list of conditions and the following disclaimer in the 15.\" documentation and/or other materials provided with the distribution. 16.\" 3. All advertising materials mentioning features or use of this software 17.\" must display the following acknowledgement: 18.\" This product includes software developed for the NetBSD Project by 19.\" Wasabi Systems, Inc. 20.\" 4. The name of Wasabi Systems, Inc. may not be used to endorse 21.\" or promote products derived from this software without specific prior 22.\" written permission. 23.\" 24.\" THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 25.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26.\" TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27.\" PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 28.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34.\" POSSIBILITY OF SUCH DAMAGE. 35.\" 36.Dd February 11, 2002 37.Dt PCI_CONFIGURE_BUS 9 38.Os 39.Sh NAME 40.Nm pci_configure_bus , 41.Nm pci_conf_hook , 42.Nm pci_conf_interrupt 43.Nd perform PCI bus configuration 44.Sh SYNOPSIS 45.Fd #include \*[Lt]dev/pci/pciconf.h\*[Gt] 46.Ft int 47.Fo pci_configure_bus 48.Fa "pci_chipset_tag_t pc" 49.Fa "struct extent *ioext" 50.Fa "struct extent *memext" 51.Fa "struct extent *pmemext" 52.Fc 53.Sh DESCRIPTION 54The 55.Fn pci_configure_bus 56function configures a PCI bus for use. This involves: 57.Bl -bullet 58.It 59Defining bus numbers for all busses on the system, 60.It 61Setting the Base Address Registers for all devices, 62.It 63Setting up the interrupt line register for all devices, and 64.It 65Configuring bus latency timers for all devices. 66.El 67.Pp 68In traditional PCs and Alpha systems, the BIOS or firmware takes care 69of this task, but that is not the case for all systems. 70.Fn pci_configure_bus 71should be called prior to the auto-configuration of the bus. 72.Pp 73The 74.Fa pc 75argument is a machine-dependent tag used to specify the PCI chipset to the 76system. This should be the same value used with 77.Fn pci_make_tag . 78The extent arguments 79define memory extents from which the address space for the cards will be 80taken. These addresses should be in the PCI address space. The 81.Fa ioext 82extent is for PCI I/O accesses. The 83.Fa memext 84extent is for PCI memory accesses that might have side effects. I.e., 85that can not be cached. The 86.Fa pmemext 87extent is for PCI memory accesses that can be cached. The 88.Fa pmemext 89extent will be used for any ROMs and any memory regions that are marked as 90.Dq prefetchable 91in their BAR. If an implementation does not distinguish between 92prefetchable and non-prefetchable memory, it may pass NULL for 93.Fa pmemext . 94In this case, prefetchable memory allocations will be made from the 95non-prefetchable region. 96.Pp 97An implementation may choose to not have full configuration performed 98by 99.Fn pci_configure_bus 100on certain PCI devices, such as PCI host bridges or PCI bus analyzers 101which are instantiated as devices on the bus. In order for this to 102take place, the header 103.Aq Pa machine/pci_machdep.h 104must define the 105.Dv __HAVE_PCI_CONF_HOOK 106symbol (without a value), and a machine-dependent function 107.Fn pci_conf_hook 108(declared in the same header) 109must be defined. The prototype for this function is 110.Pp 111.Fn "int pci_conf_hook" "pci_chipset_tag_t pc" "int id" \ 112 "int bus" "int device" "int function" 113.Pp 114In this function, 115.Fa bus , 116.Fa device , 117and 118.Fa function 119uniquely identify the item being configured; 120in addition to this, the value of the device's PCI identification 121register is passed in 122.Fa id . 123For each device 124.Fn pci_conf_hook 125can then decide upon the amount of configuration to be performed by 126returning a bitwise inclusive-or of the following flags: 127.Bl -tag -width PCI_CONF_ENABLE_MEM -offset indent 128.It Dv PCI_CONF_MAP_IO 129Configure Base Address Registers that map I/O space 130.It Dv PCI_CONF_MAP_MEM 131Configure Base Address Registers that map memory space 132.It Dv PCI_CONF_MAP_ROM 133Configure Expansion ROM Base Address register 134.It Dv PCI_CONF_ENABLE_IO 135Enable I/O space accesses 136.It Dv PCI_CONF_ENABLE_MEM 137Enable memory space accesses 138.It Dv PCI_CONF_ENABLE_BM 139Enable bus mastering 140.El 141.Pp 142In addition, 143.Dv PCI_CONF_ALL 144specifies all of the above. 145.Pp 146One of the functions of 147.Fn pci_configure_bus 148is to configure interrupt 149.Dq line 150information. This must be done on a machine-dependent basis, so a 151machine-dependent function 152.Fn pci_conf_interrupt 153must be defined. The prototype for this function is 154.Pp 155.Fn "void pci_conf_interrupt" "pci_chipset_tag_t pc" "int bus" \ 156 "int device" "int function" "int swiz" "int *iline" 157.Pp 158In this function, 159.Fa bus , 160.Fa device , 161and 162.Fa function , 163uniquely identify the item being configured. The 164.Fa swiz 165argument is a 166.Dq swizzle , 167a sum of the device numbers of the primary interface of the bridges between 168the host bridge and the current device. The function is responsible for 169setting the value of 170.Fa iline . 171See chapter 9 of the 172.Dq PCI-to-PCI Bridge Architecture Specification 173for more information on swizzling (also known as interrupt routing). 174.Sh RETURN VALUES 175If successful 176.Fn pci_configure_bus 177returns 0. A non-zero return value means that the bus was not completely 178configured for some reason. A description of the failure will be displayed 179on the console. 180.Sh ENVIRONMENT 181The 182.Fn pci_configure_bus 183function is only included in the kernel if the kernel is compiled with 184the 185.Dv PCI_NETBSD_CONFIGURE 186option enabled. 187.Sh EXAMPLES 188The 189.Fn pci_conf_hook 190function in the walnut implementation looks like: 191.Pp 192.Bd -literal -compact 193int 194pci_conf_hook(pci_chipset_tag_t pc, int bus, int dev, int func, int id) 195{ 196 197 if ((PCI_VENDOR(id) == PCI_VENDOR_IBM && 198 PCI_PRODUCT(id) == PCI_PRODUCT_IBM_405GP) || 199 (PCI_VENDOR(id) == PCI_VENDOR_INTEL && 200 PCI_PRODUCT(id) == PCI_PRODUCT_INTEL_80960_RP)) { 201 /* Don't configure the bridge and PCI probe. */ 202 return 0; 203 } 204 return (PCI_CONF_ALL & ~PCI_CONF_MAP_ROM); 205} 206.Ed 207.Pp 208The 209.Fn pci_conf_interrupt 210function in the sandpoint implementation looks like: 211.Pp 212.Bd -literal -compact 213void 214pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int func, 215 int swiz, int *iline) 216{ 217 if (bus == 0) { 218 *iline = dev; 219 } else { 220 *iline = 13 + ((swiz + dev + 3) \*[Am] 3); 221 } 222} 223.Ed 224.Pp 225The BeBox has nearly 1GB of PCI I/O memory starting at processor address 2260x81000000 (PCI I/O address 0x01000000), and nearly 1GB of PCI memory 227starting at 0xC0000000 (PCI memory address 0x00000000). 228The 229.Fn pci_configure_bus 230function might be called as follows: 231.Pp 232.Bd -literal -compact 233 struct extent *ioext, *memext; 234 ... 235 ioext = extent_create("pciio", 0x01000000, 0x0fffffff, M_DEVBUF, 236 NULL, 0, EX_NOWAIT); 237 memext = extent_create("pcimem", 0x00000000, 0x0fffffff, M_DEVBUF, 238 NULL, 0, EX_NOWAIT); 239 ... 240 pci_configure_bus(0, ioext, memext, NULL); 241 ... 242 extent_destroy(ioext); 243 extent_destroy(memext); 244 ... 245.Ed 246.Pp 247Note that this must be called before the PCI bus is attached during 248autoconfiguration. 249.Sh SEE ALSO 250.Xr pci 4 , 251.Xr extent 9 252.Sh HISTORY 253.Fn pci_configure_bus 254was added in 255.Nx 1.6 . 256