1.\" $NetBSD: pci.9,v 1.7 2002/08/04 01:03:12 gmcgarry Exp $ 2.\" 3.\" Copyright (c) 2001 The NetBSD Foundation, Inc. 4.\" All rights reserved. 5.\" 6.\" This code is derived from software contributed to The NetBSD Foundation 7.\" by Gregory McGarry. 8.\" 9.\" Redistribution and use in source and binary forms, with or without 10.\" modification, are permitted provided that the following conditions 11.\" are met: 12.\" 1. Redistributions of source code must retain the above copyright 13.\" notice, this list of conditions and the following disclaimer. 14.\" 2. Redistributions in binary form must reproduce the above copyright 15.\" notice, this list of conditions and the following disclaimer in the 16.\" documentation and/or other materials provided with the distribution. 17.\" 3. All advertising materials mentioning features or use of this software 18.\" must display the following acknowledgement: 19.\" This product includes software developed by the NetBSD 20.\" Foundation, Inc. and its contributors. 21.\" 4. Neither the name of The NetBSD Foundation nor the names of its 22.\" contributors may be used to endorse or promote products derived 23.\" from this software without specific prior written permission. 24.\" 25.\" THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 26.\" ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27.\" TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28.\" PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 29.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35.\" POSSIBILITY OF SUCH DAMAGE. 36.\" 37.Dd June 19, 2001 38.Dt PCI 9 39.Os 40.Sh NAME 41.Nm PCI , 42.Nm pci_conf_read , 43.Nm pci_conf_write , 44.Nm pci_conf_print , 45.Nm pci_find_device , 46.Nm pci_get_capability , 47.Nm pci_mapreg_type , 48.Nm pci_mapreg_map , 49.Nm pci_mapreg_info , 50.Nm pci_intr_map , 51.Nm pci_intr_string , 52.Nm pci_intr_evcnt , 53.Nm pci_intr_establish , 54.Nm pci_intr_disestablish , 55.Nm pci_get_powerstate , 56.Nm pci_set_powerstate , 57.Nm pci_make_tag , 58.Nm pci_decompose_tag , 59.Nm pci_findvendor , 60.Nm pci_devinfo , 61.Nm PCI_VENDOR , 62.Nm PCI_PRODUCT , 63.Nm PCI_REVISION 64.Nd Peripheral Component Interconnect 65.Sh SYNOPSIS 66.Fd #include \*[Lt]machine/bus.h\*[Gt] 67.Fd #include \*[Lt]dev/pci/pcivar.h\*[Gt] 68.Fd #include \*[Lt]dev/pci/pcireg.h\*[Gt] 69.Fd #include \*[Lt]dev/pci/pcidevs.h\*[Gt] 70.Ft pcireg_t 71.Fn pci_conf_read "pci_chipset_tag_t pc" "pcitag_t tag" "int reg" 72.Ft void 73.Fn pci_conf_write "pci_chipset_tag_t pc" "pcitag_t tag" "int reg" \ 74"pcireg_t val" 75.Ft void 76.Fn pci_conf_print "pci_chipset_tag_t pc" "pcitag_t tag" \ 77"void (*func)(pci_chipset_tag_t, pcitag_t, const pcireg_t *)" 78.Ft int 79.Fn pci_find_device "struct pci_attach_args *pa" \ 80"int (*func)(struct pci_attach_args *)" 81.Ft int 82.Fn pci_get_capability "pci_chipset_tag_t pc" "pcitag_t tag" \ 83"int capid" "int *offsetp" "pcireg_t *valuep" 84.Ft pcireg_t 85.Fn pci_mapreg_type "pci_chipset_tag_t pc" "pcitag_t tag" "int reg" 86.Ft int 87.Fn pci_mapreg_map "struct pci_attach_args *pa" "int reg" \ 88"pcireg_t type" "int busflags" "bus_space_tag_t *tagp" \ 89"bus_space_handle_t *handlep" "bus_addr_t *basep" "bus_size_t *sizep" 90.Ft int 91.Fn pci_mapreg_info "pci_chipset_tag_t pc" "pcitag_t tag" "int reg" \ 92"pcireg_t type" "bus_addr_t *basep" "bus_size_t *sizep" "int *flagsp" 93.Ft int 94.Fn pci_intr_map "struct pci_attach_args *pa" "pci_intr_handle_t *ih" 95.Ft const char * 96.Fn pci_intr_string "pci_chipset_tag_t pc" "pci_intr_handle_t ih" 97.Ft const struct evcnt * 98.Fn pci_intr_evcnt "pci_chipset_tag_t pc" "pci_intr_handle_t ih" 99.Ft void * 100.Fn pci_intr_establish "pci_chipset_tag_t pc" "pci_intr_handle_t ih" \ 101"int level" "int (*handler)(void *)" "void *arg" 102.Ft void 103.Fn pci_intr_disestablish "pci_chipset_tag_t pc" "void *ih" 104.Ft int 105.Fn pci_set_powerstate "pci_chipset_tag_t pc" "pcitag_t tag" \ 106"int newstate" 107.Ft int 108.Fn pci_get_powerstate "pci_chipset_tag_t pc" "pcitag_t tag" 109.Ft pcitag_t 110.Fn pci_make_tag "pci_chipset_tag_t pc" "int bus" "int device" \ 111"int function" 112.Ft void 113.Fn pci_decompose_tag "pci_chipset_tag_t pc" "pcitag_t tag" \ 114"int *busp" "int *devicep" "int *functionp" 115.Ft char * 116.Fn pci_findvendor "pcireg_t id" 117.Ft void 118.Fn pci_devinfo "pcireg_t id" "pcireg_t class" "int show" "char *cp" 119.Ft int 120.Fn PCI_VENDOR "pcireg_t id" 121.Ft int 122.Fn PCI_PRODUCT "pcireg_t id" 123.Ft int 124.Fn PCI_REVISION "pcireg_t id" 125.Sh DESCRIPTION 126The machine-independent 127.Nm 128subsystem provides support for PCI devices. 129.Pp 130The PCI bus was initially developed by Intel in the early 1990's to 131replace the ISA bus for interfacing with their Pentium processor. The 132PCI specification is widely regarded as well designed, and the PCI bus 133has found widespread acceptance in machines ranging from Apple's 134PowerPC-based systems to Sun's UltraSPARC-based machines. 135.Pp 136The PCI bus is a multiplexed bus, allowing addresses and data on the same 137pins for a reduced number of pins. Data transfers can be 8-bit, 13816-bit or 32-bit. A 64-bit extended PCI bus is also defined. 139Multi-byte transfers are little-endian. The PCI bus operates up to 14033MHz and any device on the bus can be the bus master. 141.Pp 142AGP is a version of PCI optimised for high-throughput data rates, 143particularly for accelerated frame buffers. 144.Pp 145The PCI bus is a "plug and play" bus, in the sense that devices can be 146configured dynamically by software. The PCI interface chip on a PCI 147device bus presents a small window of registers into the PCI 148configuration space. These registers contain information about the 149device such as the vendor and a product ID. The configuration 150registers can also be written to by software to alter how the device 151interfaces to the PCI bus. An important register in the configuration 152space is the Base Address Register (BAR). The BAR is written to by 153software to map the device registers into a window of processor 154address space. Once this mapping is done, the device registers can be 155accessed relative to the base address. 156.Sh DATA TYPES 157Drivers for devices attached to the 158.Nm 159will make use of the following data types: 160.Bl -tag -width compact 161.It Fa pcireg_t 162Configuration space register. 163.It Fa pci_chipset_tag_t 164Chipset tag for the PCI bus. 165.It Fa pcitag_t 166Configuration tag describing the location and function of the PCI 167device. It contains the tuple 168.Ao 169bus, device, function 170.Ac . 171.It Fa pci_intr_handle_t 172The opaque handle describing an established interrupt handler. 173.It Fa struct pci_attach_args 174Devices have their identity recorded in this structure. It contains 175the following members: 176.Bd -literal 177 bus_space_tag_t pa_iot; /* pci i/o space tag */ 178 bus_space_tag_t pa_memt; /* pci mem space tag */ 179 bus_dma_tag_t pa_dmat; /* DMA tag */ 180 pci_chipset_tag_t pa_pc; 181 int pa_flags; /* flags */ 182 pcitag_t pa_tag; 183 pcireg_t pa_id; 184 pcireg_t pa_class; 185.Ed 186.El 187.Sh FUNCTIONS 188.Bl -tag -width compact 189.It Fn pci_conf_read "pc" "tag" "reg" 190Read from register 191.Fa reg 192in PCI configuration space. The argument 193.Fa tag 194is the PCI tag for the current device attached to PCI chipset 195.Fa pc . 196.It Fn pci_conf_write "pc" "tag" "reg" "val" 197Write to register 198.Fa reg 199in PCI configuration space. The argument 200.Fa tag 201is the PCI tag for the current device attached to PCI chipset 202.Fa pc . 203.It Fn pci_conf_print "pc" "tag" "func" 204Print out most of the registers in the PCI configuration for the 205device. The argument 206.Fa tag 207is the PCI tag for the current device attached to PCI chipset 208.Fa pc . 209The argument 210.Fa func 211is a function called by 212.Fn pci_conf_print 213to print the device-dependent registers. This function is only useful 214for driver development and is usually wrapped in pre-processor 215declarations. 216.It Fn pci_find_device "pa" "func" 217Find a device using a match function on all probed busses. The 218argument 219.Fa func 220is called by 221.Fn pci_find_device 222to match a device. The argument 223.Fa pa 224is filled in if the device is matched. 225.Fn pci_find_device 226returns 1 if the device is matched, and zero otherwise. This function 227is specifically for use by LKMs (see 228.Xr lkm 4 ) 229and its use otherwise is strongly discouraged. 230.It Fn pci_get_capability "pc" "tag" "capid" "offsetp" "valuep" 231Parse the device capability list in configuration space looking for 232capability 233.Fa capid . 234If 235.Fa offsetp 236is not NULL, the register offset in configuration space is returned in 237.Fa offsetp . 238If 239.Fa valuep 240is not NULL, the value of the capability is returned in 241.Fa valuep . 242The argument 243.Fa tag 244is the PCI tag for the current device attached to PCI chipset 245.Fa pc . 246This function returns 1 if the capability was found. If the 247capability was not found, it returns zero, and 248.Fa offsetp 249and 250.Fa valuep 251remain unchanged. 252.It Fn pci_mapreg_type "pc" "tag" "reg" 253Interrogates the Base Address Register (BAR) in configuration space 254specified by 255.Fa reg 256and returns the default (or current) mapping type. Valid returns 257values are: 258.Bl -tag -width compact 259.It PCI_MAPREG_TYPE_IO 260The mapping is to I/O address space. 261.It PCI_MAPREG_TYPE_MEM 262The mapping is to memory address space. 263.It PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT 264The mapping is to 64-bit memory address space. 265.It PCI_MAPREG_TYPE_ROM 266The mapping is to ROM. 267.El 268.sp 269The argument 270.Fa tag 271is the PCI tag for the current device attached to PCI chipset 272.Fa pc . 273.It Fo pci_mapreg_map 274.Fa "pa" "reg" "type" "busflags" "tagp" "handlep" 275.Fa "basep" "sizep" 276.Fc 277Maps the register windows for the device into kernel virtual address 278space. This function is generally only called during the driver 279attach step and takes a pointer to the 280.Em struct pci_attach_args 281in 282.Fa pa . 283The physical address of the mapping is in the Base Address Register 284(BAR) in configuration space specified by 285.Fa reg . 286Valid values for the type of mapping 287.Fa type 288are: 289.Bl -tag -width compact 290.It PCI_MAPREG_TYPE_IO 291The mapping should be to I/O address space. 292.It PCI_MAPREG_TYPE_MEM 293The mapping should be to memory address space. 294.It PCI_MAPREG_TYPE_ROM 295The mapping is to access ROM. 296.El 297.sp 298The argument 299.Fa busflags 300are bus-space flags passed to 301.Fn bus_space_map 302to perform the mapping (see 303.Xr bus_space 9 ) . 304The bus-space tag and handle for the mapped register window are 305returned in 306.Fa tagp 307and 308.Fa handlep 309respectively. The bus-address and size of the mapping are returned in 310.Fa basep 311and 312.Fa sizep 313respectively. If any of 314.Fa tagp , 315.Fa handlep , 316.Fa basep , 317or 318.Fa sizep 319are NULL then 320.Fn pci_mapreg_map 321does not define their return value. This function returns zero on 322success and non-zero on error. 323.It Fn pci_mapreg_info "pc" "tag" "reg" "type" "basep" "sizep" "flagsp" 324Performs the same operations as 325.Fn pci_mapreg_map 326but doesn't actually map the register window into kernel virtual 327address space. Returns the bus-address, size and bus flags in 328.Fa basep , 329.Fa sizep 330and 331.Fa flagsp 332respectively. These return values can be used by 333.Fn bus_space_map 334to actually map the register window into kernel virtual address space. 335This function is useful for setting up the registers in configuration 336space and deferring the mapping to a later time, such as in a 337bus-independent attachment routine. 338.Fa pci_mapreg_info 339returns zero on success and non-zero on failure. 340.It Fn pci_intr_map "pa" "ih" 341See 342.Xr pci_intr 9 . 343.It Fn pci_intr_string "pc" "ih" 344See 345.Xr pci_intr 9 . 346.It Fn pci_intr_evcnt "pc" "ih" 347See 348.Xr pci_intr 9 . 349.It Fn pci_intr_establish "pc" "ih" "level" "handler" "arg" 350See 351.Xr pci_intr 9 . 352.It Fn pci_intr_disestablish "pc" "ih" 353See 354.Xr pci_intr 9 . 355.It Fn pci_set_powerstate "pc" "tag" "newstate" 356Set power state of the device to newstate. Valid values for 357.Fa newstate 358are: 359.Pp 360.Bl -tag -width PCI_PWR_D0 -compact 361.It PCI_PWR_D0 362.It PCI_PWR_D1 363.It PCI_PWR_D2 364.It PCI_PWR_D3 365.El 366.It Fn pci_get_powerstate "pc" "tag" 367Get current power state of the device. 368.It Fn pci_make_tag "pc" "bus" "device" "function" 369Create a new PCI tag for the PCI device specified by the tuple 370.Ao 371bus, device, function 372.Ac . 373This function is not useful to the usual PCI device driver. It is 374generally used by drivers of multi-function devices when attaching 375other PCI device drivers to each function. 376.It Fn pci_decompose_tag "pc" "tag" "busp" "devicep" "fnp" 377Decompose the PCI tag 378.Fa tag 379generated by 380.Fn pci_make_tag 381into its 382.Ao 383bus, device, function 384.Ac 385tuple. 386.It Fn pci_findvendor "id" 387Return the string of the vendor name for the device specified by 388.Fa id . 389.It Fn pci_devinfo "id" "class" "show" "cp" 390Returns the description string from the in-kernel PCI database for the 391device described by 392.Fa id 393and 394.Fa class . 395The description string is returned in 396.Fa cp . 397The argument 398.Fa show 399specifies whether the PCI subsystem should report the string to the 400console. 401.It Fn PCI_VENDOR "id" 402Return the PCI vendor id for device 403.Fa id . 404.It Fn PCI_PRODUCT "id" 405Return the PCI product id for device 406.Fa id . 407.It Fn PCI_REVISION "id" 408Return the PCI product revision for device 409.Fa id . 410.El 411.Sh AUTOCONFIGURATION 412During autoconfiguration, a 413.Nm 414driver will receive a pointer to 415.Fa struct pci_attach_args 416describing the device attaches to the PCI bus. Drivers match the 417device using the 418.Fa pa_id 419member using 420.Fn PCI_VENDOR . 421.Fn PCI_PRODUCT 422and 423.Fn PCI_REVISION . 424.Pp 425During the driver attach step, drivers can read the device 426configuration space using 427.Fn pci_conf_read . 428The meaning attached to registers in the PCI configuration space are 429device-dependent, but will usually contain physical addresses of the 430device register windows. Device options can also be stored into the 431PCI configuration space using 432.Fn pci_conf_write . 433For example, the driver can request support for bus-mastering DMA by 434writing the option to the PCI configuration space. 435.Pp 436Device capabilities can be queried using 437.Fn pci_get_capability , 438and returns device-specific information which can be found in the PCI 439configuration space to alter device operation. 440.Pp 441After reading the physical addresses of the device register windows 442from configuration space, these windows must be mapped into kernel 443virtual address space using 444.Fn pci_mapreg_map . 445Device registers can now be accessed using the standard bus-space API 446(see 447.Xr bus_space 9 ) . 448.Pp 449Details of using PCI interrupts is described in 450.Xr pci_intr 9 . 451.Sh DMA SUPPORT 452The PCI bus supports bus-mastering operations from any device on the 453bus. The DMA facilities are accessed through the standard 454.Xr bus_dma 9 455interface. To support DMA transfers from the device to the host, it 456is necessary to enable bus-mastering in the PCI configuration space 457for the device. 458.Pp 459During system shutdown, it is necessary to abort any DMA transfers in 460progress by registering a shutdown hook (see 461.Xr shutdownhook_establish 9 ) . 462.Sh CODE REFERENCES 463This section describes places within the 464.Nx 465source tree where actual code implementing or utilising the 466machine-independent PCI subsystem can be found. All pathnames are 467relative to 468.Pa /usr/src . 469.Pp 470The PCI subsystem itself is implemented within the files 471.Pa sys/dev/pci/pci.c , 472.Pa sys/dev/pci/pci_subr.c , 473.Pa sys/dev/pci/pci_map.c , 474.Pa sys/dev/pci/pci_quirks.c , 475and 476.Pa sys/dev/pci/pciconf.c . 477Machine-dependent portions are implemented within the file 478.Pa sys/arch/\*[Lt]arch\*[Gt]/pci/pci_machdep.c . 479.Pp 480The database of known devices exists within the file 481.Pa sys/dev/pci/pcidevs_data.h 482and is generated automatically from the file 483.Pa sys/dev/pci/pcidevs . 484New vendor and product identifiers should be added to this 485file. The database can be regenerated using the Makefile 486.Pa sys/dev/pci/Makefile.pcidevs . 487.Sh SEE ALSO 488.Xr pci 4 , 489.Xr autoconf 9 , 490.Xr bus_dma 9 , 491.Xr bus_space 9 , 492.Xr driver 9 , 493.Xr pci_configure_bus 9 , 494.Xr pci_intr 9 , 495.Xr shutdownhook_establish 9 496.Sh HISTORY 497The machine-independent PCI subsystem appeared in 498.Nx 1.2 . 499