1Copyright 2003, 2004, 2006, 2008 Free Software Foundation, Inc. 2 3This file is part of the GNU MP Library. 4 5The GNU MP Library is free software; you can redistribute it and/or modify 6it under the terms of the GNU Lesser General Public License as published by 7the Free Software Foundation; either version 3 of the License, or (at your 8option) any later version. 9 10The GNU MP Library is distributed in the hope that it will be useful, but 11WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 12or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public 13License for more details. 14 15You should have received a copy of the GNU Lesser General Public License 16along with the GNU MP Library. If not, see http://www.gnu.org/licenses/. 17 18 19 20 21 22 AMD64 MPN SUBROUTINES 23 24 25This directory contains mpn functions for AMD64 chips. It is also useful 26for 64-bit Pentiums, and "Core 2". 27 28 29 RELEVANT OPTIMIZATION ISSUES 30 31The Opteron and Athlon64 can sustain up to 3 instructions per cycle, but in 32practice that is only possible for integer instructions. But almost any 33three integer instructions can issue simultaneously, including any 3 ALU 34operations, including shifts. Up to two memory operations can issue each 35cycle. 36 37Scheduling typically requires that load-use instructions are split into 38separate load and use instructions. That requires more decode resources, 39and it is rarely a win. Opteron/Athlon64 have deep out-of-order core. 40 41 42Optimizing for 64-bit Pentium4 is probably a waste of time, as the most 43critical instructions are very poorly implemented here. Perhaps we could 44save a cycle or two, but the most common loops now run at between 10 and 22 45cycles, so a saved cycle isn't too exciting. 46 47 48The new spin of the venerable P6 core, the "Core 2" is much better than the 49Pentium4 for the GMP loops. Its integer pipeline is somewhat similar to to 50the Opteron/Athlon64 pipeline, except that the GMP favourites ADC/SBB and 51MUL are slower. Furthermore, an INC/DEC followed by ADC/SBB incur a 52pipeline stall of around 10 cycles. The default mpn_add_n and mpn_sub_n 53code suffers badly from the stall. The code in the core2 subdirectory uses 54the almost forgotten instruction JRCXZ for loop control, and updates the 55induction variable using LEA. 56 57 58 59REFERENCES 60 61"System V Application Binary Interface AMD64 Architecture Processor 62Supplement", draft version 0.99, December 2007. 63http://www.x86-64.org/documentation/abi.pdf 64