1Copyright 1999, 2000, 2001, 2003, 2004, 2005 Free Software Foundation, Inc. 2 3This file is part of the GNU MP Library. 4 5The GNU MP Library is free software; you can redistribute it and/or modify 6it under the terms of the GNU Lesser General Public License as published by 7the Free Software Foundation; either version 3 of the License, or (at your 8option) any later version. 9 10The GNU MP Library is distributed in the hope that it will be useful, but 11WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 12or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public 13License for more details. 14 15You should have received a copy of the GNU Lesser General Public License 16along with the GNU MP Library. If not, see http://www.gnu.org/licenses/. 17 18 19 20 POWERPC-64 MPN SUBROUTINES 21 22 23This directory contains mpn functions for 64-bit PowerPC chips. 24 25 26CODE ORGANIZATION 27 28 mpn/powerpc64 mode-neutral code 29 mpn/powerpc64/mode32 code for mode32 30 mpn/powerpc64/mode64 code for mode64 31 32 33The mode32 and mode64 sub-directories contain code which is for use in the 34respective chip mode, 32 or 64. The top-level directory is code that's 35unaffected by the mode. 36 37The "adde" instruction is the main difference between mode32 and mode64. It 38operates on either on a 32-bit or 64-bit quantity according to the chip mode. 39Other instructions have an operand size in their opcode and hence don't vary. 40 41 42 43POWER3/PPC630 pipeline information: 44 45Decoding is 4-way + branch and issue is 8-way with some out-of-order 46capability. 47 48Functional units: 49LS1 - ld/st unit 1 50LS2 - ld/st unit 2 51FXU1 - integer unit 1, handles any simple integer instruction 52FXU2 - integer unit 2, handles any simple integer instruction 53FXU3 - integer unit 3, handles integer multiply and divide 54FPU1 - floating-point unit 1 55FPU2 - floating-point unit 2 56 57Memory: Any two memory operations can issue, but memory subsystem 58 can sustain just one store per cycle. No need for data 59 prefetch; the hardware has very sophisticated prefetch logic. 60Simple integer: 2 operations (such as add, rl*) 61Integer multiply: 1 operation every 9th cycle worst case; exact timing depends 62 on 2nd operand's most significant bit position (10 bits per 63 cycle). Multiply unit is not pipelined, only one multiply 64 operation in progress is allowed. 65Integer divide: ? 66Floating-point: Any plain 2 arithmetic instructions (such as fmul, fadd, and 67 fmadd), latency 4 cycles. 68Floating-point divide: 69 ? 70Floating-point square root: 71 ? 72 73POWER3/PPC630 best possible times for the main loops: 74shift: 1.5 cycles limited by integer unit contention. 75 With 63 special loops, one for each shift count, we could 76 reduce the needed integer instructions to 2, which would 77 reduce the best possible time to 1 cycle. 78add/sub: 1.5 cycles, limited by ld/st unit contention. 79mul: 18 cycles (average) unless floating-point operations are used, 80 but that would only help for multiplies of perhaps 10 and more 81 limbs. 82addmul/submul:Same situation as for mul. 83 84 85POWER4/PPC970 and POWER5 pipeline information: 86 87This is a very odd pipeline, it is basically a VLIW masquerading as a plain 88architecture. Its issue rules are not made public, and since it is so weird, 89it is very hard to figure out any useful information from experimentation. 90An example: 91 92 A well-aligned loop with nop's take 3, 4, 6, 7, ... cycles. 93 3 cycles for 0, 1, 2, 3, 4, 5, 6, 7 nop's 94 4 cycles for 8, 9, 10, 11, 12, 13, 14, 15 nop's 95 6 cycles for 16, 17, 18, 19, 20, 21, 22, 23 nop's 96 7 cycles for 24, 25, 26, 27 nop's 97 8 cycles for 28, 29, 30, 31 nop's 98 ... continues regularly 99 100 101Functional units: 102LS1 - ld/st unit 1 103LS2 - ld/st unit 2 104FXU1 - integer unit 1, handles any integer instruction 105FXU2 - integer unit 2, handles any integer instruction 106FPU1 - floating-point unit 1 107FPU2 - floating-point unit 2 108 109While this is one integer unit less than POWER3/PPC630, the remaining units 110are more powerful; here they handle multiply and divide. 111 112Memory: 2 ld/st. Stores go to the L2 cache, which can sustain just 113 one store per cycle. 114 L1 load latency: to gregs 3-4 cycles, to fregs 5-6 cycles. 115 Operations that modify the address register might be split 116 to use also a an integer issue slot. 117Simple integer: 2 operations every cycle, latency 2. 118Integer multiply: 2 operations every 6th cycle, latency 7 cycles. 119Integer divide: ? 120Floating-point: Any plain 2 arithmetic instructions (such as fmul, fadd, and 121 fmadd), latency 6 cycles. 122Floating-point divide: 123 ? 124Floating-point square root: 125 ? 126 127 128IDEAS 129 130*mul_1: Handling one limb using mulld/mulhdu and two limbs using floating- 131point operations should give performance of about 20 cycles for 3 limbs, or 7 132cycles/limb. 133 134We should probably split the single-limb operand in 32-bit chunks, and the 135multi-limb operand in 16-bit chunks, allowing us to accumulate well in fp 136registers. 137 138Problem is to get 32-bit or 16-bit words to the fp registers. Only 64-bit fp 139memops copies bits without fiddling with them. We might therefore need to 140load to integer registers with zero extension, store as 64 bits into temp 141space, and then load to fp regs. Alternatively, load directly to fp space 142and add well-chosen constants to get cancelation. (Other part after given by 143subsequent subtraction.) 144 145Possible code mix for load-via-intregs variant: 146 147lwz,std,lfd 148fmadd,fmadd,fmul,fmul 149fctidz,stfd,ld,fctidz,stfd,ld 150add,adde 151lwz,std,lfd 152fmadd,fmadd,fmul,fmul 153fctidz,stfd,ld,fctidz,stfd,ld 154add,adde 155srd,sld,add,adde,add,adde 156