1Copyright 1999, 2001, 2002, 2004 Free Software Foundation, Inc. 2 3This file is part of the GNU MP Library. 4 5The GNU MP Library is free software; you can redistribute it and/or modify 6it under the terms of either: 7 8 * the GNU Lesser General Public License as published by the Free 9 Software Foundation; either version 3 of the License, or (at your 10 option) any later version. 11 12or 13 14 * the GNU General Public License as published by the Free Software 15 Foundation; either version 2 of the License, or (at your option) any 16 later version. 17 18or both in parallel, as here. 19 20The GNU MP Library is distributed in the hope that it will be useful, but 21WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 22or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 23for more details. 24 25You should have received copies of the GNU General Public License and the 26GNU Lesser General Public License along with the GNU MP Library. If not, 27see https://www.gnu.org/licenses/. 28 29 30 31 32This directory contains mpn functions for 64-bit PA-RISC 2.0. 33 34PIPELINE SUMMARY 35 36The PA8x00 processors have an orthogonal 4-way out-of-order pipeline. Each 37cycle two ALU operations and two MEM operations can issue, but just one of the 38MEM operations may be a store. The two ALU operations can be almost any 39combination of non-memory operations. Unlike every other processor, integer 40and fp operations are completely equal here; they both count as just ALU 41operations. 42 43Unfortunately, some operations cause hickups in the pipeline. Combining 44carry-consuming operations like ADD,DC with operations that does not set carry 45like ADD,L cause long delays. Skip operations also seem to cause hickups. If 46several ADD,DC are issued consecutively, or if plain carry-generating ADD feed 47ADD,DC, stalling does not occur. We can effectively issue two ADD,DC 48operations/cycle. 49 50Latency scheduling is not as important as making sure to have a mix of ALU and 51MEM operations, but for full pipeline utilization, it is still a good idea to 52do some amount of latency scheduling. 53 54Like for all other processors, RAW memory scheduling is critically important. 55Since integer multiplication takes place in the floating-point unit, the GMP 56code needs to handle this problem frequently. 57 58STATUS 59 60* mpn_lshift and mpn_rshift run at 1.5 cycles/limb on PA8000 and at 1.0 61 cycles/limb on PA8500. With latency scheduling, the numbers could 62 probably be improved to 1.0 cycles/limb for all PA8x00 chips. 63 64* mpn_add_n and mpn_sub_n run at 2.0 cycles/limb on PA8000 and at about 65 1.6875 cycles/limb on PA8500. With latency scheduling, this could 66 probably be improved to get close to 1.5 cycles/limb. A problem is the 67 stalling of carry-inputting instructions after instructions that do not 68 write to carry. 69 70* mpn_mul_1, mpn_addmul_1, and mpn_submul_1 run at between 5.625 and 6.375 71 on PA8500 and later, and about a cycle/limb slower on older chips. The 72 code uses ADD,DC for adjacent limbs, and relies heavily on reordering. 73 74 75REFERENCES 76 77Hewlett Packard, "64-Bit Runtime Architecture for PA-RISC 2.0", version 3.3, 78October 1997. 79