1:option:::insn-bit-size:16 2:option:::hi-bit-nr:15 3 4 5:option:::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X 6:option:::format-names:XI,XII,XIII 7:option:::format-names:XIV,XV 8:option:::format-names:Z 9:option:::format-names:F_I 10 11 12:model:::v850:v850: 13 14:option:::multi-sim:true 15:model:::v850e:v850e: 16:option:::multi-sim:true 17:model:::v850e1:v850e1: 18:option:::multi-sim:true 19:model:::v850e2:v850e2: 20:option:::multi-sim:true 21:model:::v850e2v3:v850e2v3: 22:option:::multi-sim:true 23:model:::v850e3v5:v850e3v5: 24 25// Cache macros 26 27:cache:::unsigned:reg1:RRRRR:(RRRRR) 28:cache:::unsigned:reg2:rrrrr:(rrrrr) 29:cache:::unsigned:reg3:wwwww:(wwwww) 30:cache:::unsigned:reg4:W,WWWW:(W + (WWWW << 1)) 31 32:cache:::unsigned:reg1e:RRRR:(RRRR << 1) 33:cache:::unsigned:reg2e:rrrr:(rrrr << 1) 34:cache:::unsigned:reg3e:wwww:(wwww << 1) 35:cache:::unsigned:reg4e:mmmm:(mmmm << 1) 36 37:cache:::unsigned:disp4:dddd:(dddd) 38:cache:::unsigned:disp5:dddd:(dddd << 1) 39:cache:::unsigned:disp7:ddddddd:ddddddd 40:cache:::unsigned:disp8:ddddddd:(ddddddd << 1) 41:cache:::unsigned:disp8:dddddd:(dddddd << 2) 42:cache:::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1) 43:cache:::unsigned:disp16:dddddddddddddddd:EXTEND16 (dddddddddddddddd) 44:cache:::unsigned:disp16:ddddddddddddddd: EXTEND16 (ddddddddddddddd << 1) 45:cache:::unsigned:disp17:d,ddddddddddddddd:SEXT32 (((d <<16) + (ddddddddddddddd << 1)), 17 - 1) 46:cache:::unsigned:disp22:dddddd,ddddddddddddddd: SEXT32 ((dddddd << 16) + (ddddddddddddddd << 1), 22 - 1) 47:cache:::unsigned:disp23:ddddddd,dddddddddddddddd: SEXT32 ((ddddddd) + (dddddddddddddddd << 7), 23 - 1) 48:cache:::unsigned:disp23:dddddd,dddddddddddddddd: SEXT32 ((dddddd << 1) + (dddddddddddddddd << 7), 23 - 1) 49 50:cache:::unsigned:imm5:iiiii:SEXT32 (iiiii, 4) 51:cache:::unsigned:imm6:iiiiii:iiiiii 52:cache:::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1) 53:cache:::unsigned:imm5:iiii:(32 - (iiii << 1)) 54:cache:::unsigned:simm16:iiiiiiiiiiiiiiii:EXTEND16 (iiiiiiiiiiiiiiii) 55:cache:::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii 56:cache:::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII) 57:cache:::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd) 58 59:cache:::unsigned:vector:iiiii:iiiii 60 61:cache:::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL) 62:cache:::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL) 63 64:cache:::unsigned:bit3:bbb:bbb 65:cache:::unsigned:bit4:bbbb:bbbb 66:cache:::unsigned:bit13:B,BBB:((B << 3) + BBB) 67 68 69// What do we do with an illegal instruction? 70:internal::::illegal: 71{ 72 sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n", 73 (unsigned long) cia); 74 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL); 75} 76 77 78 79// ADD 80rrrrr,001110,RRRRR:I:::add 81"add r<reg1>, r<reg2>" 82{ 83 COMPAT_1 (OP_1C0 ()); 84} 85 86rrrrr,010010,iiiii:II:::add 87"add <imm5>,r<reg2>" 88{ 89 COMPAT_1 (OP_240 ()); 90} 91 92 93 94// ADDI 95rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi 96"addi <simm16>, r<reg1>, r<reg2>" 97{ 98 COMPAT_2 (OP_600 ()); 99} 100 101 102 103// ADF 104rrrrr,111111,RRRRR + wwwww,011101,cccc!13,0:XI:::adf 105*v850e2 106*v850e2v3 107*v850e3v5 108"adf %s<cccc>, r<reg1>, r<reg2>, r<reg3>" 109{ 110 int cond = condition_met (cccc); 111 TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]); 112 GR[reg3] = GR[reg1] + GR[reg2] + (cond ? 1 : 0); 113 TRACE_ALU_RESULT1 (GR[reg3]); 114} 115 116 117 118// AND 119rrrrr,001010,RRRRR:I:::and 120"and r<reg1>, r<reg2>" 121{ 122 COMPAT_1 (OP_140 ()); 123} 124 125 126 127// ANDI 128rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi 129"andi <uimm16>, r<reg1>, r<reg2>" 130{ 131 COMPAT_2 (OP_6C0 ()); 132} 133 134 135 136// Map condition code to a string 137:%s::::cccc:int cccc 138{ 139 switch (cccc) 140 { 141 case 0xf: return "gt"; 142 case 0xe: return "ge"; 143 case 0x6: return "lt"; 144 145 case 0x7: return "le"; 146 147 case 0xb: return "h"; 148 case 0x9: return "nl"; 149 case 0x1: return "l"; 150 151 case 0x3: return "nh"; 152 153 case 0x2: return "e"; 154 155 case 0xa: return "ne"; 156 157 case 0x0: return "v"; 158 case 0x8: return "nv"; 159 case 0x4: return "n"; 160 case 0xc: return "p"; 161 /* case 0x1: return "c"; */ 162 /* case 0x9: return "nc"; */ 163 /* case 0x2: return "z"; */ 164 /* case 0xa: return "nz"; */ 165 case 0x5: return "r"; /* always */ 166 case 0xd: return "sa"; 167 } 168 return "(null)"; 169} 170 171 172// Bcond 173ddddd,1011,ddd,cccc:III:::Bcond 174"b%s<cccc> <disp9>" 175{ 176 int cond; 177 if ((ddddd == 0x00) && (ddd == 0x00) && (cccc == 0x05)) { 178 // Special case - treat "br *" like illegal instruction 179 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP); 180 } else { 181 cond = condition_met (cccc); 182 if (cond) 183 nia = cia + disp9; 184 TRACE_BRANCH1 (cond); 185 } 186} 187 18800000111111,d,cccc + ddddddddddddddd,1:VII:::Bcond 189"breakpoint":((disp17 == 0) && (cccc == 0x05)) 190"b%s<cccc> <disp17>" 191*v850e2v3 192*v850e3v5 193{ 194 int cond; 195 cond = condition_met (cccc); 196 if (cond) 197 nia = cia + disp17; 198 TRACE_BRANCH_INPUT1 (cond); 199 TRACE_BRANCH_RESULT (nia); 200} 201 202 203 204// BSH 205rrrrr,11111100000 + wwwww,01101000010:XII:::bsh 206*v850e 207*v850e1 208*v850e2 209*v850e2v3 210*v850e3v5 211"bsh r<reg2>, r<reg3>" 212{ 213 unsigned32 value; 214 TRACE_ALU_INPUT1 (GR[reg2]); 215 216 value = (MOVED32 (GR[reg2], 23, 16, 31, 24) 217 | MOVED32 (GR[reg2], 31, 24, 23, 16) 218 | MOVED32 (GR[reg2], 7, 0, 15, 8) 219 | MOVED32 (GR[reg2], 15, 8, 7, 0)); 220 221 GR[reg3] = value; 222 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 223 if ((value & 0xffff) == 0) PSW |= PSW_Z; 224 if (value & 0x80000000) PSW |= PSW_S; 225 if (((value & 0xff) == 0) || ((value & 0xff00) == 0)) PSW |= PSW_CY; 226 227 TRACE_ALU_RESULT (GR[reg3]); 228} 229 230 231 232// BSW 233rrrrr,11111100000 + wwwww,01101000000:XII:::bsw 234*v850e 235*v850e1 236*v850e2 237*v850e2v3 238*v850e3v5 239"bsw r<reg2>, r<reg3>" 240{ 241#define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080) 242 unsigned32 value; 243 TRACE_ALU_INPUT1 (GR[reg2]); 244 245 value = GR[reg2]; 246 value >>= 24; 247 value |= (GR[reg2] << 24); 248 value |= ((GR[reg2] << 8) & 0x00ff0000); 249 value |= ((GR[reg2] >> 8) & 0x0000ff00); 250 GR[reg3] = value; 251 252 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 253 254 if (value == 0) PSW |= PSW_Z; 255 if (value & 0x80000000) PSW |= PSW_S; 256 if (WORDHASNULLBYTE (value)) PSW |= PSW_CY; 257 258 TRACE_ALU_RESULT (GR[reg3]); 259} 260 261 262 263// CALLT 2640000001000,iiiiii:II:::callt 265*v850e 266*v850e1 267*v850e2 268*v850e2v3 269*v850e3v5 270"callt <imm6>" 271{ 272 unsigned32 adr; 273 unsigned32 off; 274 CTPC = cia + 2; 275 CTPSW = PSW; 276 adr = (CTBP & ~1) + (imm6 << 1); 277 off = load_mem (adr, 2) & ~1; /* Force alignment */ 278 nia = (CTBP & ~1) + off; 279 TRACE_BRANCH3 (adr, CTBP, off); 280} 281 282 283 284// CAXI 285rrrrr,111111,RRRRR + wwwww,00011101110:IX:::caxi 286*v850e2 287*v850e2v3 288*v850e3v5 289"caxi [reg1], reg2, reg3" 290{ 291 unsigned int z,s,cy,ov; 292 unsigned32 addr; 293 unsigned32 token,result; 294 295 addr = GR[reg1]; 296 297 if (mpu_load_mem_test(sd, addr, 4, reg1) 298 && mpu_store_mem_test(sd, addr, 4, reg1)) 299 { 300 token = load_data_mem (sd, addr, 4); 301 302 TRACE_ALU_INPUT2 (token, GR[reg2]); 303 304 result = GR[reg2] - token; 305 306 z = (result == 0); 307 s = (result & 0x80000000); 308 cy = (GR[reg2] < token); 309 ov = ((GR[reg2] & 0x80000000) != (token & 0x80000000) 310 && (GR[reg2] & 0x80000000) != (result & 0x80000000)); 311 312 if (result == 0) 313 { 314 store_data_mem (sd, addr, 4, GR[reg3]); 315 GR[reg3] = token; 316 } 317 else 318 { 319 store_data_mem (sd, addr, 4, token); 320 GR[reg3] = token; 321 } 322 323 /* Set condition codes. */ 324 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 325 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 326 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); 327 328 TRACE_ALU_RESULT1 (GR[reg3]); 329 } 330} 331 332 333// CLR1 33410,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1 335"clr1 <bit3>, <disp16>[r<reg1>]" 336{ 337 COMPAT_2 (OP_87C0 ()); 338} 339 340rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1 341*v850e 342*v850e1 343*v850e2 344*v850e2v3 345*v850e3v5 346"clr1 r<reg2>, [r<reg1>]" 347{ 348 COMPAT_2 (OP_E407E0 ()); 349} 350 351 352 353// CTRET 3540000011111100000 + 0000000101000100:X:::ctret 355*v850e 356*v850e1 357*v850e2 358*v850e2v3 359*v850e3v5 360"ctret" 361{ 362 nia = (CTPC & ~1); 363 PSW = (CTPSW & (CPU)->psw_mask); 364 TRACE_BRANCH1 (PSW); 365} 366 367 368 369// CMOV 370rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov 371*v850e 372*v850e1 373*v850e2 374*v850e2v3 375*v850e3v5 376"cmov %s<cccc>, r<reg1>, r<reg2>, r<reg3>" 377{ 378 int cond = condition_met (cccc); 379 TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]); 380 GR[reg3] = cond ? GR[reg1] : GR[reg2]; 381 TRACE_ALU_RESULT (GR[reg3]); 382} 383 384rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov 385*v850e 386*v850e1 387*v850e2 388*v850e2v3 389*v850e3v5 390"cmov %s<cccc>, <imm5>, r<reg2>, r<reg3>" 391{ 392 int cond = condition_met (cccc); 393 TRACE_ALU_INPUT3 (cond, imm5, GR[reg2]); 394 GR[reg3] = cond ? imm5 : GR[reg2]; 395 TRACE_ALU_RESULT (GR[reg3]); 396} 397 398 399 400// CMP 401rrrrr,001111,RRRRR:I:::cmp 402"cmp r<reg1>, r<reg2>" 403{ 404 COMPAT_1 (OP_1E0 ()); 405} 406 407rrrrr,010011,iiiii:II:::cmp 408"cmp <imm5>, r<reg2>" 409{ 410 COMPAT_1 (OP_260 ()); 411} 412 413 414 415// DI 4160000011111100000 + 0000000101100000:X:::di 417"di" 418{ 419 COMPAT_2 (OP_16007E0 ()); 420} 421 422 423 424// DISPOSE 425// 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose 426// "dispose <imm5>, <list12>" 4270000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose 428*v850e 429*v850e1 430*v850e2 431*v850e2v3 432*v850e3v5 433"dispose <imm5>, <list12>":RRRRR == 0 434"dispose <imm5>, <list12>, [reg1]" 435{ 436 int i; 437 SAVE_2; 438 439 trace_input ("dispose", OP_PUSHPOP1, 0); 440 441 SP += (OP[3] & 0x3e) << 1; 442 443 /* Load the registers with lower number registers being retrieved 444 from higher addresses. */ 445 for (i = 12; i--;) 446 if ((OP[3] & (1 << type1_regs[ i ]))) 447 { 448 State.regs[ 20 + i ] = load_mem (SP, 4); 449 SP += 4; 450 } 451 452 if ((OP[3] & 0x1f0000) != 0) 453 { 454 nia = State.regs[ (OP[3] >> 16) & 0x1f]; 455 } 456 457 trace_output (OP_PUSHPOP1); 458} 459 460 461 462// DIV 463rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div 464*v850e 465*v850e1 466*v850e2 467*v850e2v3 468*v850e3v5 469"div r<reg1>, r<reg2>, r<reg3>" 470{ 471 COMPAT_2 (OP_2C007E0 ()); 472} 473 474 475// DIVH 476rrrrr!0,000010,RRRRR!0:I:::divh 477"divh r<reg1>, r<reg2>" 478{ 479 unsigned32 ov, s, z; 480 signed long int op0, op1, result; 481 482 trace_input ("divh", OP_REG_REG, 0); 483 484 PC = cia; 485 OP[0] = instruction_0 & 0x1f; 486 OP[1] = (instruction_0 >> 11) & 0x1f; 487 488 /* Compute the result. */ 489 op0 = EXTEND16 (State.regs[OP[0]]); 490 op1 = State.regs[OP[1]]; 491 492 if (op0 == -1 && op1 == 0x80000000) 493 { 494 PSW &= ~PSW_Z; 495 PSW |= PSW_OV | PSW_S; 496 State.regs[OP[1]] = 0x80000000; 497 } 498 else if (op0 == 0) 499 { 500 PSW |= PSW_OV; 501 } 502 else 503 { 504 result = (signed32) op1 / op0; 505 ov = 0; 506 507 /* Compute the condition codes. */ 508 z = (result == 0); 509 s = (result & 0x80000000); 510 511 /* Store the result and condition codes. */ 512 State.regs[OP[1]] = result; 513 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 514 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (ov ? PSW_OV : 0)); 515 } 516 517 trace_output (OP_REG_REG); 518 519 PC += 2; 520 nia = PC; 521} 522 523rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh 524*v850e 525*v850e1 526*v850e2 527*v850e2v3 528*v850e3v5 529"divh r<reg1>, r<reg2>, r<reg3>" 530{ 531 COMPAT_2 (OP_28007E0 ()); 532} 533 534 535// DIVHU 536rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu 537*v850e 538*v850e1 539*v850e2 540*v850e2v3 541*v850e3v5 542"divhu r<reg1>, r<reg2>, r<reg3>" 543{ 544 COMPAT_2 (OP_28207E0 ()); 545} 546 547 548// DIVU 549rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu 550*v850e 551*v850e1 552*v850e2 553*v850e2v3 554*v850e3v5 555"divu r<reg1>, r<reg2>, r<reg3>" 556{ 557 COMPAT_2 (OP_2C207E0 ()); 558} 559 560 561// DIVQ 562rrrrr,111111,RRRRR + wwwww,01011111100:XI:::divq 563*v850e2 564*v850e2v3 565*v850e3v5 566"divq r<reg1>, r<reg2>, r<reg3>" 567{ 568 unsigned int quotient; 569 unsigned int remainder; 570 unsigned int divide_by; 571 unsigned int divide_this; 572 573 TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]); 574 575 divide_by = GR[reg1]; 576 divide_this = GR[reg2]; 577 v850_div (sd, divide_by, divide_this, "ient, &remainder); 578 GR[reg2] = quotient; 579 GR[reg3] = remainder; 580 581 TRACE_ALU_RESULT2 (GR[reg2], GR[reg3]); 582} 583 584 585// DIVQU 586rrrrr,111111,RRRRR + wwwww,01011111110:XI:::divqu 587*v850e2 588*v850e2v3 589*v850e3v5 590"divq r<reg1>, r<reg2>, r<reg3>" 591{ 592 unsigned int quotient; 593 unsigned int remainder; 594 unsigned int divide_by; 595 unsigned int divide_this; 596 597 TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]); 598 599 divide_by = GR[reg1]; 600 divide_this = GR[reg2]; 601 v850_divu (sd, divide_by, divide_this, "ient, &remainder); 602 GR[reg2] = quotient; 603 GR[reg3] = remainder; 604 605 TRACE_ALU_RESULT2 (GR[reg2], GR[reg3]); 606} 607 608 609// EI 6101000011111100000 + 0000000101100000:X:::ei 611"ei" 612{ 613 COMPAT_2 (OP_16087E0 ()); 614} 615 616 617 618// EIRET 6190000011111100000 + 0000000101001000:X:::eiret 620"eiret" 621*v850e2 622*v850e2v3 623*v850e3v5 624{ 625 TRACE_ALU_INPUT1 (MPM & MPM_AUE); 626 627 nia = EIPC; /* next PC */ 628 if (MPM & MPM_AUE) 629 { 630 PSW = EIPSW; 631 } 632 else 633 { 634 PSW = (PSW & (PSW_NPV | PSW_DMP | PSW_IMP)) 635 | (EIPSW & ~(PSW_NPV | PSW_DMP | PSW_IMP)); 636 } 637 638 TRACE_ALU_RESULT1 (PSW); 639 TRACE_BRANCH_RESULT (nia); 640} 641 642 643 644// FERET 6450000011111100000 + 0000000101001010:X:::feret 646"feret" 647*v850e2 648*v850e2v3 649*v850e3v5 650{ 651 TRACE_ALU_INPUT1 (MPM & MPM_AUE); 652 653 nia = FEPC; /* next PC */ 654 if (MPM & MPM_AUE) 655 { 656 PSW = FEPSW; 657 } 658 else 659 { 660 PSW = (PSW & (PSW_NPV | PSW_DMP | PSW_IMP)) 661 | (FEPSW & ~(PSW_NPV | PSW_DMP | PSW_IMP)); 662 } 663 664 TRACE_ALU_RESULT1 (PSW); 665 TRACE_BRANCH_RESULT (nia); 666} 667 668 669// FETRAP 6700,bbbb!0,00001000000:I:::fetrap 671"fetrap" 672*v850e2 673*v850e2v3 674*v850e3v5 675{ 676 TRACE_ALU_INPUT0 (); 677 678 FEPC = PC + 2; 679 FEPSW = PSW; 680 ECR &= ~ECR_FECC; 681 ECR |= (0x30 + bit4) << 16; 682 FEIC = 0x30 + bit4; 683 PSW |= PSW_EP | PSW_ID | PSW_NP; 684 nia = 0x30; /* next PC */ 685 686 TRACE_ALU_RESULT1 (PSW); 687 TRACE_BRANCH_RESULT (nia); 688} 689 690 691// HALT 6920000011111100000 + 0000000100100000:X:::halt 693"halt" 694{ 695 COMPAT_2 (OP_12007E0 ()); 696} 697 698 699 700// HSH 701rrrrr,11111100000 + wwwww,01101000110:XII:::hsh 702*v850e2 703*v850e2v3 704*v850e3v5 705"hsh r<reg2>, r<reg3>" 706{ 707 unsigned32 value; 708 TRACE_ALU_INPUT1 (GR[reg2]); 709 710 value = 0xffff & GR[reg2]; 711 GR[reg3] = GR[reg2]; 712 713 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 714 715 if (value == 0) { PSW |= PSW_Z; PSW |= PSW_CY; } 716 if (value & 0x80000000) PSW |= PSW_S; 717 718 TRACE_ALU_RESULT1 (GR[reg3]); 719} 720 721 722// HSW 723rrrrr,11111100000 + wwwww,01101000100:XII:::hsw 724*v850e 725*v850e1 726*v850e2 727*v850e2v3 728*v850e3v5 729"hsw r<reg2>, r<reg3>" 730{ 731 unsigned32 value; 732 TRACE_ALU_INPUT1 (GR[reg2]); 733 734 value = GR[reg2]; 735 value >>= 16; 736 value |= (GR[reg2] << 16); 737 738 GR[reg3] = value; 739 740 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 741 742 if (value == 0) PSW |= PSW_Z; 743 if (value & 0x80000000) PSW |= PSW_S; 744 if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY; 745 746 TRACE_ALU_RESULT (GR[reg3]); 747} 748 749 750 751// JARL 752rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl 753"jarl <disp22>, r<reg2>" 754{ 755 GR[reg2] = nia; 756 nia = cia + disp22; 757 TRACE_BRANCH1 (GR[reg2]); 758} 759 76000000010111,RRRRR!0 + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::jarl32 761*v850e2 762*v850e2v3 763*v850e3v5 764"jarl <imm32>, r<reg1>" 765{ 766 GR[reg1] = nia; 767 nia = (cia + imm32) & ~1; 768 769 TRACE_BRANCH_RESULT (nia); 770} 771 772 77311000111111,RRRRR + wwwww!0,00101100000:XI:::jarl_reg 774*v850e3v5 775"jarl [r<reg1>], r<reg3>" 776{ 777 GR[reg3] = nia; 778 nia = GR[reg1]; 779 TRACE_BRANCH_RESULT (nia); 780} 781 782 783// JMP 78400000000011,RRRRR:I:::jmp 785"jmp [r<reg1>]" 786{ 787 nia = GR[reg1] & ~1; 788 TRACE_BRANCH0 (); 789} 790 79100000110111,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::jmp32 792*v850e2 793*v850e2v3 794*v850e3v5 795"jmp <imm32>[r<reg1>]" 796{ 797 nia = (GR[reg1] + imm32) & ~1; 798 799 TRACE_BRANCH_RESULT (nia); 800} 801 802 803// JR 8040000011110,dddddd + ddddddddddddddd,0:V:::jr 805"jr <disp22>" 806{ 807 nia = cia + disp22; 808 TRACE_BRANCH0 (); 809} 810 811 812// JR32 8130000001011100000 + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::jr32 814*v850e2 815*v850e2v3 816*v850e3v5 817"jr <imm32>" 818{ 819 nia = (cia + imm32) & ~1; 820 821 TRACE_BRANCH_RESULT (nia); 822} 823 824 825// LD 826rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b 827"ld.b <disp16>[r<reg1>], r<reg2>" 828{ 829 COMPAT_2 (OP_700 ()); 830} 831 83200000111100,RRRRR+wwwww,ddddddd,0101+dddddddddddddddd:XIV:::ld.b 833"ld.b <disp23>[r<reg1>], r<reg3>" 834*v850e2v3 835*v850e3v5 836{ 837 unsigned32 addr = GR[reg1] + disp23; 838 unsigned32 result = EXTEND8 (load_data_mem (sd, addr, 1)); 839 GR[reg3] = result; 840 TRACE_LD (addr, result); 841} 842 843rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h 844"ld.h <disp16>[r<reg1>], r<reg2>" 845{ 846 COMPAT_2 (OP_720 ()); 847} 848 84900000111100,RRRRR+wwwww,dddddd,00111+dddddddddddddddd:XIV:::ld.h 850*v850e2v3 851*v850e3v5 852"ld.h <disp23>[r<reg1>], r<reg3>" 853{ 854 unsigned32 addr = GR[reg1] + disp23; 855 unsigned32 result = EXTEND16 (load_data_mem (sd, addr, 2)); 856 GR[reg3] = result; 857 TRACE_LD (addr, result); 858} 859 860rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w 861"ld.w <disp16>[r<reg1>], r<reg2>" 862{ 863 COMPAT_2 (OP_10720 ()); 864} 865 86600000111100,RRRRR+wwwww,dddddd,01001+dddddddddddddddd:XIV:::ld.w 867*v850e2v3 868*v850e3v5 869"ld.w <disp23>[r<reg1>], r<reg3>" 870{ 871 unsigned32 addr = GR[reg1] + disp23; 872 unsigned32 result = load_data_mem (sd, addr, 4); 873 GR[reg3] = result; 874 TRACE_LD (addr, result); 875} 876 87700000111101,RRRRR+wwwww,dddddd,01001+dddddddddddddddd:XIV:::ld.dw 878*v850e3v5 879"ld.dw <disp23>[r<reg1>], r<reg3>" 880{ 881 unsigned32 addr = GR[reg1] + disp23; 882 unsigned32 result = load_data_mem (sd, addr, 4); 883 GR[reg3] = result; 884 TRACE_LD (addr, result); 885 result = load_data_mem (sd, addr + 4, 4); 886 GR[reg3 + 1] = result; 887 TRACE_LD (addr + 4, result); 888} 889 890rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu 891*v850e 892*v850e1 893*v850e2 894*v850e2v3 895*v850e3v5 896"ld.bu <disp16>[r<reg1>], r<reg2>" 897{ 898 COMPAT_2 (OP_10780 ()); 899} 900 90100000111101,RRRRR+wwwww,ddddddd,0101+dddddddddddddddd:XIV:::ld.bu 902*v850e2v3 903*v850e3v5 904"ld.bu <disp23>[r<reg1>], r<reg3>" 905{ 906 unsigned32 addr = GR[reg1] + disp23; 907 unsigned32 result = load_data_mem (sd, addr, 1); 908 GR[reg3] = result; 909 TRACE_LD (addr, result); 910} 911 912rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu 913*v850e 914*v850e1 915*v850e2 916*v850e2v3 917*v850e3v5 918"ld.hu <disp16>[r<reg1>], r<reg2>" 919{ 920 COMPAT_2 (OP_107E0 ()); 921} 922 92300000111101,RRRRR+wwwww,dddddd,00111+dddddddddddddddd:XIV:::ld.hu 924*v850e2v3 925*v850e3v5 926"ld.hu <disp23>[r<reg1>], r<reg3>" 927{ 928 unsigned32 addr = GR[reg1] + disp23; 929 unsigned32 result = load_data_mem (sd, addr, 2); 930 GR[reg3] = result; 931 TRACE_LD (addr, result); 932} 933 934 935 936// LDSR 937regID,111111,RRRRR + selID,00000100000:IX:::ldsr 938"ldsr r<reg1>, s<regID>":(selID == 0) 939"ldsr r<reg1>, s<regID>, <selID>" 940{ 941 uint32 sreg = GR[reg1]; 942 TRACE_ALU_INPUT1 (GR[reg1]); 943 944 /* FIXME: For now we ignore the selID. */ 945 if ( (idecode_issue == idecode_v850e2_issue 946 || idecode_issue == idecode_v850e3v5_issue 947 || idecode_issue == idecode_v850e2v3_issue) 948 && regID < 28) 949 { 950 int protect_p = (PSW & PSW_NPV) ? 1 : 0; 951 952 953 switch (BSEL & 0xffff) 954 { 955 case 0x0000: 956 if ((PSW & PSW_NPV) 957 && ((regID >= 8 && regID <= 12) 958 || (regID >= 22 && regID <= 27) 959 || regID == PSW_REGNO)) 960 { 961 protect_p = 0; 962 } 963 break; 964 case 0x1000: /* MPU0 */ 965 break; 966 case 0x1001: /* MPU1 */ 967 break; 968 case 0x2000: /* FPU */ 969 if ((PSW & PSW_NPV) 970 && ((/* regID >= 0 && */ regID <= 5) 971 || regID == 8 972 || regID == 9 973 || regID == 10 974 || (regID >= 11 && regID <= 26))) 975 { 976 protect_p = 0; 977 } 978 break; 979 case 0xff00: 980 if ((PSW & PSW_NPV) 981 && (regID == 6 982 || regID == 7 983 || regID == 8 984 || regID == 9 985 || regID == 10 986 || (regID >= 11 && regID <= 15) 987 || regID == 18 988 || regID == 19 989 || (regID >= 21 && regID <= 27))) 990 { 991 protect_p = 0; 992 } 993 break; 994 case 0xffff: 995 if ((PSW & PSW_NPV) 996 && (regID == 6 997 || regID == 7 998 || regID == 8 999 || regID == 9 1000 || regID == 10 1001 || regID == 11 1002 || regID == 12 1003 || regID == 15 1004 || regID == 18 1005 || regID == 19 1006 || (regID >= 21 && regID <= 27))) 1007 { 1008 protect_p = 0; 1009 } 1010 break; 1011 } 1012 1013 if (!protect_p) 1014 { 1015 switch (BSEL & 0xffff) 1016 { 1017 case 0x0000: 1018 case 0xff00: /* user0 bank */ 1019 case 0xffff: /* user1 bank */ 1020 if(regID == PSW_REGNO) 1021 { 1022 SR[regID] = sreg & ((PSW & PSW_NPV) ? 0xf : ~0); 1023 } 1024 else 1025 { 1026 SR[regID] = sreg; 1027 } 1028 break; 1029 case 0x1000: 1030 MPU0_SR[regID] = sreg; 1031 break; 1032 case 0x1001: 1033 if (regID == MPC_REGNO) 1034 { 1035 PPC &= ~PPC_PPE; 1036 SPAL &= ~SPAL_SPE; 1037 IPA0L &= ~IPA_IPE; 1038 IPA1L &= ~IPA_IPE; 1039 IPA2L &= ~IPA_IPE; 1040 IPA3L &= ~IPA_IPE; 1041 DPA0L &= ~DPA_DPE; 1042 DPA1L &= ~DPA_DPE; 1043 DCC &= ~(DCC_DCE0 | DCC_DCE1); 1044 } 1045 else 1046 { 1047 MPU1_SR[regID] = sreg; 1048 } 1049 break; 1050 case 0x2000: /* FPU */ 1051 if (regID == FPST_REGNO) 1052 { 1053 unsigned int val = FPSR & ~(FPSR_PR | FPSR_XC | FPSR_XP); 1054 1055 val |= ((sreg & FPST_PR) ? FPSR_PR : 0) 1056 | ((sreg & FPST_XCE) ? FPSR_XCE : 0) 1057 | ((sreg & FPST_XCV) ? FPSR_XCV : 0) 1058 | ((sreg & FPST_XCZ) ? FPSR_XCZ : 0) 1059 | ((sreg & FPST_XCO) ? FPSR_XCO : 0) 1060 | ((sreg & FPST_XCU) ? FPSR_XCU : 0) 1061 | ((sreg & FPST_XCI) ? FPSR_XCI : 0) 1062 | ((sreg & FPST_XPV) ? FPSR_XPV : 0) 1063 | ((sreg & FPST_XPZ) ? FPSR_XPZ : 0) 1064 | ((sreg & FPST_XPO) ? FPSR_XPO : 0) 1065 | ((sreg & FPST_XPU) ? FPSR_XPU : 0) 1066 | ((sreg & FPST_XPI) ? FPSR_XPI : 0); 1067 FPSR = val; 1068 } 1069 else if (regID == FPCFG_REGNO) 1070 { 1071 unsigned int val = FPSR & ~(FPSR_RM | FPSR_XE); 1072 1073 val |= (((sreg & FPCFG_RM) >> 7) << 18) 1074 | ((sreg & FPCFG_XEV) ? FPSR_XEV : 0) 1075 | ((sreg & FPCFG_XEZ) ? FPSR_XEZ : 0) 1076 | ((sreg & FPCFG_XEO) ? FPSR_XEO : 0) 1077 | ((sreg & FPCFG_XEU) ? FPSR_XEU : 0) 1078 | ((sreg & FPCFG_XEI) ? FPSR_XEI : 0); 1079 FPSR = val; 1080 } 1081 1082 FPU_SR[regID] = sreg; 1083 break; 1084 } 1085 } 1086 } 1087 else 1088 { 1089 SR[regID] = sreg; 1090 } 1091 1092 TRACE_ALU_RESULT (sreg); 1093} 1094 1095 1096 1097// MAC 1098rrrrr,111111,RRRRR + wwww,0011110,mmmm,0:XI:::mac 1099*v850e2 1100*v850e2v3 1101*v850e3v5 1102"mac r<reg1>, r<reg2>, r<reg3e>, r<reg4e>" 1103{ 1104 unsigned long op0; 1105 unsigned long op1; 1106 unsigned long op2; 1107 unsigned long op2hi; 1108 unsigned long lo; 1109 unsigned long mid1; 1110 unsigned long mid2; 1111 unsigned long hi; 1112 unsigned long RdLo; 1113 unsigned long RdHi; 1114 int carry; 1115 bfd_boolean sign; 1116 1117 op0 = GR[reg1]; 1118 op1 = GR[reg2]; 1119 op2 = GR[reg3e]; 1120 op2hi = GR[reg3e+1]; 1121 1122 TRACE_ALU_INPUT4 (op0, op1, op2, op2hi); 1123 1124 sign = (op0 ^ op1) & 0x80000000; 1125 1126 if (((signed long) op0) < 0) 1127 op0 = - op0; 1128 1129 if (((signed long) op1) < 0) 1130 op1 = - op1; 1131 1132 /* We can split the 32x32 into four 16x16 operations. This ensures 1133 that we do not lose precision on 32bit only hosts: */ 1134 lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF)); 1135 mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF)); 1136 mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF)); 1137 hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF)); 1138 1139 /* We now need to add all of these results together, taking care 1140 to propogate the carries from the additions: */ 1141 RdLo = Add32 (lo, (mid1 << 16), & carry); 1142 RdHi = carry; 1143 RdLo = Add32 (RdLo, (mid2 << 16), & carry); 1144 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi); 1145 1146 if (sign) 1147 { 1148 RdLo = ~ RdLo; 1149 RdHi = ~ RdHi; 1150 if (RdLo == 0xFFFFFFFF) 1151 { 1152 RdLo = 0; 1153 RdHi += 1; 1154 } 1155 else 1156 RdLo += 1; 1157 } 1158 1159 RdLo = Add32 (RdLo, op2, & carry); 1160 RdHi += carry + op2hi; 1161 1162 /* Store the result and condition codes. */ 1163 GR[reg4e] = RdLo; 1164 GR[reg4e + 1 ] = RdHi; 1165 1166 TRACE_ALU_RESULT2 (RdLo, RdHi); 1167} 1168 1169 1170 1171// MACU 1172rrrrr,111111,RRRRR + wwww,0011111,mmmm,0:XI:::macu 1173*v850e2 1174*v850e2v3 1175*v850e3v5 1176"macu r<reg1>, r<reg2>, r<reg3e>, r<reg4e>" 1177{ 1178 unsigned long op0; 1179 unsigned long op1; 1180 unsigned long op2; 1181 unsigned long op2hi; 1182 unsigned long lo; 1183 unsigned long mid1; 1184 unsigned long mid2; 1185 unsigned long hi; 1186 unsigned long RdLo; 1187 unsigned long RdHi; 1188 int carry; 1189 1190 op0 = GR[reg1]; 1191 op1 = GR[reg2]; 1192 op2 = GR[reg3e]; 1193 op2hi = GR[reg3e + 1]; 1194 1195 TRACE_ALU_INPUT4 (op0, op1, op2, op2hi); 1196 1197 /* We can split the 32x32 into four 16x16 operations. This ensures 1198 that we do not lose precision on 32bit only hosts: */ 1199 lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF)); 1200 mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF)); 1201 mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF)); 1202 hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF)); 1203 1204 /* We now need to add all of these results together, taking care 1205 to propogate the carries from the additions: */ 1206 RdLo = Add32 (lo, (mid1 << 16), & carry); 1207 RdHi = carry; 1208 RdLo = Add32 (RdLo, (mid2 << 16), & carry); 1209 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi); 1210 1211 RdLo = Add32 (RdLo, op2, & carry); 1212 RdHi += carry + op2hi; 1213 1214 /* Store the result and condition codes. */ 1215 GR[reg4e] = RdLo; 1216 GR[reg4e+1] = RdHi; 1217 1218 TRACE_ALU_RESULT2 (RdLo, RdHi); 1219} 1220 1221 1222 1223// MOV 1224rrrrr!0,000000,RRRRR:I:::mov 1225"mov r<reg1>, r<reg2>" 1226{ 1227 TRACE_ALU_INPUT0 (); 1228 GR[reg2] = GR[reg1]; 1229 TRACE_ALU_RESULT (GR[reg2]); 1230} 1231 1232rrrrr!0,010000,iiiii:II:::mov 1233"mov <imm5>, r<reg2>" 1234{ 1235 COMPAT_1 (OP_200 ()); 1236} 1237 123800000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov 1239*v850e 1240*v850e1 1241*v850e2 1242*v850e2v3 1243*v850e3v5 1244"mov <imm32>, r<reg1>" 1245{ 1246 SAVE_2; 1247 trace_input ("mov", OP_IMM_REG, 4); 1248 State.regs[ OP[0] ] = load_mem (PC + 2, 4); 1249 trace_output (OP_IMM_REG); 1250} 1251 1252 1253 1254// MOVEA 1255rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea 1256"movea <simm16>, r<reg1>, r<reg2>" 1257{ 1258 TRACE_ALU_INPUT2 (GR[reg1], simm16); 1259 GR[reg2] = GR[reg1] + simm16; 1260 TRACE_ALU_RESULT (GR[reg2]); 1261} 1262 1263 1264 1265// MOVHI 1266rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi 1267"movhi <uimm16>, r<reg1>, r<reg2>" 1268{ 1269 COMPAT_2 (OP_640 ()); 1270} 1271 1272 1273 1274// MUL 1275rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul 1276*v850e 1277*v850e1 1278*v850e2 1279*v850e2v3 1280*v850e3v5 1281"mul r<reg1>, r<reg2>, r<reg3>" 1282{ 1283 COMPAT_2 (OP_22007E0 ()); 1284} 1285 1286rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul 1287*v850e 1288*v850e1 1289*v850e2 1290*v850e2v3 1291*v850e3v5 1292"mul <imm9>, r<reg2>, r<reg3>" 1293{ 1294 COMPAT_2 (OP_24007E0 ()); 1295} 1296 1297 1298// MULH 1299rrrrr!0,000111,RRRRR:I:::mulh 1300"mulh r<reg1>, r<reg2>" 1301{ 1302 COMPAT_1 (OP_E0 ()); 1303} 1304 1305rrrrr!0,010111,iiiii:II:::mulh 1306"mulh <imm5>, r<reg2>" 1307{ 1308 COMPAT_1 (OP_2E0 ()); 1309} 1310 1311 1312 1313// MULHI 1314rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi 1315"mulhi <uimm16>, r<reg1>, r<reg2>" 1316{ 1317 COMPAT_2 (OP_6E0 ()); 1318} 1319 1320 1321 1322// MULU 1323rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu 1324*v850e 1325*v850e1 1326*v850e2 1327*v850e2v3 1328*v850e3v5 1329"mulu r<reg1>, r<reg2>, r<reg3>" 1330{ 1331 COMPAT_2 (OP_22207E0 ()); 1332} 1333 1334rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu 1335*v850e 1336*v850e1 1337*v850e2 1338*v850e2v3 1339*v850e3v5 1340"mulu <imm9>, r<reg2>, r<reg3>" 1341{ 1342 COMPAT_2 (OP_24207E0 ()); 1343} 1344 1345 1346 1347// NOP 13480000000000000000:I:::nop 1349"nop" 1350{ 1351 /* do nothing, trace nothing */ 1352} 1353 1354 1355 1356// NOT 1357rrrrr,000001,RRRRR:I:::not 1358"not r<reg1>, r<reg2>" 1359{ 1360 COMPAT_1 (OP_20 ()); 1361} 1362 1363 1364 1365// NOT1 136601,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1 1367"not1 <bit3>, <disp16>[r<reg1>]" 1368{ 1369 COMPAT_2 (OP_47C0 ()); 1370} 1371 1372rrrrr,111111,RRRRR + 0000000011100010:IX:::not1 1373*v850e 1374*v850e1 1375*v850e2 1376*v850e2v3 1377*v850e3v5 1378"not1 r<reg2>, r<reg1>" 1379{ 1380 COMPAT_2 (OP_E207E0 ()); 1381} 1382 1383 1384 1385// OR 1386rrrrr,001000,RRRRR:I:::or 1387"or r<reg1>, r<reg2>" 1388{ 1389 COMPAT_1 (OP_100 ()); 1390} 1391 1392 1393 1394// ORI 1395rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori 1396"ori <uimm16>, r<reg1>, r<reg2>" 1397{ 1398 COMPAT_2 (OP_680 ()); 1399} 1400 1401 1402 1403// PREPARE 14040000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare 1405*v850e 1406*v850e1 1407*v850e2 1408*v850e2v3 1409*v850e3v5 1410"prepare <list12>, <imm5>" 1411{ 1412 int i; 1413 SAVE_2; 1414 1415 trace_input ("prepare", OP_PUSHPOP1, 0); 1416 1417 /* Store the registers with lower number registers being placed at 1418 higher addresses. */ 1419 for (i = 0; i < 12; i++) 1420 if ((OP[3] & (1 << type1_regs[ i ]))) 1421 { 1422 SP -= 4; 1423 store_mem (SP, 4, State.regs[ 20 + i ]); 1424 } 1425 1426 SP -= (OP[3] & 0x3e) << 1; 1427 1428 trace_output (OP_PUSHPOP1); 1429} 1430 1431 14320000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00 1433*v850e 1434*v850e1 1435*v850e2 1436*v850e2v3 1437*v850e3v5 1438"prepare <list12>, <imm5>, sp" 1439{ 1440 COMPAT_2 (OP_30780 ()); 1441} 1442 14430000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01 1444*v850e 1445*v850e1 1446*v850e2 1447*v850e2v3 1448*v850e3v5 1449"prepare <list12>, <imm5>, <uimm16>" 1450{ 1451 COMPAT_2 (OP_B0780 ()); 1452} 1453 14540000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10 1455*v850e 1456*v850e1 1457*v850e2 1458*v850e2v3 1459*v850e3v5 1460"prepare <list12>, <imm5>, <uimm16>" 1461{ 1462 COMPAT_2 (OP_130780 ()); 1463} 1464 14650000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11 1466*v850e 1467*v850e1 1468*v850e2 1469*v850e2v3 1470*v850e3v5 1471"prepare <list12>, <imm5>, <uimm32>" 1472{ 1473 COMPAT_2 (OP_1B0780 ()); 1474} 1475 1476 1477 1478// RETI 14790000011111100000 + 0000000101000000:X:::reti 1480"reti" 1481{ 1482 if ((PSW & PSW_EP)) 1483 { 1484 nia = (EIPC & ~1); 1485 PSW = EIPSW; 1486 } 1487 else if ((PSW & PSW_NP)) 1488 { 1489 nia = (FEPC & ~1); 1490 PSW = FEPSW; 1491 } 1492 else 1493 { 1494 nia = (EIPC & ~1); 1495 PSW = EIPSW; 1496 } 1497 TRACE_BRANCH1 (PSW); 1498} 1499 1500 1501 1502// SAR 1503rrrrr,111111,RRRRR + 0000000010100000:IX:::sar 1504"sar r<reg1>, r<reg2>" 1505{ 1506 COMPAT_2 (OP_A007E0 ()); 1507} 1508 1509rrrrr,010101,iiiii:II:::sar 1510"sar <imm5>, r<reg2>" 1511{ 1512 COMPAT_1 (OP_2A0 ()); 1513} 1514 1515rrrrr,111111,RRRRR + wwwww,00010100010:XI:::sar 1516*v850e2 1517*v850e2v3 1518*v850e3v5 1519"sar r<reg1>, r<reg2>, r<reg3>" 1520{ 1521 TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]); 1522 v850_sar(sd, GR[reg1], GR[reg2], &GR[reg3]); 1523 TRACE_ALU_RESULT1 (GR[reg3]); 1524} 1525 1526 1527// SASF 1528rrrrr,1111110,cccc + 0000001000000000:IX:::sasf 1529*v850e 1530*v850e1 1531*v850e2 1532*v850e2v3 1533*v850e3v5 1534"sasf %s<cccc>, r<reg2>" 1535{ 1536 COMPAT_2 (OP_20007E0 ()); 1537} 1538 1539 1540 1541// SATADD 1542rrrrr!0,000110,RRRRR:I:::satadd 1543"satadd r<reg1>, r<reg2>" 1544{ 1545 COMPAT_1 (OP_C0 ()); 1546} 1547 1548rrrrr!0,010001,iiiii:II:::satadd 1549"satadd <imm5>, r<reg2>" 1550{ 1551 COMPAT_1 (OP_220 ()); 1552} 1553 1554rrrrr,111111,RRRRR + wwwww,01110111010:XI:::satadd 1555*v850e2 1556*v850e2v3 1557*v850e3v5 1558"satadd r<reg1>, r<reg2>, r<reg3>" 1559{ 1560 TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]); 1561 v850_satadd (sd, GR[reg1], GR[reg2], &GR[reg3]); 1562 TRACE_ALU_RESULT1 (GR[reg3]); 1563} 1564 1565 1566 1567// SATSUB 1568rrrrr!0,000101,RRRRR:I:::satsub 1569"satsub r<reg1>, r<reg2>" 1570{ 1571 COMPAT_1 (OP_A0 ()); 1572} 1573 1574rrrrr,111111,RRRRR + wwwww,01110011010:XI:::satsub 1575*v850e2 1576*v850e2v3 1577*v850e3v5 1578"satsub r<reg1>, r<reg2>, r<reg3>" 1579{ 1580 TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]); 1581 v850_satsub (sd, GR[reg1], GR[reg2], &GR[reg3]); 1582 TRACE_ALU_RESULT1 (GR[reg3]); 1583} 1584 1585 1586 1587// SATSUBI 1588rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi 1589"satsubi <simm16>, r<reg1>, r<reg2>" 1590{ 1591 COMPAT_2 (OP_660 ()); 1592} 1593 1594 1595 1596// SATSUBR 1597rrrrr!0,000100,RRRRR:I:::satsubr 1598"satsubr r<reg1>, r<reg2>" 1599{ 1600 COMPAT_1 (OP_80 ()); 1601} 1602 1603 1604 1605//SBF 1606rrrrr,111111,RRRRR + wwwww,011100,cccc!13,0:XI:::sbf 1607*v850e2 1608*v850e2v3 1609*v850e3v5 1610"sbf %s<cccc>, r<reg1>, r<reg2>, r<reg3>" 1611{ 1612 int cond = condition_met (cccc); 1613 TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]); 1614 GR[reg3] = GR[reg2] - GR[reg1] - (cond ? 1 : 0); 1615 TRACE_ALU_RESULT1 (GR[reg3]); 1616} 1617 1618 1619 1620// SCH0L 1621rrrrr,11111100000 + wwwww,01101100100:IX:::sch0l 1622*v850e2 1623*v850e2v3 1624*v850e3v5 1625"sch0l r<reg2>, r<reg3>" 1626{ 1627 unsigned int pos, op0; 1628 1629 TRACE_ALU_INPUT1 (GR[reg2]); 1630 1631 op0 = GR[reg2]; 1632 1633 if (op0 == 0xffffffff) 1634 { 1635 PSW &= ~PSW_CY; 1636 PSW &= ~PSW_OV; 1637 PSW &= ~PSW_S; 1638 PSW |= PSW_Z; 1639 pos = 0; 1640 } 1641 else if (op0 == 0xfffffffe) 1642 { 1643 PSW |= PSW_CY; 1644 PSW &= ~PSW_OV; 1645 PSW &= ~PSW_S; 1646 PSW &= ~PSW_Z; 1647 pos = 32; 1648 } 1649 else 1650 { 1651 pos = 1; 1652 while (op0 & 0x80000000) 1653 { 1654 op0 <<= 1; 1655 pos++; 1656 } 1657 PSW &= ~PSW_CY; 1658 PSW &= ~PSW_OV; 1659 PSW &= ~PSW_S; 1660 PSW &= ~PSW_Z; 1661 } 1662 1663 GR[reg3] = pos; 1664 1665 TRACE_ALU_RESULT1 (GR[reg3]); 1666} 1667 1668 1669 1670// SCH0R 1671rrrrr,11111100000 + wwwww,01101100000:IX:::sch0r 1672*v850e2 1673*v850e2v3 1674*v850e3v5 1675"sch0r r<reg2>, r<reg3>" 1676{ 1677 unsigned int pos, op0; 1678 1679 TRACE_ALU_INPUT1 (GR[reg2]); 1680 1681 op0 = GR[reg2]; 1682 1683 if (op0 == 0xffffffff) 1684 { 1685 PSW &= ~PSW_CY; 1686 PSW &= ~PSW_OV; 1687 PSW &= ~PSW_S; 1688 PSW |= PSW_Z; 1689 pos = 0; 1690 } 1691 else if (op0 == 0x7fffffff) 1692 { 1693 PSW |= PSW_CY; 1694 PSW &= ~PSW_OV; 1695 PSW &= ~PSW_S; 1696 PSW &= ~PSW_Z; 1697 pos = 32; 1698 } 1699 else 1700 { 1701 pos = 1; 1702 while (op0 & 0x00000001) 1703 { 1704 op0 >>= 1; 1705 pos++; 1706 } 1707 PSW &= ~PSW_CY; 1708 PSW &= ~PSW_OV; 1709 PSW &= ~PSW_S; 1710 PSW &= ~PSW_Z; 1711 } 1712 1713 GR[reg3] = pos; 1714 1715 TRACE_ALU_RESULT1 (GR[reg3]); 1716} 1717 1718// SCH1L 1719rrrrr,11111100000 + wwwww,01101100110:IX:::sch1l 1720*v850e2 1721*v850e2v3 1722*v850e3v5 1723"sch1l r<reg2>, r<reg3>" 1724{ 1725 unsigned int pos, op0; 1726 1727 TRACE_ALU_INPUT1 (GR[reg2]); 1728 1729 op0 = GR[reg2]; 1730 1731 if (op0 == 0x00000000) 1732 { 1733 PSW &= ~PSW_CY; 1734 PSW &= ~PSW_OV; 1735 PSW &= ~PSW_S; 1736 PSW |= PSW_Z; 1737 pos = 0; 1738 } 1739 else if (op0 == 0x00000001) 1740 { 1741 PSW |= PSW_CY; 1742 PSW &= ~PSW_OV; 1743 PSW &= ~PSW_S; 1744 PSW &= ~PSW_Z; 1745 pos = 32; 1746 } 1747 else 1748 { 1749 pos = 1; 1750 while (!(op0 & 0x80000000)) 1751 { 1752 op0 <<= 1; 1753 pos++; 1754 } 1755 PSW &= ~PSW_CY; 1756 PSW &= ~PSW_OV; 1757 PSW &= ~PSW_S; 1758 PSW &= ~PSW_Z; 1759 } 1760 1761 GR[reg3] = pos; 1762 1763 TRACE_ALU_RESULT1 (GR[reg3]); 1764} 1765 1766// SCH1R 1767rrrrr,11111100000 + wwwww,01101100010:IX:::sch1r 1768*v850e2 1769*v850e2v3 1770*v850e3v5 1771"sch1r r<reg2>, r<reg3>" 1772{ 1773 unsigned int pos, op0; 1774 1775 TRACE_ALU_INPUT1 (GR[reg2]); 1776 1777 op0 = GR[reg2]; 1778 1779 if (op0 == 0x00000000) 1780 { 1781 PSW &= ~PSW_CY; 1782 PSW &= ~PSW_OV; 1783 PSW &= ~PSW_S; 1784 PSW |= PSW_Z; 1785 pos = 0; 1786 } 1787 else if (op0 == 0x80000000) 1788 { 1789 PSW |= PSW_CY; 1790 PSW &= ~PSW_OV; 1791 PSW &= ~PSW_S; 1792 PSW &= ~PSW_Z; 1793 pos = 32; 1794 } 1795 else 1796 { 1797 pos = 1; 1798 while (!(op0 & 0x00000001)) 1799 { 1800 op0 >>= 1; 1801 pos++; 1802 } 1803 PSW &= ~PSW_CY; 1804 PSW &= ~PSW_OV; 1805 PSW &= ~PSW_S; 1806 PSW &= ~PSW_Z; 1807 } 1808 1809 GR[reg3] = pos; 1810 1811 TRACE_ALU_RESULT1 (GR[reg3]); 1812} 1813 1814//SHL 1815rrrrr,111111,RRRRR + wwwww,00011000010:XI:::shl 1816*v850e2 1817*v850e2v3 1818*v850e3v5 1819"shl r<reg1>, r<reg2>, r<reg3>" 1820{ 1821 TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]); 1822 v850_shl(sd, GR[reg1], GR[reg2], &GR[reg3]); 1823 TRACE_ALU_RESULT1 (GR[reg3]); 1824} 1825 1826//SHR 1827rrrrr,111111,RRRRR + wwwww,00010000010:XI:::shr 1828*v850e2 1829*v850e2v3 1830*v850e3v5 1831"shr r<reg1>, r<reg2>, r<reg3>" 1832{ 1833 TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]); 1834 v850_shr(sd, GR[reg1], GR[reg2], &GR[reg3]); 1835 TRACE_ALU_RESULT1 (GR[reg3]); 1836} 1837 1838 1839 1840// SETF 1841rrrrr,1111110,cccc + 0000000000000000:IX:::setf 1842"setf %s<cccc>, r<reg2>" 1843{ 1844 COMPAT_2 (OP_7E0 ()); 1845} 1846 1847 1848 1849// SET1 185000,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1 1851"set1 <bit3>, <disp16>[r<reg1>]" 1852{ 1853 COMPAT_2 (OP_7C0 ()); 1854} 1855 1856rrrrr,111111,RRRRR + 0000000011100000:IX:::set1 1857*v850e 1858*v850e1 1859*v850e2 1860*v850e2v3 1861*v850e3v5 1862"set1 r<reg2>, [r<reg1>]" 1863{ 1864 COMPAT_2 (OP_E007E0 ()); 1865} 1866 1867 1868 1869// SHL 1870rrrrr,111111,RRRRR + 0000000011000000:IX:::shl 1871"shl r<reg1>, r<reg2>" 1872{ 1873 COMPAT_2 (OP_C007E0 ()); 1874} 1875 1876rrrrr,010110,iiiii:II:::shl 1877"shl <imm5>, r<reg2>" 1878{ 1879 COMPAT_1 (OP_2C0 ()); 1880} 1881 1882 1883 1884// SHR 1885rrrrr,111111,RRRRR + 0000000010000000:IX:::shr 1886"shr r<reg1>, r<reg2>" 1887{ 1888 COMPAT_2 (OP_8007E0 ()); 1889} 1890 1891rrrrr,010100,iiiii:II:::shr 1892"shr <imm5>, r<reg2>" 1893{ 1894 COMPAT_1 (OP_280 ()); 1895} 1896 1897 1898 1899// SLD 1900rrrrr,0110,ddddddd:IV:::sld.b 1901"sld.bu <disp7>[ep], r<reg2>":(PSW & PSW_US) 1902"sld.b <disp7>[ep], r<reg2>" 1903{ 1904 unsigned32 addr = EP + disp7; 1905 unsigned32 result = load_mem (addr, 1); 1906 if (PSW & PSW_US) 1907 { 1908 GR[reg2] = result; 1909 TRACE_LD_NAME ("sld.bu", addr, result); 1910 } 1911 else 1912 { 1913 result = EXTEND8 (result); 1914 GR[reg2] = result; 1915 TRACE_LD (addr, result); 1916 } 1917} 1918 1919rrrrr,1000,ddddddd:IV:::sld.h 1920"sld.hu <disp8>[ep], r<reg2>":(PSW & PSW_US) 1921"sld.h <disp8>[ep], r<reg2>" 1922{ 1923 unsigned32 addr = EP + disp8; 1924 unsigned32 result = load_mem (addr, 2); 1925 if (PSW & PSW_US) 1926 { 1927 GR[reg2] = result; 1928 TRACE_LD_NAME ("sld.hu", addr, result); 1929 } 1930 else 1931 { 1932 result = EXTEND16 (result); 1933 GR[reg2] = result; 1934 TRACE_LD (addr, result); 1935 } 1936} 1937 1938rrrrr,1010,dddddd,0:IV:::sld.w 1939"sld.w <disp8>[ep], r<reg2>" 1940{ 1941 unsigned32 addr = EP + disp8; 1942 unsigned32 result = load_mem (addr, 4); 1943 GR[reg2] = result; 1944 TRACE_LD (addr, result); 1945} 1946 1947rrrrr!0,0000110,dddd:IV:::sld.bu 1948*v850e 1949*v850e1 1950*v850e2 1951*v850e2v3 1952*v850e3v5 1953"sld.b <disp4>[ep], r<reg2>":(PSW & PSW_US) 1954"sld.bu <disp4>[ep], r<reg2>" 1955{ 1956 unsigned32 addr = EP + disp4; 1957 unsigned32 result = load_mem (addr, 1); 1958 if (PSW & PSW_US) 1959 { 1960 result = EXTEND8 (result); 1961 GR[reg2] = result; 1962 TRACE_LD_NAME ("sld.b", addr, result); 1963 } 1964 else 1965 { 1966 GR[reg2] = result; 1967 TRACE_LD (addr, result); 1968 } 1969} 1970 1971rrrrr!0,0000111,dddd:IV:::sld.hu 1972*v850e 1973*v850e1 1974*v850e2 1975*v850e2v3 1976*v850e3v5 1977"sld.h <disp5>[ep], r<reg2>":(PSW & PSW_US) 1978"sld.hu <disp5>[ep], r<reg2>" 1979{ 1980 unsigned32 addr = EP + disp5; 1981 unsigned32 result = load_mem (addr, 2); 1982 if (PSW & PSW_US) 1983 { 1984 result = EXTEND16 (result); 1985 GR[reg2] = result; 1986 TRACE_LD_NAME ("sld.h", addr, result); 1987 } 1988 else 1989 { 1990 GR[reg2] = result; 1991 TRACE_LD (addr, result); 1992 } 1993} 1994 1995 1996 1997// SST 1998rrrrr,0111,ddddddd:IV:::sst.b 1999"sst.b r<reg2>, <disp7>[ep]" 2000{ 2001 COMPAT_1 (OP_380 ()); 2002} 2003 2004rrrrr,1001,ddddddd:IV:::sst.h 2005"sst.h r<reg2>, <disp8>[ep]" 2006{ 2007 COMPAT_1 (OP_480 ()); 2008} 2009 2010rrrrr,1010,dddddd,1:IV:::sst.w 2011"sst.w r<reg2>, <disp8>[ep]" 2012{ 2013 COMPAT_1 (OP_501 ()); 2014} 2015 2016// ST 2017rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b 2018"st.b r<reg2>, <disp16>[r<reg1>]" 2019{ 2020 COMPAT_2 (OP_740 ()); 2021} 2022 202300000111100,RRRRR + wwwww,ddddddd,1101 + dddddddddddddddd:XIV:::st.b 2024*v850e2v3 2025*v850e3v5 2026"st.b r<reg3>, <disp23>[r<reg1>]" 2027{ 2028 unsigned32 addr = GR[reg1] + disp23; 2029 store_data_mem (sd, addr, 1, GR[reg3]); 2030 TRACE_ST (addr, GR[reg3]); 2031} 2032 2033rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h 2034"st.h r<reg2>, <disp16>[r<reg1>]" 2035{ 2036 COMPAT_2 (OP_760 ()); 2037} 2038 203900000111101,RRRRR+wwwww,dddddd,01101+dddddddddddddddd:XIV:::st.h 2040*v850e2v3 2041*v850e3v5 2042"st.h r<reg3>, <disp23>[r<reg1>]" 2043{ 2044 unsigned32 addr = GR[reg1] + disp23; 2045 store_data_mem (sd, addr, 2, GR[reg3]); 2046 TRACE_ST (addr, GR[reg3]); 2047} 2048 2049rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w 2050"st.w r<reg2>, <disp16>[r<reg1>]" 2051{ 2052 COMPAT_2 (OP_10760 ()); 2053} 2054 205500000111100,RRRRR+wwwww,dddddd,01111+dddddddddddddddd:XIV:::st.w 2056*v850e2v3 2057*v850e3v5 2058"st.w r<reg3>, <disp23>[r<reg1>]" 2059{ 2060 unsigned32 addr = GR[reg1] + disp23; 2061 store_data_mem (sd, addr, 4, GR[reg3]); 2062 TRACE_ST (addr, GR[reg3]); 2063} 2064 206500000111101,RRRRR+wwwww,dddddd,01111+dddddddddddddddd:XIV:::st.dw 2066*v850e3v5 2067"st.dw r<reg3>, <disp23>[r<reg1>]" 2068{ 2069 unsigned32 addr = GR[reg1] + disp23; 2070 store_data_mem (sd, addr, 4, GR[reg3]); 2071 TRACE_ST (addr, GR[reg3]); 2072 store_data_mem (sd, addr + 4, 4, GR[reg3 + 1]); 2073 TRACE_ST (addr + 4, GR[reg3 + 1]); 2074} 2075 2076 2077// STSR 2078rrrrr,111111,regID + 0000000001000000:IX:::stsr 2079"stsr s<regID>, r<reg2>" 2080{ 2081 uint32 sreg = 0; 2082 2083 if ((idecode_issue == idecode_v850e2_issue 2084 || idecode_issue == idecode_v850e3v5_issue 2085 || idecode_issue == idecode_v850e2v3_issue) 2086 && regID < 28) 2087 { 2088 switch (BSEL & 0xffff) 2089 { 2090 case 0x0000: 2091 case 0xff00: /* USER 0 */ 2092 case 0xffff: /* USER 1 */ 2093 sreg = SR[regID]; 2094 break; 2095 case 0x1000: 2096 sreg = MPU0_SR[regID]; 2097 break; 2098 case 0x1001: 2099 sreg = MPU1_SR[regID]; 2100 break; 2101 case 0x2000: 2102 if (regID == FPST_REGNO) 2103 { 2104 sreg = ((FPSR & FPSR_PR) ? FPST_PR : 0) 2105 | ((FPSR & FPSR_XCE) ? FPST_XCE : 0) 2106 | ((FPSR & FPSR_XCV) ? FPST_XCV : 0) 2107 | ((FPSR & FPSR_XCZ) ? FPST_XCZ : 0) 2108 | ((FPSR & FPSR_XCO) ? FPST_XCO : 0) 2109 | ((FPSR & FPSR_XCU) ? FPST_XCU : 0) 2110 | ((FPSR & FPSR_XCI) ? FPST_XCI : 0) 2111 | ((FPSR & FPSR_XPV) ? FPST_XPV : 0) 2112 | ((FPSR & FPSR_XPZ) ? FPST_XPZ : 0) 2113 | ((FPSR & FPSR_XPO) ? FPST_XPO : 0) 2114 | ((FPSR & FPSR_XPU) ? FPST_XPU : 0) 2115 | ((FPSR & FPSR_XPI) ? FPST_XPI : 0); 2116 } 2117 else if (regID == FPCFG_REGNO) 2118 { 2119 sreg = (((FPSR & FPSR_RM) >> 18) << 7) 2120 | ((FPSR & FPSR_XEV) ? FPCFG_XEV : 0) 2121 | ((FPSR & FPSR_XEZ) ? FPCFG_XEZ : 0) 2122 | ((FPSR & FPSR_XEO) ? FPCFG_XEO : 0) 2123 | ((FPSR & FPSR_XEU) ? FPCFG_XEU : 0) 2124 | ((FPSR & FPSR_XEI) ? FPCFG_XEI : 0); 2125 } 2126 else 2127 { 2128 sreg = FPU_SR[regID]; 2129 } 2130 break; 2131 } 2132 } 2133 else 2134 { 2135 sreg = SR[regID]; 2136 } 2137 2138 TRACE_ALU_INPUT1 (sreg); 2139 GR[reg2] = sreg; 2140 TRACE_ALU_RESULT (GR[reg2]); 2141} 2142 2143// SUB 2144rrrrr,001101,RRRRR:I:::sub 2145"sub r<reg1>, r<reg2>" 2146{ 2147 COMPAT_1 (OP_1A0 ()); 2148} 2149 2150// SUBR 2151rrrrr,001100,RRRRR:I:::subr 2152"subr r<reg1>, r<reg2>" 2153{ 2154 COMPAT_1 (OP_180 ()); 2155} 2156 2157// SWITCH 215800000000010,RRRRR:I:::switch 2159*v850e 2160*v850e1 2161*v850e2 2162*v850e2v3 2163*v850e3v5 2164"switch r<reg1>" 2165{ 2166 unsigned long adr; 2167 SAVE_1; 2168 trace_input ("switch", OP_REG, 0); 2169 adr = (cia + 2) + (State.regs[ reg1 ] << 1); 2170 nia = (cia + 2) + (EXTEND16 (load_mem (adr, 2)) << 1); 2171 trace_output (OP_REG); 2172} 2173 2174// SXB 217500000000101,RRRRR:I:::sxb 2176*v850e 2177*v850e1 2178*v850e2 2179*v850e2v3 2180*v850e3v5 2181"sxb r<reg1>" 2182{ 2183 TRACE_ALU_INPUT1 (GR[reg1]); 2184 GR[reg1] = EXTEND8 (GR[reg1]); 2185 TRACE_ALU_RESULT (GR[reg1]); 2186} 2187 2188// SXH 218900000000111,RRRRR:I:::sxh 2190*v850e 2191*v850e1 2192*v850e2 2193*v850e2v3 2194*v850e3v5 2195"sxh r<reg1>" 2196{ 2197 TRACE_ALU_INPUT1 (GR[reg1]); 2198 GR[reg1] = EXTEND16 (GR[reg1]); 2199 TRACE_ALU_RESULT (GR[reg1]); 2200} 2201 2202// TRAP 220300000111111,iiiii + 0000000100000000:X:::trap 2204"trap <vector>" 2205{ 2206 COMPAT_2 (OP_10007E0 ()); 2207} 2208 2209// TST 2210rrrrr,001011,RRRRR:I:::tst 2211"tst r<reg1>, r<reg2>" 2212{ 2213 COMPAT_1 (OP_160 ()); 2214} 2215 2216// TST1 221711,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1 2218"tst1 <bit3>, <disp16>[r<reg1>]" 2219{ 2220 COMPAT_2 (OP_C7C0 ()); 2221} 2222 2223rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1 2224*v850e 2225*v850e1 2226*v850e2 2227*v850e2v3 2228*v850e3v5 2229"tst1 r<reg2>, [r<reg1>]" 2230{ 2231 COMPAT_2 (OP_E607E0 ()); 2232} 2233 2234// XOR 2235rrrrr,001001,RRRRR:I:::xor 2236"xor r<reg1>, r<reg2>" 2237{ 2238 COMPAT_1 (OP_120 ()); 2239} 2240 2241// XORI 2242rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori 2243"xori <uimm16>, r<reg1>, r<reg2>" 2244{ 2245 COMPAT_2 (OP_6A0 ()); 2246} 2247 2248// ZXB 224900000000100,RRRRR:I:::zxb 2250*v850e 2251*v850e1 2252*v850e2 2253*v850e2v3 2254*v850e3v5 2255"zxb r<reg1>" 2256{ 2257 TRACE_ALU_INPUT1 (GR[reg1]); 2258 GR[reg1] = GR[reg1] & 0xff; 2259 TRACE_ALU_RESULT (GR[reg1]); 2260} 2261 2262// ZXH 226300000000110,RRRRR:I:::zxh 2264*v850e 2265*v850e1 2266*v850e2 2267*v850e2v3 2268*v850e3v5 2269"zxh r<reg1>" 2270{ 2271 TRACE_ALU_INPUT1 (GR[reg1]); 2272 GR[reg1] = GR[reg1] & 0xffff; 2273 TRACE_ALU_RESULT (GR[reg1]); 2274} 2275 2276// Right field must be zero so that it doesn't clash with DIVH 2277// Left field must be non-zero so that it doesn't clash with SWITCH 227811111,000010,00000:I:::break 2279*v850 2280*v850e 2281{ 2282 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP); 2283} 2284 228511111,000010,00000:I:::dbtrap 2286*v850e1 2287*v850e2 2288*v850e2v3 2289*v850e3v5 2290"dbtrap" 2291{ 2292 if (STATE_OPEN_KIND (SD) == SIM_OPEN_DEBUG) 2293 { 2294 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP); 2295 } 2296 else 2297 { 2298 DBPC = cia + 2; 2299 DBPSW = PSW; 2300 PSW = PSW | (PSW_NP | PSW_EP | PSW_ID); 2301 PC = 0x00000060; 2302 nia = 0x00000060; 2303 TRACE_BRANCH0 (); 2304 } 2305} 2306 2307// New breakpoint: 0x7E0 0x7E0 230800000,111111,00000 + 00000,11111,100000:X:::ilgop 2309{ 2310 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP); 2311} 2312 2313// Return from debug trap: 0x146007e0 23140000011111100000 + 0000000101000110:X:::dbret 2315*v850e1 2316*v850e2 2317*v850e2v3 2318*v850e3v5 2319"dbret" 2320{ 2321 nia = DBPC; 2322 PSW = DBPSW; 2323 TRACE_BRANCH1 (PSW); 2324} 2325 2326 2327// 2328// FLOAT 2329// 2330 2331// Map condition code to a string 2332:%s::::FFFF:int FFFF 2333{ 2334 switch (FFFF) 2335 { 2336 case 0: return "f"; 2337 case 1: return "un"; 2338 case 2: return "eq"; 2339 case 3: return "ueq"; 2340 case 4: return "olt"; 2341 case 5: return "ult"; 2342 case 6: return "ole"; 2343 case 7: return "ule"; 2344 case 8: return "sf"; 2345 case 9: return "ngle"; 2346 case 10: return "seq"; 2347 case 11: return "ngl"; 2348 case 12: return "lt"; 2349 case 13: return "nge"; 2350 case 14: return "le"; 2351 case 15: return "ngt"; 2352 } 2353 return "(null)"; 2354} 2355 2356// ABSF.D 2357rrrr,011111100000 + wwww,010001011000:F_I:::absf_d 2358*v850e2v3 2359*v850e3v5 2360"absf.d r<reg2e>, r<reg3e>" 2361{ 2362 sim_fpu ans, wop; 2363 sim_fpu_status status; 2364 2365 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); 2366 TRACE_FP_INPUT_FPU1 (&wop); 2367 2368 status = sim_fpu_abs (&ans, &wop); 2369 check_invalid_snan(sd, status, 1); 2370 2371 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); 2372 2373 TRACE_FP_RESULT_FPU1 (&ans); 2374} 2375 2376// ABSF.S 2377rrrrr,11111100000 + wwwww,10001001000:F_I:::absf_s 2378*v850e2v3 2379*v850e3v5 2380"absf.s r<reg2>, r<reg3>" 2381{ 2382 sim_fpu ans, wop; 2383 sim_fpu_status status; 2384 2385 sim_fpu_32to (&wop, GR[reg2]); 2386 TRACE_FP_INPUT_FPU1 (&wop); 2387 2388 status = sim_fpu_abs (&ans, &wop); 2389 check_invalid_snan(sd, status, 0); 2390 2391 sim_fpu_to32 (&GR[reg3], &ans); 2392 TRACE_FP_RESULT_FPU1 (&ans); 2393} 2394 2395// ADDF.D 2396rrrr,0111111,RRRR,0 + wwww,010001110000:F_I:::addf_d 2397*v850e2v3 2398*v850e3v5 2399"addf.d r<reg1e>, r<reg2e>, r<reg3e>" 2400{ 2401 sim_fpu ans, wop1, wop2; 2402 sim_fpu_status status; 2403 2404 sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]); 2405 sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]); 2406 TRACE_FP_INPUT_FPU2 (&wop1, &wop2); 2407 2408 status = sim_fpu_add (&ans, &wop1, &wop2); 2409 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); 2410 2411 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1); 2412 2413 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); 2414 TRACE_FP_RESULT_FPU1 (&ans); 2415} 2416 2417// ADDF.S 2418rrrrr,111111,RRRRR + wwwww,10001100000:F_I:::addf_s 2419*v850e2v3 2420*v850e3v5 2421"addf.s r<reg1>, r<reg2>, r<reg3>" 2422{ 2423 sim_fpu ans, wop1, wop2; 2424 sim_fpu_status status; 2425 2426 sim_fpu_32to (&wop1, GR[reg1]); 2427 sim_fpu_32to (&wop2, GR[reg2]); 2428 TRACE_FP_INPUT_FPU2 (&wop1, &wop2); 2429 2430 status = sim_fpu_add (&ans, &wop1, &wop2); 2431 status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); 2432 2433 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); 2434 2435 sim_fpu_to32 (&GR[reg3], &ans); 2436 TRACE_FP_RESULT_FPU1 (&ans); 2437} 2438 2439// CMOVF.D 2440rrrr,0111111,RRRR,0 + wwww!0,01000001,bbb,0:F_I:::cmovf_d 2441*v850e2v3 2442*v850e3v5 2443"cmovf.d <bbb>, r<reg1e>, r<reg2e>, r<reg3e>" 2444{ 2445 unsigned int ophi,oplow; 2446 sim_fpu ans, wop1, wop2; 2447 2448 sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]); 2449 sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]); 2450 TRACE_FP_INPUT_BOOL1_FPU2 (TEST_FPCC(bbb), &wop1, &wop2); 2451 2452 if (TEST_FPCC(bbb)) 2453 { 2454 ophi = GR[reg1e+1]; 2455 oplow = GR[reg1e]; 2456 ans = wop1; 2457 } 2458 else 2459 { 2460 ophi = GR[reg2e+1]; 2461 oplow = GR[reg2e]; 2462 ans = wop2; 2463 } 2464 2465 GR[reg3e+1] = ophi; 2466 GR[reg3e] = oplow; 2467 TRACE_FP_RESULT_FPU1 (&ans);; 2468} 2469 2470// CMOVF.S 2471rrrrr,111111,RRRRR!0 + wwwww!0,1000000,bbb,0:F_I:::cmovf_s 2472*v850e2v3 2473*v850e3v5 2474"cmovf.d <bbb>, r<reg1>, r<reg2>, r<reg3>" 2475{ 2476 unsigned int op; 2477 sim_fpu ans, wop1, wop2; 2478 2479 sim_fpu_32to (&wop1, GR[reg1]); 2480 sim_fpu_32to (&wop2, GR[reg2]); 2481 TRACE_FP_INPUT_BOOL1_FPU2 (TEST_FPCC(bbb), &wop1, &wop2); 2482 2483 if (TEST_FPCC(bbb)) 2484 { 2485 op = GR[reg1]; 2486 ans = wop1; 2487 } 2488 else 2489 { 2490 op = GR[reg2]; 2491 ans = wop2; 2492 } 2493 2494 GR[reg3] = op; 2495 TRACE_FP_RESULT_FPU1 (&ans); 2496} 2497 2498// CMPF.D 2499rrrr,0111111,RRRR,0 + 0,FFFF,1000011,bbb,0:F_I:::cmpf_d 2500*v850e2v3 2501*v850e3v5 2502"cmpf.d %s<FFFF>, r<reg2e>, r<reg1e>":(bbb == 0) 2503"cmpf.d %s<FFFF>, r<reg2e>, r<reg1e>, <bbb>" 2504{ 2505 int result; 2506 sim_fpu wop1; 2507 sim_fpu wop2; 2508 2509 sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]); 2510 sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]); 2511 TRACE_FP_INPUT_FPU2 (&wop2, &wop1); 2512 2513 result = v850_float_compare(sd, FFFF, wop2, wop1, 1); 2514 2515 if (result) 2516 SET_FPCC(bbb); 2517 else 2518 CLEAR_FPCC(bbb); 2519 2520 TRACE_FP_RESULT_BOOL (result); 2521} 2522 2523// CMPF.S 2524rrrrr,111111,RRRRR + 0,FFFF,1000010,bbb,0:F_I:::cmpf_s 2525*v850e2v3 2526*v850e3v5 2527"cmpf.s %s<FFFF>, r<reg2>, r<reg1>":(bbb == 0) 2528"cmpf.s %s<FFFF>, r<reg2>, r<reg1>, <bbb>" 2529{ 2530 int result; 2531 sim_fpu wop1; 2532 sim_fpu wop2; 2533 2534 sim_fpu_32to( &wop1, GR[reg1] ); 2535 sim_fpu_32to( &wop2, GR[reg2] ); 2536 TRACE_FP_INPUT_FPU2 (&wop2, &wop1); 2537 2538 result = v850_float_compare(sd, FFFF, wop2, wop1, 0); 2539 2540 if (result) 2541 SET_FPCC(bbb); 2542 else 2543 CLEAR_FPCC(bbb); 2544 2545 TRACE_FP_RESULT_BOOL (result); 2546} 2547 2548// CVTF.DL 2549rrrr,011111100100 + wwww,010001010100:F_I:::cvtf_dl 2550*v850e2v3 2551*v850e3v5 2552"cvtf.dl r<reg2e>, r<reg3e>" 2553{ 2554 unsigned64 ans; 2555 sim_fpu wop; 2556 sim_fpu_status status; 2557 2558 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); 2559 TRACE_FP_INPUT_FPU1 (&wop); 2560 2561 status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero); 2562 status |= sim_fpu_to64i (&ans, &wop, FPSR_GET_ROUND()); 2563 2564 check_cvt_fi(sd, status, 1); 2565 2566 GR[reg3e] = ans; 2567 GR[reg3e+1] = ans>>32L; 2568 TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]); 2569} 2570 2571// CVTF.DS 2572rrrr,011111100011 + wwwww,10001010010:F_I:::cvtf_ds 2573*v850e2v3 2574*v850e3v5 2575"cvtf.ds r<reg2e>, r<reg3>" 2576{ 2577 sim_fpu wop; 2578 sim_fpu_status status; 2579 2580 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); 2581 TRACE_FP_INPUT_FPU1 (&wop); 2582 2583 status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); 2584 2585 check_cvt_fi(sd, status, 0); 2586 2587 sim_fpu_to32 (&GR[reg3], &wop); 2588 TRACE_FP_RESULT_FPU1 (&wop); 2589} 2590 2591// CVTF.DW 2592rrrr,011111100100 + wwwww,10001010000:F_I:::cvtf_dw 2593*v850e2v3 2594*v850e3v5 2595"cvtf.dw r<reg2e>, r<reg3>" 2596{ 2597 uint32 ans; 2598 sim_fpu wop; 2599 sim_fpu_status status; 2600 2601 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); 2602 TRACE_FP_INPUT_FPU1 (&wop); 2603 2604 status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero); 2605 status |= sim_fpu_to32i (&ans, &wop, FPSR_GET_ROUND()); 2606 2607 check_cvt_fi(sd, status, 1); 2608 2609 GR[reg3] = ans; 2610 TRACE_FP_RESULT_WORD1 (ans); 2611} 2612 2613// CVTF.LD 2614rrrr,011111100001 + wwww,010001010010:F_I:::cvtf_ld 2615*v850e2v3 2616*v850e3v5 2617"cvtf.ld r<reg2e>, r<reg3e>" 2618{ 2619 signed64 op; 2620 sim_fpu wop; 2621 sim_fpu_status status; 2622 2623 op = ((signed64)GR[reg2e+1] << 32L) | GR[reg2e]; 2624 TRACE_FP_INPUT_WORD2 (GR[reg2e], GR[reg2e+1]); 2625 2626 sim_fpu_i64to (&wop, op, FPSR_GET_ROUND()); 2627 status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero); 2628 2629 check_cvt_if(sd, status, 1); 2630 2631 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &wop); 2632 TRACE_FP_RESULT_FPU1 (&wop); 2633} 2634 2635// CVTF.LS 2636rrrr,011111100001 + wwwww,10001000010:F_I:::cvtf_ls 2637*v850e2v3 2638*v850e3v5 2639"cvtf.ls r<reg2e>, r<reg3>" 2640{ 2641 signed64 op; 2642 sim_fpu wop; 2643 sim_fpu_status status; 2644 2645 op = ((signed64)GR[reg2e+1] << 32L) | GR[reg2e]; 2646 TRACE_FP_INPUT_WORD2 (GR[reg2e], GR[reg2e+1]); 2647 2648 sim_fpu_i64to (&wop, op, FPSR_GET_ROUND()); 2649 status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero); 2650 2651 check_cvt_if(sd, status, 0); 2652 2653 sim_fpu_to32 (&GR[reg3], &wop); 2654 TRACE_FP_RESULT_FPU1 (&wop); 2655} 2656 2657// CVTF.SD 2658rrrrr,11111100010 + wwww,010001010010:F_I:::cvtf_sd 2659*v850e2v3 2660*v850e3v5 2661"cvtf.sd r<reg2>, r<reg3e>" 2662{ 2663 sim_fpu wop; 2664 sim_fpu_status status; 2665 2666 sim_fpu_32to (&wop, GR[reg2]); 2667 TRACE_FP_INPUT_FPU1 (&wop); 2668 status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); 2669 2670 check_cvt_ff(sd, status, 1); 2671 2672 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &wop); 2673 TRACE_FP_RESULT_FPU1 (&wop); 2674} 2675 2676// CVTF.SL 2677rrrrr,11111100100 + wwww,010001000100:F_I:::cvtf_sl 2678*v850e2v3 2679*v850e3v5 2680"cvtf.sl r<reg2>, r<reg3e>" 2681{ 2682 signed64 ans; 2683 sim_fpu wop; 2684 sim_fpu_status status; 2685 2686 sim_fpu_32to (&wop, GR[reg2]); 2687 TRACE_FP_INPUT_FPU1 (&wop); 2688 2689 status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero); 2690 status |= sim_fpu_to64i (&ans, &wop, FPSR_GET_ROUND()); 2691 2692 check_cvt_fi(sd, status, 0); 2693 2694 GR[reg3e] = ans; 2695 GR[reg3e+1] = ans >> 32L; 2696 TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]); 2697} 2698 2699// CVTF.SW 2700rrrrr,11111100100 + wwwww,10001000000:F_I:::cvtf_sw 2701*v850e2v3 2702*v850e3v5 2703"cvtf.sw r<reg2>, r<reg3>" 2704{ 2705 uint32 ans; 2706 sim_fpu wop; 2707 sim_fpu_status status; 2708 2709 sim_fpu_32to (&wop, GR[reg2]); 2710 TRACE_FP_INPUT_FPU1 (&wop); 2711 2712 status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero); 2713 status |= sim_fpu_to32i (&ans, &wop, sim_fpu_round_zero); 2714 2715 check_cvt_fi(sd, status, 0); 2716 2717 GR[reg3] = ans; 2718 TRACE_FP_RESULT_WORD1 (ans); 2719} 2720 2721// CVTF.WD 2722rrrrr,11111100000 + wwww,010001010010:F_I:::cvtf_wd 2723*v850e2v3 2724*v850e3v5 2725"cvtf.wd r<reg2>, r<reg3e>" 2726{ 2727 sim_fpu wop; 2728 sim_fpu_status status; 2729 2730 TRACE_FP_INPUT_WORD1 (GR[reg2]); 2731 sim_fpu_i32to (&wop, GR[reg2], FPSR_GET_ROUND()); 2732 status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero); 2733 2734 check_cvt_if(sd, status, 1); 2735 2736 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &wop); 2737 TRACE_FP_RESULT_FPU1 (&wop); 2738} 2739 2740// CVTF.WS 2741rrrrr,11111100000 + wwwww,10001000010:F_I:::cvtf_ws 2742*v850e2v3 2743*v850e3v5 2744"cvtf.ws r<reg2>, r<reg3>" 2745{ 2746 sim_fpu wop; 2747 sim_fpu_status status; 2748 2749 TRACE_FP_INPUT_WORD1 (GR[reg2]); 2750 sim_fpu_i32to (&wop, GR[reg2], FPSR_GET_ROUND()); 2751 status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero); 2752 2753 check_cvt_if(sd, status, 0); 2754 2755 sim_fpu_to32 (&GR[reg3], &wop); 2756 TRACE_FP_RESULT_FPU1 (&wop); 2757} 2758 2759// DIVF.D 2760rrrr,0111111,RRRR,0 + wwww,010001111110:F_I:::divf_d 2761*v850e2v3 2762*v850e3v5 2763"divf.d r<reg1e>, r<reg2e>, r<reg3e>" 2764{ 2765 sim_fpu ans, wop1, wop2; 2766 sim_fpu_status status; 2767 2768 sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]); 2769 sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]); 2770 TRACE_FP_INPUT_FPU2 (&wop1, &wop2); 2771 2772 status = sim_fpu_div (&ans, &wop2, &wop1); 2773 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); 2774 2775 update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1); 2776 2777 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); 2778 TRACE_FP_RESULT_FPU1 (&ans); 2779} 2780 2781// DIVF.S 2782rrrrr,111111,RRRRR + wwwww,10001101110:F_I:::divf_s 2783*v850e2v3 2784*v850e3v5 2785"divf.s r<reg1>, r<reg2>, r<reg3>" 2786{ 2787 sim_fpu ans, wop1, wop2; 2788 sim_fpu_status status; 2789 2790 sim_fpu_32to (&wop1, GR[reg1]); 2791 sim_fpu_32to (&wop2, GR[reg2]); 2792 TRACE_FP_INPUT_FPU2 (&wop1, &wop2); 2793 2794 status = sim_fpu_div (&ans, &wop2, &wop1); 2795 status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); 2796 2797 update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); 2798 2799 sim_fpu_to32 (&GR[reg3], &ans); 2800 TRACE_FP_RESULT_FPU1 (&ans); 2801} 2802 2803// MADDF.S 2804rrrrr,111111,RRRRR + wwwww,101,W,00,WWWW,0:F_I:::maddf_s 2805*v850e2v3 2806*v850e3v5 2807"maddf.s r<reg1>, r<reg2>, r<reg3>, r<reg4>" 2808{ 2809 sim_fpu ans, wop1, wop2, wop3; 2810 sim_fpu_status status; 2811 2812 sim_fpu_32to (&wop1, GR[reg1]); 2813 sim_fpu_32to (&wop2, GR[reg2]); 2814 sim_fpu_32to (&wop3, GR[reg3]); 2815 TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3); 2816 2817 status = sim_fpu_mul (&ans, &wop1, &wop2); 2818 wop1 = ans; 2819 status |= sim_fpu_add (&ans, &wop1, &wop3); 2820 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); 2821 2822 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); 2823 2824 sim_fpu_to32 (&GR[reg4], &ans); 2825 TRACE_FP_RESULT_FPU1 (&ans); 2826} 2827 2828// MAXF.D 2829rrrr,0111111,RRRR,0 + wwww,010001111000:F_I:::maxf_d 2830*v850e2v3 2831*v850e3v5 2832"maxf.d r<reg1e>, r<reg2e>, r<reg3e>" 2833{ 2834 sim_fpu ans, wop1, wop2; 2835 2836 sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]); 2837 sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]); 2838 TRACE_FP_INPUT_FPU2 (&wop1, &wop2); 2839 2840 if (sim_fpu_is_nan(&wop1) || sim_fpu_is_nan(&wop2)) 2841 { 2842 if (FPSR & FPSR_XEV) 2843 { 2844 SignalExceptionFPE(sd, 1); 2845 } 2846 else 2847 { 2848 ans = sim_fpu_qnan; 2849 } 2850 } 2851 else if (FPSR & FPSR_FS 2852 && ((sim_fpu_is_zero (&wop1) || sim_fpu_is_denorm (&wop1)) 2853 && (sim_fpu_is_zero (&wop2) || sim_fpu_is_denorm (&wop2)))) 2854 { 2855 ans = sim_fpu_zero; 2856 } 2857 else 2858 { 2859 sim_fpu_max (&ans, &wop1, &wop2); 2860 } 2861 2862 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); 2863 TRACE_FP_RESULT_FPU1 (&ans); 2864} 2865 2866// MAXF.S 2867rrrrr,111111,RRRRR + wwwww,10001101000:F_I:::maxf_s 2868*v850e2v3 2869*v850e3v5 2870"maxf.s r<reg1>, r<reg2>, r<reg3>" 2871{ 2872 sim_fpu ans, wop1, wop2; 2873 2874 sim_fpu_32to (&wop1, GR[reg1]); 2875 sim_fpu_32to (&wop2, GR[reg2]); 2876 TRACE_FP_INPUT_FPU2 (&wop1, &wop2); 2877 2878 if (sim_fpu_is_nan(&wop1) || sim_fpu_is_nan(&wop2)) 2879 { 2880 if (FPSR & FPSR_XEV) 2881 { 2882 SignalExceptionFPE(sd, 0); 2883 } 2884 else 2885 { 2886 ans = sim_fpu_qnan; 2887 } 2888 } 2889 else if ((FPSR & FPSR_FS) 2890 && ((sim_fpu_is_zero (&wop1) || sim_fpu_is_denorm (&wop1)) 2891 && (sim_fpu_is_zero (&wop2)|| sim_fpu_is_denorm (&wop2)))) 2892 { 2893 ans = sim_fpu_zero; 2894 } 2895 else 2896 { 2897 sim_fpu_max (&ans, &wop1, &wop2); 2898 } 2899 2900 sim_fpu_to32 (&GR[reg3], &ans); 2901 TRACE_FP_RESULT_FPU1 (&ans); 2902} 2903 2904// MINF.D 2905rrrr,0111111,RRRR,0 + wwww,010001111010:F_I:::minf_d 2906*v850e2v3 2907*v850e3v5 2908"minf.d r<reg1e>, r<reg2e>, r<reg3e>" 2909{ 2910 sim_fpu ans, wop1, wop2; 2911 2912 sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]); 2913 sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]); 2914 TRACE_FP_INPUT_FPU2 (&wop1, &wop2); 2915 2916 if (sim_fpu_is_nan(&wop1) || sim_fpu_is_nan(&wop2)) 2917 { 2918 if (FPSR & FPSR_XEV) 2919 { 2920 SignalExceptionFPE(sd, 1); 2921 } 2922 else 2923 { 2924 ans = sim_fpu_qnan; 2925 } 2926 } 2927 else if (FPSR & FPSR_FS 2928 && ((sim_fpu_is_zero (&wop1) || sim_fpu_is_denorm (&wop1)) 2929 && (sim_fpu_is_zero (&wop2) || sim_fpu_is_denorm (&wop2)))) 2930 { 2931 ans = sim_fpu_zero; 2932 } 2933 else 2934 { 2935 sim_fpu_min (&ans, &wop1, &wop2); 2936 } 2937 2938 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); 2939 TRACE_FP_RESULT_FPU1 (&ans); 2940} 2941 2942// MINF.S 2943rrrrr,111111,RRRRR + wwwww,10001101010:F_I:::minf_s 2944*v850e2v3 2945*v850e3v5 2946"minf.s r<reg1>, r<reg2>, r<reg3>" 2947{ 2948 sim_fpu ans, wop1, wop2; 2949 2950 sim_fpu_32to (&wop1, GR[reg1]); 2951 sim_fpu_32to (&wop2, GR[reg2]); 2952 TRACE_FP_INPUT_FPU2 (&wop1, &wop2); 2953 2954 if (sim_fpu_is_nan(&wop1) || sim_fpu_is_nan(&wop2)) 2955 { 2956 if (FPSR & FPSR_XEV) 2957 { 2958 SignalExceptionFPE(sd, 0); 2959 } 2960 else 2961 { 2962 ans = sim_fpu_qnan; 2963 } 2964 } 2965 else if (FPSR & FPSR_FS 2966 && ((sim_fpu_is_zero (&wop1) || sim_fpu_is_denorm (&wop1)) 2967 && (sim_fpu_is_zero (&wop2) || sim_fpu_is_denorm (&wop2)))) 2968 { 2969 ans = sim_fpu_zero; 2970 } 2971 else 2972 { 2973 sim_fpu_min (&ans, &wop1, &wop2); 2974 } 2975 2976 sim_fpu_to32 (&GR[reg3], &ans); 2977 TRACE_FP_RESULT_FPU1 (&ans); 2978} 2979 2980// MSUBF.S 2981rrrrr,111111,RRRRR + wwwww,101,W,01,WWWW,0:F_I:::msubf_s 2982*v850e2v3 2983*v850e3v5 2984"msubf.s r<reg1>, r<reg2>, r<reg3>, r<reg4>" 2985{ 2986 sim_fpu ans, wop1, wop2, wop3; 2987 sim_fpu_status status; 2988 2989 sim_fpu_32to (&wop1, GR[reg1]); 2990 sim_fpu_32to (&wop2, GR[reg2]); 2991 sim_fpu_32to (&wop3, GR[reg3]); 2992 TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3); 2993 2994 status = sim_fpu_mul (&ans, &wop1, &wop2); 2995 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); 2996 wop1 = ans; 2997 status |= sim_fpu_sub (&ans, &wop1, &wop3); 2998 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); 2999 3000 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); 3001 3002 sim_fpu_to32 (&GR[reg4], &ans); 3003 TRACE_FP_RESULT_FPU1 (&ans); 3004} 3005 3006// MULF.D 3007rrrr,0111111,RRRR,0 + wwww,010001110100:F_I:::mulf_d 3008*v850e2v3 3009*v850e3v5 3010"mulf.d r<reg1e>, r<reg2e>, r<reg3e>" 3011{ 3012 sim_fpu ans, wop1, wop2; 3013 sim_fpu_status status; 3014 3015 sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]); 3016 sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]); 3017 TRACE_FP_INPUT_FPU2 (&wop1, &wop2); 3018 3019 status = sim_fpu_mul (&ans, &wop1, &wop2); 3020 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); 3021 3022 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1); 3023 3024 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); 3025 TRACE_FP_RESULT_FPU1 (&ans); 3026} 3027 3028// MULF.S 3029rrrrr,111111,RRRRR + wwwww,10001100100:F_I:::mulf_s 3030*v850e2v3 3031*v850e3v5 3032"mulf.s r<reg1>, r<reg2>, r<reg3>" 3033{ 3034 sim_fpu ans, wop1, wop2; 3035 sim_fpu_status status; 3036 3037 sim_fpu_32to (&wop1, GR[reg1]); 3038 sim_fpu_32to (&wop2, GR[reg2]); 3039 TRACE_FP_INPUT_FPU2 (&wop1, &wop2); 3040 3041 status = sim_fpu_mul (&ans, &wop1, &wop2); 3042 status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); 3043 3044 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); 3045 3046 sim_fpu_to32 (&GR[reg3], &ans); 3047 TRACE_FP_RESULT_FPU1 (&ans); 3048} 3049 3050// NEGF.D 3051rrrr,011111100001 + wwww,010001011000:F_I:::negf_d 3052*v850e2v3 3053*v850e3v5 3054"negf.d r<reg2e>, r<reg3e>" 3055{ 3056 sim_fpu ans, wop; 3057 sim_fpu_status status; 3058 3059 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); 3060 TRACE_FP_INPUT_FPU1 (&wop); 3061 3062 status = sim_fpu_neg (&ans, &wop); 3063 3064 check_invalid_snan(sd, status, 1); 3065 3066 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); 3067 TRACE_FP_RESULT_FPU1 (&ans); 3068} 3069 3070// NEGF.S 3071rrrrr,11111100001 + wwwww,10001001000:F_I:::negf_s 3072*v850e2v3 3073*v850e3v5 3074"negf.s r<reg2>, r<reg3>" 3075{ 3076 sim_fpu ans, wop; 3077 sim_fpu_status status; 3078 3079 sim_fpu_32to (&wop, GR[reg2]); 3080 TRACE_FP_INPUT_FPU1 (&wop); 3081 3082 status = sim_fpu_neg (&ans, &wop); 3083 3084 check_invalid_snan(sd, status, 0); 3085 3086 sim_fpu_to32 (&GR[reg3], &ans); 3087 TRACE_FP_RESULT_FPU1 (&ans); 3088} 3089 3090// NMADDF.S 3091rrrrr,111111,RRRRR + wwwww,101,W,10,WWWW,0:F_I:::nmaddf_s 3092*v850e2v3 3093*v850e3v5 3094"nmaddf.s r<reg1>, r<reg2>, r<reg3>, r<reg4>" 3095{ 3096 sim_fpu ans, wop1, wop2, wop3; 3097 sim_fpu_status status; 3098 3099 sim_fpu_32to (&wop1, GR[reg1]); 3100 sim_fpu_32to (&wop2, GR[reg2]); 3101 sim_fpu_32to (&wop3, GR[reg3]); 3102 TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3); 3103 3104 status = sim_fpu_mul (&ans, &wop1, &wop2); 3105 wop1 = ans; 3106 status |= sim_fpu_add (&ans, &wop1, &wop3); 3107 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); 3108 wop1 = ans; 3109 status |= sim_fpu_neg (&ans, &wop1); 3110 3111 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); 3112 3113 sim_fpu_to32 (&GR[reg4], &ans); 3114 TRACE_FP_RESULT_FPU1 (&ans); 3115} 3116 3117// NMSUBF.S 3118rrrrr,111111,RRRRR + wwwww,101,W,11,WWWW,0:F_I:::nmsubf_s 3119*v850e2v3 3120*v850e3v5 3121"nmsubf.s r<reg1>, r<reg2>, r<reg3>, r<reg4>" 3122{ 3123 sim_fpu ans, wop1, wop2, wop3; 3124 sim_fpu_status status; 3125 3126 sim_fpu_32to (&wop1, GR[reg1]); 3127 sim_fpu_32to (&wop2, GR[reg2]); 3128 sim_fpu_32to (&wop3, GR[reg3]); 3129 TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3); 3130 3131 status = sim_fpu_mul (&ans, &wop1, &wop2); 3132 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); 3133 wop1 = ans; 3134 status |= sim_fpu_sub (&ans, &wop1, &wop3); 3135 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); 3136 wop1 = ans; 3137 status |= sim_fpu_neg (&ans, &wop1); 3138 3139 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); 3140 3141 sim_fpu_to32 (&GR[reg4], &ans); 3142 TRACE_FP_RESULT_FPU1 (&ans); 3143} 3144 3145// RECIPF.D 3146rrrr,011111100001 + wwww,010001011110:F_I:::recipf.d 3147*v850e2v3 3148*v850e3v5 3149"recipf.d r<reg2e>, r<reg3e>" 3150{ 3151 sim_fpu ans, wop; 3152 sim_fpu_status status; 3153 3154 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); 3155 TRACE_FP_INPUT_FPU1 (&wop); 3156 3157 status = sim_fpu_div (&ans, &sim_fpu_one, &wop); 3158 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); 3159 3160 update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1); 3161 3162 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); 3163 TRACE_FP_RESULT_FPU1 (&ans); 3164} 3165 3166// RECIPF.S 3167rrrrr,11111100001 + wwwww,10001001110:F_I:::recipf.s 3168*v850e2v3 3169*v850e3v5 3170"recipf.s r<reg2>, r<reg3>" 3171{ 3172 sim_fpu ans, wop; 3173 sim_fpu_status status; 3174 3175 sim_fpu_32to (&wop, GR[reg2]); 3176 TRACE_FP_INPUT_FPU1 (&wop); 3177 3178 status = sim_fpu_div (&ans, &sim_fpu_one, &wop); 3179 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); 3180 3181 update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); 3182 3183 sim_fpu_to32 (&GR[reg3], &ans); 3184 TRACE_FP_RESULT_FPU1 (&ans); 3185} 3186 3187// RSQRTF.D 3188rrrr,011111100010 + wwww,010001011110:F_I:::rsqrtf.d 3189*v850e2v3 3190*v850e3v5 3191"rsqrtf.d r<reg2e>, r<reg3e>" 3192{ 3193 sim_fpu ans, wop; 3194 sim_fpu_status status; 3195 3196 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); 3197 TRACE_FP_INPUT_FPU1 (&wop); 3198 3199 status = sim_fpu_sqrt (&ans, &wop); 3200 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); 3201 wop = ans; 3202 status = sim_fpu_div (&ans, &sim_fpu_one, &wop); 3203 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); 3204 3205 update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1); 3206 3207 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); 3208 TRACE_FP_RESULT_FPU1 (&ans); 3209} 3210 3211// RSQRTF.S 3212rrrrr,11111100010 + wwwww,10001001110:F_I:::rsqrtf.s 3213*v850e2v3 3214*v850e3v5 3215"rsqrtf.s r<reg2>, r<reg3>" 3216{ 3217 sim_fpu ans, wop; 3218 sim_fpu_status status; 3219 3220 sim_fpu_32to (&wop, GR[reg2]); 3221 TRACE_FP_INPUT_FPU1 (&wop); 3222 3223 status = sim_fpu_sqrt (&ans, &wop); 3224 status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); 3225 wop = ans; 3226 status = sim_fpu_div (&ans, &sim_fpu_one, &wop); 3227 status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); 3228 3229 update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); 3230 3231 sim_fpu_to32 (&GR[reg3], &ans); 3232 TRACE_FP_RESULT_FPU1 (&ans); 3233} 3234 3235// SQRTF.D 3236rrrr,011111100000 + wwww,010001011110:F_I:::sqrtf.d 3237*v850e2v3 3238*v850e3v5 3239"sqrtf.d r<reg2e>, r<reg3e>" 3240{ 3241 sim_fpu ans, wop; 3242 sim_fpu_status status; 3243 3244 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); 3245 TRACE_FP_INPUT_FPU1 (&wop); 3246 3247 status = sim_fpu_sqrt (&ans, &wop); 3248 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); 3249 3250 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI, 1); 3251 3252 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); 3253 TRACE_FP_RESULT_FPU1 (&ans); 3254} 3255 3256// SQRTF.S 3257rrrrr,11111100000 + wwwww,10001001110:F_I:::sqrtf.s 3258*v850e2v3 3259*v850e3v5 3260"sqrtf.s r<reg2>, r<reg3>" 3261{ 3262 sim_fpu ans, wop; 3263 sim_fpu_status status; 3264 3265 sim_fpu_32to (&wop, GR[reg2]); 3266 TRACE_FP_INPUT_FPU1 (&wop); 3267 3268 status = sim_fpu_sqrt (&ans, &wop); 3269 status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); 3270 3271 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI, 0); 3272 3273 sim_fpu_to32 (&GR[reg3], &ans); 3274 TRACE_FP_RESULT_FPU1 (&ans); 3275} 3276 3277// SUBF.D 3278rrrr,0111111,RRRR,0 + wwww,010001110010:F_I:::subf.d 3279*v850e2v3 3280*v850e3v5 3281"subf.d r<reg1e>, r<reg2e>, r<reg3e>" 3282{ 3283 sim_fpu ans, wop1, wop2; 3284 sim_fpu_status status; 3285 3286 sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]); 3287 sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]); 3288 TRACE_FP_INPUT_FPU2 (&wop1, &wop2); 3289 3290 status = sim_fpu_sub (&ans, &wop2, &wop1); 3291 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); 3292 3293 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1); 3294 3295 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); 3296 TRACE_FP_RESULT_FPU1 (&ans); 3297} 3298 3299// SUBF.S 3300rrrrr,111111,RRRRR + wwwww,10001100010:F_I:::subf.s 3301*v850e2v3 3302*v850e3v5 3303"subf.s r<reg1>, r<reg2>, r<reg3>" 3304{ 3305 sim_fpu ans, wop1, wop2; 3306 sim_fpu_status status; 3307 3308 sim_fpu_32to (&wop1, GR[reg1]); 3309 sim_fpu_32to (&wop2, GR[reg2]); 3310 TRACE_FP_INPUT_FPU2 (&wop1, &wop2); 3311 3312 status = sim_fpu_sub (&ans, &wop2, &wop1); 3313 status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); 3314 3315 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); 3316 3317 sim_fpu_to32 (&GR[reg3], &ans); 3318 TRACE_FP_RESULT_FPU1 (&ans); 3319} 3320 3321// TRFSR 33220000011111100000 + 000001000000,bbb,0:F_I:::trfsr 3323*v850e2v3 3324*v850e3v5 3325"trfsr":(bbb == 0) 3326"trfsr <bbb>" 3327{ 3328 TRACE_ALU_INPUT1 (GET_FPCC()); 3329 3330 if (TEST_FPCC (bbb)) 3331 PSW |= PSW_Z; 3332 else 3333 PSW &= ~PSW_Z; 3334 3335 TRACE_ALU_RESULT1 (PSW); 3336} 3337 3338// TRNCF.DL 3339rrrr,011111100001 + wwww,010001010100:F_I:::trncf_dl 3340*v850e2v3 3341*v850e3v5 3342"trncf.dl r<reg2e>, r<reg3e>" 3343{ 3344 signed64 ans; 3345 sim_fpu wop; 3346 sim_fpu_status status; 3347 3348 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); 3349 TRACE_FP_INPUT_FPU1 (&wop); 3350 3351 status = sim_fpu_to64i (&ans, &wop, sim_fpu_round_zero); 3352 3353 check_cvt_fi(sd, status, 1); 3354 3355 GR[reg3e] = ans; 3356 GR[reg3e+1] = ans>>32L; 3357 TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]); 3358} 3359 3360// TRNCF.DUL 3361rrrr,011111110001 + wwww,010001010100:F_I:::trncf_dul 3362*v850e2v3 3363*v850e3v5 3364"trncf.dul r<reg2e>, r<reg3e>" 3365{ 3366 signed64 ans; 3367 sim_fpu wop; 3368 sim_fpu_status status; 3369 3370 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); 3371 TRACE_FP_INPUT_FPU1 (&wop); 3372 3373 status = sim_fpu_to64u (&ans, &wop, sim_fpu_round_zero); 3374 3375 check_cvt_fi(sd, status, 1); 3376 3377 GR[reg3e] = ans; 3378 GR[reg3e+1] = ans>>32L; 3379 TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]); 3380} 3381 3382// TRNCF.DW 3383rrrr,011111100001 + wwwww,10001010000:F_I:::trncf_dw 3384*v850e2v3 3385*v850e3v5 3386"trncf.dw r<reg2e>, r<reg3>" 3387{ 3388 uint32 ans; 3389 sim_fpu wop; 3390 sim_fpu_status status; 3391 3392 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); 3393 TRACE_FP_INPUT_FPU1 (&wop); 3394 3395 status = sim_fpu_to32i (&ans, &wop, sim_fpu_round_zero); 3396 3397 check_cvt_fi(sd, status, 1); 3398 3399 GR[reg3] = ans; 3400 TRACE_FP_RESULT_WORD1 (ans); 3401} 3402 3403// TRNCF.DUW 3404rrrr,011111110001 + wwwww,10001010000:F_I:::trncf_duw 3405*v850e2v3 3406*v850e3v5 3407"trncf.duw r<reg2e>, r<reg3>" 3408{ 3409 uint32 ans; 3410 sim_fpu wop; 3411 sim_fpu_status status; 3412 3413 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); 3414 TRACE_FP_INPUT_FPU1 (&wop); 3415 3416 status = sim_fpu_to32u (&ans, &wop, sim_fpu_round_zero); 3417 3418 check_cvt_fi(sd, status, 1); 3419 3420 GR[reg3] = ans; 3421 TRACE_FP_RESULT_WORD1 (ans); 3422} 3423 3424// TRNCF.SL 3425rrrrr,11111100001 + wwww,010001000100:F_I:::trncf_sl 3426*v850e2v3 3427*v850e3v5 3428"trncf.sl r<reg2>, r<reg3e>" 3429{ 3430 signed64 ans; 3431 sim_fpu wop; 3432 sim_fpu_status status; 3433 3434 sim_fpu_32to (&wop, GR[reg2]); 3435 TRACE_FP_INPUT_FPU1 (&wop); 3436 3437 status = sim_fpu_to64i (&ans, &wop, sim_fpu_round_zero); 3438 3439 GR[reg3e] = ans; 3440 GR[reg3e+1] = ans >> 32L; 3441 TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]); 3442} 3443 3444// TRNCF.SUL 3445rrrrr,11111110001 + wwww,010001000100:F_I:::trncf_sul 3446*v850e2v3 3447*v850e3v5 3448"trncf.sul r<reg2>, r<reg3e>" 3449{ 3450 signed64 ans; 3451 sim_fpu wop; 3452 sim_fpu_status status; 3453 3454 sim_fpu_32to (&wop, GR[reg2]); 3455 TRACE_FP_INPUT_FPU1 (&wop); 3456 3457 status = sim_fpu_to64u (&ans, &wop, sim_fpu_round_zero); 3458 3459 GR[reg3e] = ans; 3460 GR[reg3e+1] = ans >> 32L; 3461 TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]); 3462} 3463 3464// TRNCF.SW 3465rrrrr,11111100001 + wwwww,10001000000:F_I:::trncf_sw 3466*v850e2v3 3467*v850e3v5 3468"trncf.sw r<reg2>, r<reg3>" 3469{ 3470 uint32 ans; 3471 sim_fpu wop; 3472 sim_fpu_status status; 3473 3474 sim_fpu_32to (&wop, GR[reg2]); 3475 TRACE_FP_INPUT_FPU1 (&wop); 3476 3477 status = sim_fpu_to32i (&ans, &wop, sim_fpu_round_zero); 3478 3479 check_cvt_fi(sd, status, 0); 3480 3481 GR[reg3] = ans; 3482 TRACE_FP_RESULT_WORD1 (ans); 3483} 3484 3485 3486// TRNCF.SUW 3487rrrrr,11111110001 + wwwww,10001000000:F_I:::trncf_suw 3488*v850e2v3 3489*v850e3v5 3490"trncf.suw r<reg2>, r<reg3>" 3491{ 3492 uint32 ans; 3493 sim_fpu wop; 3494 sim_fpu_status status; 3495 3496 sim_fpu_32to (&wop, GR[reg2]); 3497 TRACE_FP_INPUT_FPU1 (&wop); 3498 3499 status = sim_fpu_to32u (&ans, &wop, sim_fpu_round_zero); 3500 3501 check_cvt_fi(sd, status, 0); 3502 3503 GR[reg3] = ans; 3504 TRACE_FP_RESULT_WORD1 (ans); 3505} 3506 3507 3508// ROTL 3509rrrrr,111111,iiiii+wwwww,00011000100:VII:::rotl_imm 3510*v850e3v5 3511"rotl imm5, r<reg2>, r<reg3>" 3512{ 3513 TRACE_ALU_INPUT1 (GR[reg2]); 3514 v850_rotl (sd, imm5, GR[reg2], & GR[reg3]); 3515 TRACE_ALU_RESULT1 (GR[reg3]); 3516} 3517 3518rrrrr,111111,RRRRR+wwwww,00011000110:VII:::rotl 3519*v850e3v5 3520"rotl r<reg1>, r<reg2>, r<reg3>" 3521{ 3522 TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]); 3523 v850_rotl (sd, GR[reg1], GR[reg2], & GR[reg3]); 3524 TRACE_ALU_RESULT1 (GR[reg3]); 3525} 3526 3527// BINS 3528rrrrr,111111,RRRRR+bbbb,B,0001001,BBB,0:IX:::bins_top 3529*v850e3v5 3530"bins r<reg1>, <bit13> + 16, <bit4> - <bit13> + 17, r<reg2>" 3531{ 3532 TRACE_ALU_INPUT1 (GR[reg1]); 3533 v850_bins (sd, GR[reg1], bit13 + 16, bit4 + 16, & GR[reg2]); 3534 TRACE_ALU_RESULT1 (GR[reg2]); 3535} 3536 3537rrrrr,111111,RRRRR+bbbb,B,0001011,BBB,0:IX:::bins_middle 3538*v850e3v5 3539"bins r<reg1>, <bit13>, <bit4> - <bit13> + 17, r<reg2>" 3540{ 3541 TRACE_ALU_INPUT1 (GR[reg1]); 3542 v850_bins (sd, GR[reg1], bit13, bit4 + 16, & GR[reg2]); 3543 TRACE_ALU_RESULT1 (GR[reg2]); 3544} 3545 3546rrrrr,111111,RRRRR+bbbb,B,0001101,BBB,0:IX:::bins_bottom 3547*v850e3v5 3548"bins r<reg1>, <bit13>, <bit4> - <bit13> + 1, r<reg2>" 3549{ 3550 TRACE_ALU_INPUT1 (GR[reg1]); 3551 v850_bins (sd, GR[reg1], bit13, bit4, & GR[reg2]); 3552 TRACE_ALU_RESULT1 (GR[reg2]); 3553} 3554