1 #include "sim-main.h" 2 #include "v850_sim.h" 3 #include "simops.h" 4 5 #include <sys/types.h> 6 7 #ifdef HAVE_UTIME_H 8 #include <utime.h> 9 #endif 10 11 #ifdef HAVE_TIME_H 12 #include <time.h> 13 #endif 14 15 #ifdef HAVE_UNISTD_H 16 #include <unistd.h> 17 #endif 18 19 #ifdef HAVE_STRING_H 20 #include <string.h> 21 #else 22 #ifdef HAVE_STRINGS_H 23 #include <strings.h> 24 #endif 25 #endif 26 27 #include "targ-vals.h" 28 29 #include "libiberty.h" 30 31 #include <errno.h> 32 #if !defined(__GO32__) && !defined(_WIN32) 33 #include <sys/stat.h> 34 #include <sys/times.h> 35 #include <sys/time.h> 36 #endif 37 38 /* This is an array of the bit positions of registers r20 .. r31 in 39 that order in a prepare/dispose instruction. */ 40 int type1_regs[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 }; 41 /* This is an array of the bit positions of registers r16 .. r31 in 42 that order in a push/pop instruction. */ 43 int type2_regs[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21}; 44 /* This is an array of the bit positions of registers r1 .. r15 in 45 that order in a push/pop instruction. */ 46 int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21}; 47 48 #ifdef DEBUG 49 #ifndef SIZE_INSTRUCTION 50 #define SIZE_INSTRUCTION 18 51 #endif 52 53 #ifndef SIZE_VALUES 54 #define SIZE_VALUES 11 55 #endif 56 57 58 unsigned32 trace_values[3]; 59 int trace_num_values; 60 unsigned32 trace_pc; 61 const char * trace_name; 62 int trace_module; 63 64 65 void 66 trace_input (char *name, enum op_types type, int size) 67 { 68 if (!TRACE_ALU_P (STATE_CPU (simulator, 0))) 69 return; 70 71 trace_pc = PC; 72 trace_name = name; 73 trace_module = TRACE_ALU_IDX; 74 75 switch (type) 76 { 77 default: 78 case OP_UNKNOWN: 79 case OP_NONE: 80 case OP_TRAP: 81 trace_num_values = 0; 82 break; 83 84 case OP_REG: 85 case OP_REG_REG_MOVE: 86 trace_values[0] = State.regs[OP[0]]; 87 trace_num_values = 1; 88 break; 89 90 case OP_BIT_CHANGE: 91 case OP_REG_REG: 92 case OP_REG_REG_CMP: 93 trace_values[0] = State.regs[OP[1]]; 94 trace_values[1] = State.regs[OP[0]]; 95 trace_num_values = 2; 96 break; 97 98 case OP_IMM_REG: 99 case OP_IMM_REG_CMP: 100 trace_values[0] = SEXT5 (OP[0]); 101 trace_values[1] = OP[1]; 102 trace_num_values = 2; 103 break; 104 105 case OP_IMM_REG_MOVE: 106 trace_values[0] = SEXT5 (OP[0]); 107 trace_num_values = 1; 108 break; 109 110 case OP_COND_BR: 111 trace_values[0] = State.pc; 112 trace_values[1] = SEXT9 (OP[0]); 113 trace_values[2] = PSW; 114 trace_num_values = 3; 115 break; 116 117 case OP_LOAD16: 118 trace_values[0] = OP[1] * size; 119 trace_values[1] = State.regs[30]; 120 trace_num_values = 2; 121 break; 122 123 case OP_STORE16: 124 trace_values[0] = State.regs[OP[0]]; 125 trace_values[1] = OP[1] * size; 126 trace_values[2] = State.regs[30]; 127 trace_num_values = 3; 128 break; 129 130 case OP_LOAD32: 131 trace_values[0] = EXTEND16 (OP[2]); 132 trace_values[1] = State.regs[OP[0]]; 133 trace_num_values = 2; 134 break; 135 136 case OP_STORE32: 137 trace_values[0] = State.regs[OP[1]]; 138 trace_values[1] = EXTEND16 (OP[2]); 139 trace_values[2] = State.regs[OP[0]]; 140 trace_num_values = 3; 141 break; 142 143 case OP_JUMP: 144 trace_values[0] = SEXT22 (OP[0]); 145 trace_values[1] = State.pc; 146 trace_num_values = 2; 147 break; 148 149 case OP_IMM_REG_REG: 150 trace_values[0] = EXTEND16 (OP[0]) << size; 151 trace_values[1] = State.regs[OP[1]]; 152 trace_num_values = 2; 153 break; 154 155 case OP_IMM16_REG_REG: 156 trace_values[0] = EXTEND16 (OP[2]) << size; 157 trace_values[1] = State.regs[OP[1]]; 158 trace_num_values = 2; 159 break; 160 161 case OP_UIMM_REG_REG: 162 trace_values[0] = (OP[0] & 0xffff) << size; 163 trace_values[1] = State.regs[OP[1]]; 164 trace_num_values = 2; 165 break; 166 167 case OP_UIMM16_REG_REG: 168 trace_values[0] = (OP[2]) << size; 169 trace_values[1] = State.regs[OP[1]]; 170 trace_num_values = 2; 171 break; 172 173 case OP_BIT: 174 trace_num_values = 0; 175 break; 176 177 case OP_EX1: 178 trace_values[0] = PSW; 179 trace_num_values = 1; 180 break; 181 182 case OP_EX2: 183 trace_num_values = 0; 184 break; 185 186 case OP_LDSR: 187 trace_values[0] = State.regs[OP[0]]; 188 trace_num_values = 1; 189 break; 190 191 case OP_STSR: 192 trace_values[0] = State.sregs[OP[1]]; 193 trace_num_values = 1; 194 } 195 196 } 197 198 void 199 trace_result (int has_result, unsigned32 result) 200 { 201 char buf[1000]; 202 char *chp; 203 204 buf[0] = '\0'; 205 chp = buf; 206 207 /* write out the values saved during the trace_input call */ 208 { 209 int i; 210 for (i = 0; i < trace_num_values; i++) 211 { 212 sprintf (chp, "%*s0x%.8lx", SIZE_VALUES - 10, "", 213 (long) trace_values[i]); 214 chp = strchr (chp, '\0'); 215 } 216 while (i++ < 3) 217 { 218 sprintf (chp, "%*s", SIZE_VALUES, ""); 219 chp = strchr (chp, '\0'); 220 } 221 } 222 223 /* append any result to the end of the buffer */ 224 if (has_result) 225 sprintf (chp, " :: 0x%.8lx", (unsigned long) result); 226 227 trace_generic (simulator, STATE_CPU (simulator, 0), trace_module, "%s", buf); 228 } 229 230 void 231 trace_output (enum op_types result) 232 { 233 if (!TRACE_ALU_P (STATE_CPU (simulator, 0))) 234 return; 235 236 switch (result) 237 { 238 default: 239 case OP_UNKNOWN: 240 case OP_NONE: 241 case OP_TRAP: 242 case OP_REG: 243 case OP_REG_REG_CMP: 244 case OP_IMM_REG_CMP: 245 case OP_COND_BR: 246 case OP_STORE16: 247 case OP_STORE32: 248 case OP_BIT: 249 case OP_EX2: 250 trace_result (0, 0); 251 break; 252 253 case OP_LOAD16: 254 case OP_STSR: 255 trace_result (1, State.regs[OP[0]]); 256 break; 257 258 case OP_REG_REG: 259 case OP_REG_REG_MOVE: 260 case OP_IMM_REG: 261 case OP_IMM_REG_MOVE: 262 case OP_LOAD32: 263 case OP_EX1: 264 trace_result (1, State.regs[OP[1]]); 265 break; 266 267 case OP_IMM_REG_REG: 268 case OP_UIMM_REG_REG: 269 case OP_IMM16_REG_REG: 270 case OP_UIMM16_REG_REG: 271 trace_result (1, State.regs[OP[1]]); 272 break; 273 274 case OP_JUMP: 275 if (OP[1] != 0) 276 trace_result (1, State.regs[OP[1]]); 277 else 278 trace_result (0, 0); 279 break; 280 281 case OP_LDSR: 282 trace_result (1, State.sregs[OP[1]]); 283 break; 284 } 285 } 286 #endif 287 288 289 /* Returns 1 if the specific condition is met, returns 0 otherwise. */ 290 int 291 condition_met (unsigned code) 292 { 293 unsigned int psw = PSW; 294 295 switch (code & 0xf) 296 { 297 case 0x0: return ((psw & PSW_OV) != 0); 298 case 0x1: return ((psw & PSW_CY) != 0); 299 case 0x2: return ((psw & PSW_Z) != 0); 300 case 0x3: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0); 301 case 0x4: return ((psw & PSW_S) != 0); 302 /*case 0x5: return 1;*/ 303 case 0x6: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0); 304 case 0x7: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) != 0); 305 case 0x8: return ((psw & PSW_OV) == 0); 306 case 0x9: return ((psw & PSW_CY) == 0); 307 case 0xa: return ((psw & PSW_Z) == 0); 308 case 0xb: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0); 309 case 0xc: return ((psw & PSW_S) == 0); 310 case 0xd: return ((psw & PSW_SAT) != 0); 311 case 0xe: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0); 312 case 0xf: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) == 0); 313 } 314 315 return 1; 316 } 317 318 unsigned long 319 Add32 (unsigned long a1, unsigned long a2, int * carry) 320 { 321 unsigned long result = (a1 + a2); 322 323 * carry = (result < a1); 324 325 return result; 326 } 327 328 static void 329 Multiply64 (int sign, unsigned long op0) 330 { 331 unsigned long op1; 332 unsigned long lo; 333 unsigned long mid1; 334 unsigned long mid2; 335 unsigned long hi; 336 unsigned long RdLo; 337 unsigned long RdHi; 338 int carry; 339 340 op1 = State.regs[ OP[1] ]; 341 342 if (sign) 343 { 344 /* Compute sign of result and adjust operands if necessary. */ 345 346 sign = (op0 ^ op1) & 0x80000000; 347 348 if (((signed long) op0) < 0) 349 op0 = - op0; 350 351 if (((signed long) op1) < 0) 352 op1 = - op1; 353 } 354 355 /* We can split the 32x32 into four 16x16 operations. This ensures 356 that we do not lose precision on 32bit only hosts: */ 357 lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF)); 358 mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF)); 359 mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF)); 360 hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF)); 361 362 /* We now need to add all of these results together, taking care 363 to propogate the carries from the additions: */ 364 RdLo = Add32 (lo, (mid1 << 16), & carry); 365 RdHi = carry; 366 RdLo = Add32 (RdLo, (mid2 << 16), & carry); 367 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi); 368 369 if (sign) 370 { 371 /* Negate result if necessary. */ 372 373 RdLo = ~ RdLo; 374 RdHi = ~ RdHi; 375 if (RdLo == 0xFFFFFFFF) 376 { 377 RdLo = 0; 378 RdHi += 1; 379 } 380 else 381 RdLo += 1; 382 } 383 384 /* Don't store into register 0. */ 385 if (OP[1]) 386 State.regs[ OP[1] ] = RdLo; 387 if (OP[2] >> 11) 388 State.regs[ OP[2] >> 11 ] = RdHi; 389 390 return; 391 } 392 393 394 /* Read a null terminated string from memory, return in a buffer. */ 395 396 static char * 397 fetch_str (SIM_DESC sd, address_word addr) 398 { 399 char *buf; 400 int nr = 0; 401 402 while (sim_core_read_1 (STATE_CPU (sd, 0), 403 PC, read_map, addr + nr) != 0) 404 nr++; 405 406 buf = NZALLOC (char, nr + 1); 407 sim_read (simulator, addr, (unsigned char *) buf, nr); 408 409 return buf; 410 } 411 412 /* Read a null terminated argument vector from memory, return in a 413 buffer. */ 414 415 static char ** 416 fetch_argv (SIM_DESC sd, address_word addr) 417 { 418 int max_nr = 64; 419 int nr = 0; 420 char **buf = xmalloc (max_nr * sizeof (char*)); 421 422 while (1) 423 { 424 unsigned32 a = sim_core_read_4 (STATE_CPU (sd, 0), 425 PC, read_map, addr + nr * 4); 426 if (a == 0) break; 427 buf[nr] = fetch_str (sd, a); 428 nr ++; 429 if (nr == max_nr - 1) 430 { 431 max_nr += 50; 432 buf = xrealloc (buf, max_nr * sizeof (char*)); 433 } 434 } 435 buf[nr] = 0; 436 return buf; 437 } 438 439 440 /* sst.b */ 441 int 442 OP_380 (void) 443 { 444 trace_input ("sst.b", OP_STORE16, 1); 445 446 store_mem (State.regs[30] + (OP[3] & 0x7f), 1, State.regs[ OP[1] ]); 447 448 trace_output (OP_STORE16); 449 450 return 2; 451 } 452 453 /* sst.h */ 454 int 455 OP_480 (void) 456 { 457 trace_input ("sst.h", OP_STORE16, 2); 458 459 store_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2, State.regs[ OP[1] ]); 460 461 trace_output (OP_STORE16); 462 463 return 2; 464 } 465 466 /* sst.w */ 467 int 468 OP_501 (void) 469 { 470 trace_input ("sst.w", OP_STORE16, 4); 471 472 store_mem (State.regs[30] + ((OP[3] & 0x7e) << 1), 4, State.regs[ OP[1] ]); 473 474 trace_output (OP_STORE16); 475 476 return 2; 477 } 478 479 /* ld.b */ 480 int 481 OP_700 (void) 482 { 483 int adr; 484 485 trace_input ("ld.b", OP_LOAD32, 1); 486 487 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]); 488 489 State.regs[ OP[1] ] = EXTEND8 (load_mem (adr, 1)); 490 491 trace_output (OP_LOAD32); 492 493 return 4; 494 } 495 496 /* ld.h */ 497 int 498 OP_720 (void) 499 { 500 int adr; 501 502 trace_input ("ld.h", OP_LOAD32, 2); 503 504 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]); 505 adr &= ~0x1; 506 507 State.regs[ OP[1] ] = EXTEND16 (load_mem (adr, 2)); 508 509 trace_output (OP_LOAD32); 510 511 return 4; 512 } 513 514 /* ld.w */ 515 int 516 OP_10720 (void) 517 { 518 int adr; 519 520 trace_input ("ld.w", OP_LOAD32, 4); 521 522 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1); 523 adr &= ~0x3; 524 525 State.regs[ OP[1] ] = load_mem (adr, 4); 526 527 trace_output (OP_LOAD32); 528 529 return 4; 530 } 531 532 /* st.b */ 533 int 534 OP_740 (void) 535 { 536 trace_input ("st.b", OP_STORE32, 1); 537 538 store_mem (State.regs[ OP[0] ] + EXTEND16 (OP[2]), 1, State.regs[ OP[1] ]); 539 540 trace_output (OP_STORE32); 541 542 return 4; 543 } 544 545 /* st.h */ 546 int 547 OP_760 (void) 548 { 549 int adr; 550 551 trace_input ("st.h", OP_STORE32, 2); 552 553 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]); 554 adr &= ~1; 555 556 store_mem (adr, 2, State.regs[ OP[1] ]); 557 558 trace_output (OP_STORE32); 559 560 return 4; 561 } 562 563 /* st.w */ 564 int 565 OP_10760 (void) 566 { 567 int adr; 568 569 trace_input ("st.w", OP_STORE32, 4); 570 571 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1); 572 adr &= ~3; 573 574 store_mem (adr, 4, State.regs[ OP[1] ]); 575 576 trace_output (OP_STORE32); 577 578 return 4; 579 } 580 581 /* add reg, reg */ 582 int 583 OP_1C0 (void) 584 { 585 unsigned int op0, op1, result, z, s, cy, ov; 586 587 trace_input ("add", OP_REG_REG, 0); 588 589 /* Compute the result. */ 590 591 op0 = State.regs[ OP[0] ]; 592 op1 = State.regs[ OP[1] ]; 593 594 result = op0 + op1; 595 596 /* Compute the condition codes. */ 597 z = (result == 0); 598 s = (result & 0x80000000); 599 cy = (result < op0 || result < op1); 600 ov = ((op0 & 0x80000000) == (op1 & 0x80000000) 601 && (op0 & 0x80000000) != (result & 0x80000000)); 602 603 /* Store the result and condition codes. */ 604 State.regs[OP[1]] = result; 605 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 606 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 607 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); 608 trace_output (OP_REG_REG); 609 610 return 2; 611 } 612 613 /* add sign_extend(imm5), reg */ 614 int 615 OP_240 (void) 616 { 617 unsigned int op0, op1, result, z, s, cy, ov; 618 int temp; 619 620 trace_input ("add", OP_IMM_REG, 0); 621 622 /* Compute the result. */ 623 temp = SEXT5 (OP[0]); 624 op0 = temp; 625 op1 = State.regs[OP[1]]; 626 result = op0 + op1; 627 628 /* Compute the condition codes. */ 629 z = (result == 0); 630 s = (result & 0x80000000); 631 cy = (result < op0 || result < op1); 632 ov = ((op0 & 0x80000000) == (op1 & 0x80000000) 633 && (op0 & 0x80000000) != (result & 0x80000000)); 634 635 /* Store the result and condition codes. */ 636 State.regs[OP[1]] = result; 637 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 638 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 639 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); 640 trace_output (OP_IMM_REG); 641 642 return 2; 643 } 644 645 /* addi sign_extend(imm16), reg, reg */ 646 int 647 OP_600 (void) 648 { 649 unsigned int op0, op1, result, z, s, cy, ov; 650 651 trace_input ("addi", OP_IMM16_REG_REG, 0); 652 653 /* Compute the result. */ 654 655 op0 = EXTEND16 (OP[2]); 656 op1 = State.regs[ OP[0] ]; 657 result = op0 + op1; 658 659 /* Compute the condition codes. */ 660 z = (result == 0); 661 s = (result & 0x80000000); 662 cy = (result < op0 || result < op1); 663 ov = ((op0 & 0x80000000) == (op1 & 0x80000000) 664 && (op0 & 0x80000000) != (result & 0x80000000)); 665 666 /* Store the result and condition codes. */ 667 State.regs[OP[1]] = result; 668 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 669 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 670 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); 671 trace_output (OP_IMM16_REG_REG); 672 673 return 4; 674 } 675 676 /* sub reg1, reg2 */ 677 int 678 OP_1A0 (void) 679 { 680 unsigned int op0, op1, result, z, s, cy, ov; 681 682 trace_input ("sub", OP_REG_REG, 0); 683 /* Compute the result. */ 684 op0 = State.regs[ OP[0] ]; 685 op1 = State.regs[ OP[1] ]; 686 result = op1 - op0; 687 688 /* Compute the condition codes. */ 689 z = (result == 0); 690 s = (result & 0x80000000); 691 cy = (op1 < op0); 692 ov = ((op1 & 0x80000000) != (op0 & 0x80000000) 693 && (op1 & 0x80000000) != (result & 0x80000000)); 694 695 /* Store the result and condition codes. */ 696 State.regs[OP[1]] = result; 697 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 698 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 699 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); 700 trace_output (OP_REG_REG); 701 702 return 2; 703 } 704 705 /* subr reg1, reg2 */ 706 int 707 OP_180 (void) 708 { 709 unsigned int op0, op1, result, z, s, cy, ov; 710 711 trace_input ("subr", OP_REG_REG, 0); 712 /* Compute the result. */ 713 op0 = State.regs[ OP[0] ]; 714 op1 = State.regs[ OP[1] ]; 715 result = op0 - op1; 716 717 /* Compute the condition codes. */ 718 z = (result == 0); 719 s = (result & 0x80000000); 720 cy = (op0 < op1); 721 ov = ((op0 & 0x80000000) != (op1 & 0x80000000) 722 && (op0 & 0x80000000) != (result & 0x80000000)); 723 724 /* Store the result and condition codes. */ 725 State.regs[OP[1]] = result; 726 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 727 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 728 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); 729 trace_output (OP_REG_REG); 730 731 return 2; 732 } 733 734 /* sxh reg1 */ 735 int 736 OP_E0 (void) 737 { 738 trace_input ("mulh", OP_REG_REG, 0); 739 740 State.regs[ OP[1] ] = (EXTEND16 (State.regs[ OP[1] ]) * EXTEND16 (State.regs[ OP[0] ])); 741 742 trace_output (OP_REG_REG); 743 744 return 2; 745 } 746 747 /* mulh sign_extend(imm5), reg2 */ 748 int 749 OP_2E0 (void) 750 { 751 trace_input ("mulh", OP_IMM_REG, 0); 752 753 State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[1] ]) * SEXT5 (OP[0]); 754 755 trace_output (OP_IMM_REG); 756 757 return 2; 758 } 759 760 /* mulhi imm16, reg1, reg2 */ 761 int 762 OP_6E0 (void) 763 { 764 trace_input ("mulhi", OP_IMM16_REG_REG, 0); 765 766 State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[0] ]) * EXTEND16 (OP[2]); 767 768 trace_output (OP_IMM16_REG_REG); 769 770 return 4; 771 } 772 773 /* cmp reg, reg */ 774 int 775 OP_1E0 (void) 776 { 777 unsigned int op0, op1, result, z, s, cy, ov; 778 779 trace_input ("cmp", OP_REG_REG_CMP, 0); 780 /* Compute the result. */ 781 op0 = State.regs[ OP[0] ]; 782 op1 = State.regs[ OP[1] ]; 783 result = op1 - op0; 784 785 /* Compute the condition codes. */ 786 z = (result == 0); 787 s = (result & 0x80000000); 788 cy = (op1 < op0); 789 ov = ((op1 & 0x80000000) != (op0 & 0x80000000) 790 && (op1 & 0x80000000) != (result & 0x80000000)); 791 792 /* Set condition codes. */ 793 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 794 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 795 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); 796 trace_output (OP_REG_REG_CMP); 797 798 return 2; 799 } 800 801 /* cmp sign_extend(imm5), reg */ 802 int 803 OP_260 (void) 804 { 805 unsigned int op0, op1, result, z, s, cy, ov; 806 int temp; 807 808 /* Compute the result. */ 809 trace_input ("cmp", OP_IMM_REG_CMP, 0); 810 temp = SEXT5 (OP[0]); 811 op0 = temp; 812 op1 = State.regs[OP[1]]; 813 result = op1 - op0; 814 815 /* Compute the condition codes. */ 816 z = (result == 0); 817 s = (result & 0x80000000); 818 cy = (op1 < op0); 819 ov = ((op1 & 0x80000000) != (op0 & 0x80000000) 820 && (op1 & 0x80000000) != (result & 0x80000000)); 821 822 /* Set condition codes. */ 823 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 824 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 825 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); 826 trace_output (OP_IMM_REG_CMP); 827 828 return 2; 829 } 830 831 /* setf cccc,reg2 */ 832 int 833 OP_7E0 (void) 834 { 835 trace_input ("setf", OP_EX1, 0); 836 837 State.regs[ OP[1] ] = condition_met (OP[0]); 838 839 trace_output (OP_EX1); 840 841 return 4; 842 } 843 844 /* satadd reg,reg */ 845 int 846 OP_C0 (void) 847 { 848 unsigned int op0, op1, result, z, s, cy, ov, sat; 849 850 trace_input ("satadd", OP_REG_REG, 0); 851 /* Compute the result. */ 852 op0 = State.regs[ OP[0] ]; 853 op1 = State.regs[ OP[1] ]; 854 result = op0 + op1; 855 856 /* Compute the condition codes. */ 857 z = (result == 0); 858 s = (result & 0x80000000); 859 cy = (result < op0 || result < op1); 860 ov = ((op0 & 0x80000000) == (op1 & 0x80000000) 861 && (op0 & 0x80000000) != (result & 0x80000000)); 862 sat = ov; 863 864 /* Handle saturated results. */ 865 if (sat && s) 866 { 867 /* An overflow that results in a negative result implies that we 868 became too positive. */ 869 result = 0x7fffffff; 870 s = 0; 871 } 872 else if (sat) 873 { 874 /* Any other overflow must have thus been too negative. */ 875 result = 0x80000000; 876 s = 1; 877 z = 0; 878 } 879 880 /* Store the result and condition codes. */ 881 State.regs[OP[1]] = result; 882 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 883 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 884 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) 885 | (sat ? PSW_SAT : 0)); 886 887 trace_output (OP_REG_REG); 888 889 return 2; 890 } 891 892 /* satadd sign_extend(imm5), reg */ 893 int 894 OP_220 (void) 895 { 896 unsigned int op0, op1, result, z, s, cy, ov, sat; 897 898 int temp; 899 900 trace_input ("satadd", OP_IMM_REG, 0); 901 902 /* Compute the result. */ 903 temp = SEXT5 (OP[0]); 904 op0 = temp; 905 op1 = State.regs[OP[1]]; 906 result = op0 + op1; 907 908 /* Compute the condition codes. */ 909 z = (result == 0); 910 s = (result & 0x80000000); 911 cy = (result < op0 || result < op1); 912 ov = ((op0 & 0x80000000) == (op1 & 0x80000000) 913 && (op0 & 0x80000000) != (result & 0x80000000)); 914 sat = ov; 915 916 /* Handle saturated results. */ 917 if (sat && s) 918 { 919 /* An overflow that results in a negative result implies that we 920 became too positive. */ 921 result = 0x7fffffff; 922 s = 0; 923 } 924 else if (sat) 925 { 926 /* Any other overflow must have thus been too negative. */ 927 result = 0x80000000; 928 s = 1; 929 z = 0; 930 } 931 932 /* Store the result and condition codes. */ 933 State.regs[OP[1]] = result; 934 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 935 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 936 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) 937 | (sat ? PSW_SAT : 0)); 938 trace_output (OP_IMM_REG); 939 940 return 2; 941 } 942 943 /* satsub reg1, reg2 */ 944 int 945 OP_A0 (void) 946 { 947 unsigned int op0, op1, result, z, s, cy, ov, sat; 948 949 trace_input ("satsub", OP_REG_REG, 0); 950 951 /* Compute the result. */ 952 op0 = State.regs[ OP[0] ]; 953 op1 = State.regs[ OP[1] ]; 954 result = op1 - op0; 955 956 /* Compute the condition codes. */ 957 z = (result == 0); 958 s = (result & 0x80000000); 959 cy = (op1 < op0); 960 ov = ((op1 & 0x80000000) != (op0 & 0x80000000) 961 && (op1 & 0x80000000) != (result & 0x80000000)); 962 sat = ov; 963 964 /* Handle saturated results. */ 965 if (sat && s) 966 { 967 /* An overflow that results in a negative result implies that we 968 became too positive. */ 969 result = 0x7fffffff; 970 s = 0; 971 } 972 else if (sat) 973 { 974 /* Any other overflow must have thus been too negative. */ 975 result = 0x80000000; 976 s = 1; 977 z = 0; 978 } 979 980 /* Store the result and condition codes. */ 981 State.regs[OP[1]] = result; 982 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 983 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 984 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) 985 | (sat ? PSW_SAT : 0)); 986 987 trace_output (OP_REG_REG); 988 return 2; 989 } 990 991 /* satsubi sign_extend(imm16), reg */ 992 int 993 OP_660 (void) 994 { 995 unsigned int op0, op1, result, z, s, cy, ov, sat; 996 int temp; 997 998 trace_input ("satsubi", OP_IMM_REG, 0); 999 1000 /* Compute the result. */ 1001 temp = EXTEND16 (OP[2]); 1002 op0 = temp; 1003 op1 = State.regs[ OP[0] ]; 1004 result = op1 - op0; 1005 1006 /* Compute the condition codes. */ 1007 z = (result == 0); 1008 s = (result & 0x80000000); 1009 cy = (op1 < op0); 1010 ov = ((op1 & 0x80000000) != (op0 & 0x80000000) 1011 && (op1 & 0x80000000) != (result & 0x80000000)); 1012 sat = ov; 1013 1014 /* Handle saturated results. */ 1015 if (sat && s) 1016 { 1017 /* An overflow that results in a negative result implies that we 1018 became too positive. */ 1019 result = 0x7fffffff; 1020 s = 0; 1021 } 1022 else if (sat) 1023 { 1024 /* Any other overflow must have thus been too negative. */ 1025 result = 0x80000000; 1026 s = 1; 1027 z = 0; 1028 } 1029 1030 /* Store the result and condition codes. */ 1031 State.regs[OP[1]] = result; 1032 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 1033 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 1034 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) 1035 | (sat ? PSW_SAT : 0)); 1036 1037 trace_output (OP_IMM_REG); 1038 1039 return 4; 1040 } 1041 1042 /* satsubr reg,reg */ 1043 int 1044 OP_80 (void) 1045 { 1046 unsigned int op0, op1, result, z, s, cy, ov, sat; 1047 1048 trace_input ("satsubr", OP_REG_REG, 0); 1049 1050 /* Compute the result. */ 1051 op0 = State.regs[ OP[0] ]; 1052 op1 = State.regs[ OP[1] ]; 1053 result = op0 - op1; 1054 1055 /* Compute the condition codes. */ 1056 z = (result == 0); 1057 s = (result & 0x80000000); 1058 cy = (op0 < op1); 1059 ov = ((op0 & 0x80000000) != (op1 & 0x80000000) 1060 && (op0 & 0x80000000) != (result & 0x80000000)); 1061 sat = ov; 1062 1063 /* Handle saturated results. */ 1064 if (sat && s) 1065 { 1066 /* An overflow that results in a negative result implies that we 1067 became too positive. */ 1068 result = 0x7fffffff; 1069 s = 0; 1070 } 1071 else if (sat) 1072 { 1073 /* Any other overflow must have thus been too negative. */ 1074 result = 0x80000000; 1075 s = 1; 1076 z = 0; 1077 } 1078 1079 /* Store the result and condition codes. */ 1080 State.regs[OP[1]] = result; 1081 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 1082 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 1083 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) 1084 | (sat ? PSW_SAT : 0)); 1085 1086 trace_output (OP_REG_REG); 1087 1088 return 2; 1089 } 1090 1091 /* tst reg,reg */ 1092 int 1093 OP_160 (void) 1094 { 1095 unsigned int op0, op1, result, z, s; 1096 1097 trace_input ("tst", OP_REG_REG_CMP, 0); 1098 1099 /* Compute the result. */ 1100 op0 = State.regs[ OP[0] ]; 1101 op1 = State.regs[ OP[1] ]; 1102 result = op0 & op1; 1103 1104 /* Compute the condition codes. */ 1105 z = (result == 0); 1106 s = (result & 0x80000000); 1107 1108 /* Store the condition codes. */ 1109 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 1110 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); 1111 trace_output (OP_REG_REG_CMP); 1112 1113 return 2; 1114 } 1115 1116 /* mov sign_extend(imm5), reg */ 1117 int 1118 OP_200 (void) 1119 { 1120 int value = SEXT5 (OP[0]); 1121 1122 trace_input ("mov", OP_IMM_REG_MOVE, 0); 1123 1124 State.regs[ OP[1] ] = value; 1125 1126 trace_output (OP_IMM_REG_MOVE); 1127 1128 return 2; 1129 } 1130 1131 /* movhi imm16, reg, reg */ 1132 int 1133 OP_640 (void) 1134 { 1135 trace_input ("movhi", OP_UIMM16_REG_REG, 16); 1136 1137 State.regs[ OP[1] ] = State.regs[ OP[0] ] + (OP[2] << 16); 1138 1139 trace_output (OP_UIMM16_REG_REG); 1140 1141 return 4; 1142 } 1143 1144 /* sar zero_extend(imm5),reg1 */ 1145 int 1146 OP_2A0 (void) 1147 { 1148 unsigned int op0, op1, result, z, s, cy; 1149 1150 trace_input ("sar", OP_IMM_REG, 0); 1151 op0 = OP[0]; 1152 op1 = State.regs[ OP[1] ]; 1153 result = (signed)op1 >> op0; 1154 1155 /* Compute the condition codes. */ 1156 z = (result == 0); 1157 s = (result & 0x80000000); 1158 cy = op0 ? (op1 & (1 << (op0 - 1))) : 0; 1159 1160 /* Store the result and condition codes. */ 1161 State.regs[ OP[1] ] = result; 1162 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); 1163 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 1164 | (cy ? PSW_CY : 0)); 1165 trace_output (OP_IMM_REG); 1166 1167 return 2; 1168 } 1169 1170 /* sar reg1, reg2 */ 1171 int 1172 OP_A007E0 (void) 1173 { 1174 unsigned int op0, op1, result, z, s, cy; 1175 1176 trace_input ("sar", OP_REG_REG, 0); 1177 1178 op0 = State.regs[ OP[0] ] & 0x1f; 1179 op1 = State.regs[ OP[1] ]; 1180 result = (signed)op1 >> op0; 1181 1182 /* Compute the condition codes. */ 1183 z = (result == 0); 1184 s = (result & 0x80000000); 1185 cy = op0 ? (op1 & (1 << (op0 - 1))) : 0; 1186 1187 /* Store the result and condition codes. */ 1188 State.regs[OP[1]] = result; 1189 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); 1190 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 1191 | (cy ? PSW_CY : 0)); 1192 trace_output (OP_REG_REG); 1193 1194 return 4; 1195 } 1196 1197 /* shl zero_extend(imm5),reg1 */ 1198 int 1199 OP_2C0 (void) 1200 { 1201 unsigned int op0, op1, result, z, s, cy; 1202 1203 trace_input ("shl", OP_IMM_REG, 0); 1204 op0 = OP[0]; 1205 op1 = State.regs[ OP[1] ]; 1206 result = op1 << op0; 1207 1208 /* Compute the condition codes. */ 1209 z = (result == 0); 1210 s = (result & 0x80000000); 1211 cy = op0 ? (op1 & (1 << (32 - op0))) : 0; 1212 1213 /* Store the result and condition codes. */ 1214 State.regs[OP[1]] = result; 1215 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); 1216 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 1217 | (cy ? PSW_CY : 0)); 1218 trace_output (OP_IMM_REG); 1219 1220 return 2; 1221 } 1222 1223 /* shl reg1, reg2 */ 1224 int 1225 OP_C007E0 (void) 1226 { 1227 unsigned int op0, op1, result, z, s, cy; 1228 1229 trace_input ("shl", OP_REG_REG, 0); 1230 op0 = State.regs[ OP[0] ] & 0x1f; 1231 op1 = State.regs[ OP[1] ]; 1232 result = op1 << op0; 1233 1234 /* Compute the condition codes. */ 1235 z = (result == 0); 1236 s = (result & 0x80000000); 1237 cy = op0 ? (op1 & (1 << (32 - op0))) : 0; 1238 1239 /* Store the result and condition codes. */ 1240 State.regs[OP[1]] = result; 1241 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); 1242 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 1243 | (cy ? PSW_CY : 0)); 1244 trace_output (OP_REG_REG); 1245 1246 return 4; 1247 } 1248 1249 /* shr zero_extend(imm5),reg1 */ 1250 int 1251 OP_280 (void) 1252 { 1253 unsigned int op0, op1, result, z, s, cy; 1254 1255 trace_input ("shr", OP_IMM_REG, 0); 1256 op0 = OP[0]; 1257 op1 = State.regs[ OP[1] ]; 1258 result = op1 >> op0; 1259 1260 /* Compute the condition codes. */ 1261 z = (result == 0); 1262 s = (result & 0x80000000); 1263 cy = op0 ? (op1 & (1 << (op0 - 1))) : 0; 1264 1265 /* Store the result and condition codes. */ 1266 State.regs[OP[1]] = result; 1267 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); 1268 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 1269 | (cy ? PSW_CY : 0)); 1270 trace_output (OP_IMM_REG); 1271 1272 return 2; 1273 } 1274 1275 /* shr reg1, reg2 */ 1276 int 1277 OP_8007E0 (void) 1278 { 1279 unsigned int op0, op1, result, z, s, cy; 1280 1281 trace_input ("shr", OP_REG_REG, 0); 1282 op0 = State.regs[ OP[0] ] & 0x1f; 1283 op1 = State.regs[ OP[1] ]; 1284 result = op1 >> op0; 1285 1286 /* Compute the condition codes. */ 1287 z = (result == 0); 1288 s = (result & 0x80000000); 1289 cy = op0 ? (op1 & (1 << (op0 - 1))) : 0; 1290 1291 /* Store the result and condition codes. */ 1292 State.regs[OP[1]] = result; 1293 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); 1294 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 1295 | (cy ? PSW_CY : 0)); 1296 trace_output (OP_REG_REG); 1297 1298 return 4; 1299 } 1300 1301 /* or reg, reg */ 1302 int 1303 OP_100 (void) 1304 { 1305 unsigned int op0, op1, result, z, s; 1306 1307 trace_input ("or", OP_REG_REG, 0); 1308 1309 /* Compute the result. */ 1310 op0 = State.regs[ OP[0] ]; 1311 op1 = State.regs[ OP[1] ]; 1312 result = op0 | op1; 1313 1314 /* Compute the condition codes. */ 1315 z = (result == 0); 1316 s = (result & 0x80000000); 1317 1318 /* Store the result and condition codes. */ 1319 State.regs[OP[1]] = result; 1320 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 1321 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); 1322 trace_output (OP_REG_REG); 1323 1324 return 2; 1325 } 1326 1327 /* ori zero_extend(imm16), reg, reg */ 1328 int 1329 OP_680 (void) 1330 { 1331 unsigned int op0, op1, result, z, s; 1332 1333 trace_input ("ori", OP_UIMM16_REG_REG, 0); 1334 op0 = OP[2]; 1335 op1 = State.regs[ OP[0] ]; 1336 result = op0 | op1; 1337 1338 /* Compute the condition codes. */ 1339 z = (result == 0); 1340 s = (result & 0x80000000); 1341 1342 /* Store the result and condition codes. */ 1343 State.regs[OP[1]] = result; 1344 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 1345 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); 1346 trace_output (OP_UIMM16_REG_REG); 1347 1348 return 4; 1349 } 1350 1351 /* and reg, reg */ 1352 int 1353 OP_140 (void) 1354 { 1355 unsigned int op0, op1, result, z, s; 1356 1357 trace_input ("and", OP_REG_REG, 0); 1358 1359 /* Compute the result. */ 1360 op0 = State.regs[ OP[0] ]; 1361 op1 = State.regs[ OP[1] ]; 1362 result = op0 & op1; 1363 1364 /* Compute the condition codes. */ 1365 z = (result == 0); 1366 s = (result & 0x80000000); 1367 1368 /* Store the result and condition codes. */ 1369 State.regs[OP[1]] = result; 1370 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 1371 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); 1372 trace_output (OP_REG_REG); 1373 1374 return 2; 1375 } 1376 1377 /* andi zero_extend(imm16), reg, reg */ 1378 int 1379 OP_6C0 (void) 1380 { 1381 unsigned int result, z; 1382 1383 trace_input ("andi", OP_UIMM16_REG_REG, 0); 1384 1385 result = OP[2] & State.regs[ OP[0] ]; 1386 1387 /* Compute the condition codes. */ 1388 z = (result == 0); 1389 1390 /* Store the result and condition codes. */ 1391 State.regs[ OP[1] ] = result; 1392 1393 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 1394 PSW |= (z ? PSW_Z : 0); 1395 1396 trace_output (OP_UIMM16_REG_REG); 1397 1398 return 4; 1399 } 1400 1401 /* xor reg, reg */ 1402 int 1403 OP_120 (void) 1404 { 1405 unsigned int op0, op1, result, z, s; 1406 1407 trace_input ("xor", OP_REG_REG, 0); 1408 1409 /* Compute the result. */ 1410 op0 = State.regs[ OP[0] ]; 1411 op1 = State.regs[ OP[1] ]; 1412 result = op0 ^ op1; 1413 1414 /* Compute the condition codes. */ 1415 z = (result == 0); 1416 s = (result & 0x80000000); 1417 1418 /* Store the result and condition codes. */ 1419 State.regs[OP[1]] = result; 1420 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 1421 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); 1422 trace_output (OP_REG_REG); 1423 1424 return 2; 1425 } 1426 1427 /* xori zero_extend(imm16), reg, reg */ 1428 int 1429 OP_6A0 (void) 1430 { 1431 unsigned int op0, op1, result, z, s; 1432 1433 trace_input ("xori", OP_UIMM16_REG_REG, 0); 1434 op0 = OP[2]; 1435 op1 = State.regs[ OP[0] ]; 1436 result = op0 ^ op1; 1437 1438 /* Compute the condition codes. */ 1439 z = (result == 0); 1440 s = (result & 0x80000000); 1441 1442 /* Store the result and condition codes. */ 1443 State.regs[OP[1]] = result; 1444 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 1445 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); 1446 trace_output (OP_UIMM16_REG_REG); 1447 1448 return 4; 1449 } 1450 1451 /* not reg1, reg2 */ 1452 int 1453 OP_20 (void) 1454 { 1455 unsigned int op0, result, z, s; 1456 1457 trace_input ("not", OP_REG_REG_MOVE, 0); 1458 /* Compute the result. */ 1459 op0 = State.regs[ OP[0] ]; 1460 result = ~op0; 1461 1462 /* Compute the condition codes. */ 1463 z = (result == 0); 1464 s = (result & 0x80000000); 1465 1466 /* Store the result and condition codes. */ 1467 State.regs[OP[1]] = result; 1468 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 1469 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); 1470 trace_output (OP_REG_REG_MOVE); 1471 1472 return 2; 1473 } 1474 1475 /* set1 */ 1476 int 1477 OP_7C0 (void) 1478 { 1479 unsigned int op0, op1, op2; 1480 int temp; 1481 1482 trace_input ("set1", OP_BIT, 0); 1483 op0 = State.regs[ OP[0] ]; 1484 op1 = OP[1] & 0x7; 1485 temp = EXTEND16 (OP[2]); 1486 op2 = temp; 1487 temp = load_mem (op0 + op2, 1); 1488 PSW &= ~PSW_Z; 1489 if ((temp & (1 << op1)) == 0) 1490 PSW |= PSW_Z; 1491 temp |= (1 << op1); 1492 store_mem (op0 + op2, 1, temp); 1493 trace_output (OP_BIT); 1494 1495 return 4; 1496 } 1497 1498 /* not1 */ 1499 int 1500 OP_47C0 (void) 1501 { 1502 unsigned int op0, op1, op2; 1503 int temp; 1504 1505 trace_input ("not1", OP_BIT, 0); 1506 op0 = State.regs[ OP[0] ]; 1507 op1 = OP[1] & 0x7; 1508 temp = EXTEND16 (OP[2]); 1509 op2 = temp; 1510 temp = load_mem (op0 + op2, 1); 1511 PSW &= ~PSW_Z; 1512 if ((temp & (1 << op1)) == 0) 1513 PSW |= PSW_Z; 1514 temp ^= (1 << op1); 1515 store_mem (op0 + op2, 1, temp); 1516 trace_output (OP_BIT); 1517 1518 return 4; 1519 } 1520 1521 /* clr1 */ 1522 int 1523 OP_87C0 (void) 1524 { 1525 unsigned int op0, op1, op2; 1526 int temp; 1527 1528 trace_input ("clr1", OP_BIT, 0); 1529 op0 = State.regs[ OP[0] ]; 1530 op1 = OP[1] & 0x7; 1531 temp = EXTEND16 (OP[2]); 1532 op2 = temp; 1533 temp = load_mem (op0 + op2, 1); 1534 PSW &= ~PSW_Z; 1535 if ((temp & (1 << op1)) == 0) 1536 PSW |= PSW_Z; 1537 temp &= ~(1 << op1); 1538 store_mem (op0 + op2, 1, temp); 1539 trace_output (OP_BIT); 1540 1541 return 4; 1542 } 1543 1544 /* tst1 */ 1545 int 1546 OP_C7C0 (void) 1547 { 1548 unsigned int op0, op1, op2; 1549 int temp; 1550 1551 trace_input ("tst1", OP_BIT, 0); 1552 op0 = State.regs[ OP[0] ]; 1553 op1 = OP[1] & 0x7; 1554 temp = EXTEND16 (OP[2]); 1555 op2 = temp; 1556 temp = load_mem (op0 + op2, 1); 1557 PSW &= ~PSW_Z; 1558 if ((temp & (1 << op1)) == 0) 1559 PSW |= PSW_Z; 1560 trace_output (OP_BIT); 1561 1562 return 4; 1563 } 1564 1565 /* di */ 1566 int 1567 OP_16007E0 (void) 1568 { 1569 trace_input ("di", OP_NONE, 0); 1570 PSW |= PSW_ID; 1571 trace_output (OP_NONE); 1572 1573 return 4; 1574 } 1575 1576 /* ei */ 1577 int 1578 OP_16087E0 (void) 1579 { 1580 trace_input ("ei", OP_NONE, 0); 1581 PSW &= ~PSW_ID; 1582 trace_output (OP_NONE); 1583 1584 return 4; 1585 } 1586 1587 /* halt */ 1588 int 1589 OP_12007E0 (void) 1590 { 1591 trace_input ("halt", OP_NONE, 0); 1592 /* FIXME this should put processor into a mode where NMI still handled */ 1593 trace_output (OP_NONE); 1594 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC, 1595 sim_stopped, SIM_SIGTRAP); 1596 return 0; 1597 } 1598 1599 /* trap */ 1600 int 1601 OP_10007E0 (void) 1602 { 1603 trace_input ("trap", OP_TRAP, 0); 1604 trace_output (OP_TRAP); 1605 1606 /* Trap 31 is used for simulating OS I/O functions */ 1607 1608 if (OP[0] == 31) 1609 { 1610 int save_errno = errno; 1611 errno = 0; 1612 1613 /* Registers passed to trap 0 */ 1614 1615 #define FUNC State.regs[6] /* function number, return value */ 1616 #define PARM1 State.regs[7] /* optional parm 1 */ 1617 #define PARM2 State.regs[8] /* optional parm 2 */ 1618 #define PARM3 State.regs[9] /* optional parm 3 */ 1619 1620 /* Registers set by trap 0 */ 1621 1622 #define RETVAL State.regs[10] /* return value */ 1623 #define RETERR State.regs[11] /* return error code */ 1624 1625 /* Turn a pointer in a register into a pointer into real memory. */ 1626 1627 #define MEMPTR(x) (map (x)) 1628 1629 RETERR = 0; 1630 1631 switch (FUNC) 1632 { 1633 1634 #ifdef HAVE_FORK 1635 #ifdef TARGET_SYS_fork 1636 case TARGET_SYS_fork: 1637 RETVAL = fork (); 1638 RETERR = errno; 1639 break; 1640 #endif 1641 #endif 1642 1643 #ifdef HAVE_EXECVE 1644 #ifdef TARGET_SYS_execv 1645 case TARGET_SYS_execve: 1646 { 1647 char *path = fetch_str (simulator, PARM1); 1648 char **argv = fetch_argv (simulator, PARM2); 1649 char **envp = fetch_argv (simulator, PARM3); 1650 RETVAL = execve (path, argv, envp); 1651 free (path); 1652 freeargv (argv); 1653 freeargv (envp); 1654 RETERR = errno; 1655 break; 1656 } 1657 #endif 1658 #endif 1659 1660 #if HAVE_EXECV 1661 #ifdef TARGET_SYS_execv 1662 case TARGET_SYS_execv: 1663 { 1664 char *path = fetch_str (simulator, PARM1); 1665 char **argv = fetch_argv (simulator, PARM2); 1666 RETVAL = execv (path, argv); 1667 free (path); 1668 freeargv (argv); 1669 RETERR = errno; 1670 break; 1671 } 1672 #endif 1673 #endif 1674 1675 #if 0 1676 #ifdef TARGET_SYS_pipe 1677 case TARGET_SYS_pipe: 1678 { 1679 reg_t buf; 1680 int host_fd[2]; 1681 1682 buf = PARM1; 1683 RETVAL = pipe (host_fd); 1684 SW (buf, host_fd[0]); 1685 buf += sizeof (uint16); 1686 SW (buf, host_fd[1]); 1687 RETERR = errno; 1688 } 1689 break; 1690 #endif 1691 #endif 1692 1693 #if 0 1694 #ifdef TARGET_SYS_wait 1695 case TARGET_SYS_wait: 1696 { 1697 int status; 1698 1699 RETVAL = wait (&status); 1700 SW (PARM1, status); 1701 RETERR = errno; 1702 } 1703 break; 1704 #endif 1705 #endif 1706 1707 #ifdef TARGET_SYS_read 1708 case TARGET_SYS_read: 1709 { 1710 char *buf = zalloc (PARM3); 1711 RETVAL = sim_io_read (simulator, PARM1, buf, PARM3); 1712 sim_write (simulator, PARM2, (unsigned char *) buf, PARM3); 1713 free (buf); 1714 if ((int) RETVAL < 0) 1715 RETERR = sim_io_get_errno (simulator); 1716 break; 1717 } 1718 #endif 1719 1720 #ifdef TARGET_SYS_write 1721 case TARGET_SYS_write: 1722 { 1723 char *buf = zalloc (PARM3); 1724 sim_read (simulator, PARM2, (unsigned char *) buf, PARM3); 1725 if (PARM1 == 1) 1726 RETVAL = sim_io_write_stdout (simulator, buf, PARM3); 1727 else 1728 RETVAL = sim_io_write (simulator, PARM1, buf, PARM3); 1729 free (buf); 1730 if ((int) RETVAL < 0) 1731 RETERR = sim_io_get_errno (simulator); 1732 break; 1733 } 1734 #endif 1735 1736 #ifdef TARGET_SYS_lseek 1737 case TARGET_SYS_lseek: 1738 RETVAL = sim_io_lseek (simulator, PARM1, PARM2, PARM3); 1739 if ((int) RETVAL < 0) 1740 RETERR = sim_io_get_errno (simulator); 1741 break; 1742 #endif 1743 1744 #ifdef TARGET_SYS_close 1745 case TARGET_SYS_close: 1746 RETVAL = sim_io_close (simulator, PARM1); 1747 if ((int) RETVAL < 0) 1748 RETERR = sim_io_get_errno (simulator); 1749 break; 1750 #endif 1751 1752 #ifdef TARGET_SYS_open 1753 case TARGET_SYS_open: 1754 { 1755 char *buf = fetch_str (simulator, PARM1); 1756 RETVAL = sim_io_open (simulator, buf, PARM2); 1757 free (buf); 1758 if ((int) RETVAL < 0) 1759 RETERR = sim_io_get_errno (simulator); 1760 break; 1761 } 1762 #endif 1763 1764 #ifdef TARGET_SYS_exit 1765 case TARGET_SYS_exit: 1766 if ((PARM1 & 0xffff0000) == 0xdead0000 && (PARM1 & 0xffff) != 0) 1767 /* get signal encoded by kill */ 1768 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC, 1769 sim_signalled, PARM1 & 0xffff); 1770 else if (PARM1 == 0xdead) 1771 /* old libraries */ 1772 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC, 1773 sim_stopped, SIM_SIGABRT); 1774 else 1775 /* PARM1 has exit status */ 1776 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC, 1777 sim_exited, PARM1); 1778 break; 1779 #endif 1780 1781 #ifdef TARGET_SYS_stat 1782 case TARGET_SYS_stat: /* added at hmsi */ 1783 /* stat system call */ 1784 { 1785 struct stat host_stat; 1786 reg_t buf; 1787 char *path = fetch_str (simulator, PARM1); 1788 1789 RETVAL = sim_io_stat (simulator, path, &host_stat); 1790 1791 free (path); 1792 buf = PARM2; 1793 1794 /* Just wild-assed guesses. */ 1795 store_mem (buf, 2, host_stat.st_dev); 1796 store_mem (buf + 2, 2, host_stat.st_ino); 1797 store_mem (buf + 4, 4, host_stat.st_mode); 1798 store_mem (buf + 8, 2, host_stat.st_nlink); 1799 store_mem (buf + 10, 2, host_stat.st_uid); 1800 store_mem (buf + 12, 2, host_stat.st_gid); 1801 store_mem (buf + 14, 2, host_stat.st_rdev); 1802 store_mem (buf + 16, 4, host_stat.st_size); 1803 store_mem (buf + 20, 4, host_stat.st_atime); 1804 store_mem (buf + 28, 4, host_stat.st_mtime); 1805 store_mem (buf + 36, 4, host_stat.st_ctime); 1806 1807 if ((int) RETVAL < 0) 1808 RETERR = sim_io_get_errno (simulator); 1809 } 1810 break; 1811 #endif 1812 1813 #ifdef TARGET_SYS_fstat 1814 case TARGET_SYS_fstat: 1815 /* fstat system call */ 1816 { 1817 struct stat host_stat; 1818 reg_t buf; 1819 1820 RETVAL = sim_io_fstat (simulator, PARM1, &host_stat); 1821 1822 buf = PARM2; 1823 1824 /* Just wild-assed guesses. */ 1825 store_mem (buf, 2, host_stat.st_dev); 1826 store_mem (buf + 2, 2, host_stat.st_ino); 1827 store_mem (buf + 4, 4, host_stat.st_mode); 1828 store_mem (buf + 8, 2, host_stat.st_nlink); 1829 store_mem (buf + 10, 2, host_stat.st_uid); 1830 store_mem (buf + 12, 2, host_stat.st_gid); 1831 store_mem (buf + 14, 2, host_stat.st_rdev); 1832 store_mem (buf + 16, 4, host_stat.st_size); 1833 store_mem (buf + 20, 4, host_stat.st_atime); 1834 store_mem (buf + 28, 4, host_stat.st_mtime); 1835 store_mem (buf + 36, 4, host_stat.st_ctime); 1836 1837 if ((int) RETVAL < 0) 1838 RETERR = sim_io_get_errno (simulator); 1839 } 1840 break; 1841 #endif 1842 1843 #ifdef TARGET_SYS_rename 1844 case TARGET_SYS_rename: 1845 { 1846 char *oldpath = fetch_str (simulator, PARM1); 1847 char *newpath = fetch_str (simulator, PARM2); 1848 RETVAL = sim_io_rename (simulator, oldpath, newpath); 1849 free (oldpath); 1850 free (newpath); 1851 if ((int) RETVAL < 0) 1852 RETERR = sim_io_get_errno (simulator); 1853 } 1854 break; 1855 #endif 1856 1857 #ifdef TARGET_SYS_unlink 1858 case TARGET_SYS_unlink: 1859 { 1860 char *path = fetch_str (simulator, PARM1); 1861 RETVAL = sim_io_unlink (simulator, path); 1862 free (path); 1863 if ((int) RETVAL < 0) 1864 RETERR = sim_io_get_errno (simulator); 1865 } 1866 break; 1867 #endif 1868 1869 #ifdef HAVE_CHOWN 1870 #ifdef TARGET_SYS_chown 1871 case TARGET_SYS_chown: 1872 { 1873 char *path = fetch_str (simulator, PARM1); 1874 RETVAL = chown (path, PARM2, PARM3); 1875 free (path); 1876 RETERR = errno; 1877 } 1878 break; 1879 #endif 1880 #endif 1881 1882 #if HAVE_CHMOD 1883 #ifdef TARGET_SYS_chmod 1884 case TARGET_SYS_chmod: 1885 { 1886 char *path = fetch_str (simulator, PARM1); 1887 RETVAL = chmod (path, PARM2); 1888 free (path); 1889 RETERR = errno; 1890 } 1891 break; 1892 #endif 1893 #endif 1894 1895 #ifdef TARGET_SYS_time 1896 #if HAVE_TIME 1897 case TARGET_SYS_time: 1898 { 1899 time_t now; 1900 RETVAL = time (&now); 1901 store_mem (PARM1, 4, now); 1902 RETERR = errno; 1903 } 1904 break; 1905 #endif 1906 #endif 1907 1908 #if !defined(__GO32__) && !defined(_WIN32) 1909 #ifdef TARGET_SYS_times 1910 case TARGET_SYS_times: 1911 { 1912 struct tms tms; 1913 RETVAL = times (&tms); 1914 store_mem (PARM1, 4, tms.tms_utime); 1915 store_mem (PARM1 + 4, 4, tms.tms_stime); 1916 store_mem (PARM1 + 8, 4, tms.tms_cutime); 1917 store_mem (PARM1 + 12, 4, tms.tms_cstime); 1918 reterr = errno; 1919 break; 1920 } 1921 #endif 1922 #endif 1923 1924 #ifdef TARGET_SYS_gettimeofday 1925 #if !defined(__GO32__) && !defined(_WIN32) 1926 case TARGET_SYS_gettimeofday: 1927 { 1928 struct timeval t; 1929 struct timezone tz; 1930 RETVAL = gettimeofday (&t, &tz); 1931 store_mem (PARM1, 4, t.tv_sec); 1932 store_mem (PARM1 + 4, 4, t.tv_usec); 1933 store_mem (PARM2, 4, tz.tz_minuteswest); 1934 store_mem (PARM2 + 4, 4, tz.tz_dsttime); 1935 RETERR = errno; 1936 break; 1937 } 1938 #endif 1939 #endif 1940 1941 #ifdef TARGET_SYS_utime 1942 #if HAVE_UTIME 1943 case TARGET_SYS_utime: 1944 { 1945 /* Cast the second argument to void *, to avoid type mismatch 1946 if a prototype is present. */ 1947 sim_io_error (simulator, "Utime not supported"); 1948 /* RETVAL = utime (path, (void *) MEMPTR (PARM2)); */ 1949 } 1950 break; 1951 #endif 1952 #endif 1953 1954 default: 1955 abort (); 1956 } 1957 errno = save_errno; 1958 1959 return 4; 1960 } 1961 else 1962 { /* Trap 0 -> 30 */ 1963 EIPC = PC + 4; 1964 EIPSW = PSW; 1965 /* Mask out EICC */ 1966 ECR &= 0xffff0000; 1967 ECR |= 0x40 + OP[0]; 1968 /* Flag that we are now doing exception processing. */ 1969 PSW |= PSW_EP | PSW_ID; 1970 PC = (OP[0] < 0x10) ? 0x40 : 0x50; 1971 1972 return 0; 1973 } 1974 } 1975 1976 /* tst1 reg2, [reg1] */ 1977 int 1978 OP_E607E0 (void) 1979 { 1980 int temp; 1981 1982 trace_input ("tst1", OP_BIT, 1); 1983 1984 temp = load_mem (State.regs[ OP[0] ], 1); 1985 1986 PSW &= ~PSW_Z; 1987 if ((temp & (1 << (State.regs[ OP[1] ] & 0x7))) == 0) 1988 PSW |= PSW_Z; 1989 1990 trace_output (OP_BIT); 1991 1992 return 4; 1993 } 1994 1995 /* mulu reg1, reg2, reg3 */ 1996 int 1997 OP_22207E0 (void) 1998 { 1999 trace_input ("mulu", OP_REG_REG_REG, 0); 2000 2001 Multiply64 (0, State.regs[ OP[0] ]); 2002 2003 trace_output (OP_REG_REG_REG); 2004 2005 return 4; 2006 } 2007 2008 #define BIT_CHANGE_OP( name, binop ) \ 2009 unsigned int bit; \ 2010 unsigned int temp; \ 2011 \ 2012 trace_input (name, OP_BIT_CHANGE, 0); \ 2013 \ 2014 bit = 1 << (State.regs[ OP[1] ] & 0x7); \ 2015 temp = load_mem (State.regs[ OP[0] ], 1); \ 2016 \ 2017 PSW &= ~PSW_Z; \ 2018 if ((temp & bit) == 0) \ 2019 PSW |= PSW_Z; \ 2020 temp binop bit; \ 2021 \ 2022 store_mem (State.regs[ OP[0] ], 1, temp); \ 2023 \ 2024 trace_output (OP_BIT_CHANGE); \ 2025 \ 2026 return 4; 2027 2028 /* clr1 reg2, [reg1] */ 2029 int 2030 OP_E407E0 (void) 2031 { 2032 BIT_CHANGE_OP ("clr1", &= ~ ); 2033 } 2034 2035 /* not1 reg2, [reg1] */ 2036 int 2037 OP_E207E0 (void) 2038 { 2039 BIT_CHANGE_OP ("not1", ^= ); 2040 } 2041 2042 /* set1 */ 2043 int 2044 OP_E007E0 (void) 2045 { 2046 BIT_CHANGE_OP ("set1", |= ); 2047 } 2048 2049 /* sasf */ 2050 int 2051 OP_20007E0 (void) 2052 { 2053 trace_input ("sasf", OP_EX1, 0); 2054 2055 State.regs[ OP[1] ] = (State.regs[ OP[1] ] << 1) | condition_met (OP[0]); 2056 2057 trace_output (OP_EX1); 2058 2059 return 4; 2060 } 2061 2062 /* This function is courtesy of Sugimoto at NEC, via Seow Tan 2063 (Soew_Tan@el.nec.com) */ 2064 void 2065 divun 2066 ( 2067 unsigned int N, 2068 unsigned long int als, 2069 unsigned long int sfi, 2070 unsigned32 /*unsigned long int*/ * quotient_ptr, 2071 unsigned32 /*unsigned long int*/ * remainder_ptr, 2072 int * overflow_ptr 2073 ) 2074 { 2075 unsigned long ald = sfi >> (N - 1); 2076 unsigned long alo = als; 2077 unsigned int Q = 1; 2078 unsigned int C; 2079 unsigned int S = 0; 2080 unsigned int i; 2081 unsigned int R1 = 1; 2082 unsigned int DBZ = (als == 0) ? 1 : 0; 2083 unsigned long alt = Q ? ~als : als; 2084 2085 /* 1st Loop */ 2086 alo = ald + alt + Q; 2087 C = (((alt >> 31) & (ald >> 31)) 2088 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); 2089 C = C ^ Q; 2090 Q = ~(C ^ S) & 1; 2091 R1 = (alo == 0) ? 0 : (R1 & Q); 2092 if ((S ^ (alo>>31)) && !C) 2093 { 2094 DBZ = 1; 2095 } 2096 S = alo >> 31; 2097 sfi = (sfi << (32-N+1)) | Q; 2098 ald = (alo << 1) | (sfi >> 31); 2099 2100 /* 2nd - N-1th Loop */ 2101 for (i = 2; i < N; i++) 2102 { 2103 alt = Q ? ~als : als; 2104 alo = ald + alt + Q; 2105 C = (((alt >> 31) & (ald >> 31)) 2106 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); 2107 C = C ^ Q; 2108 Q = ~(C ^ S) & 1; 2109 R1 = (alo == 0) ? 0 : (R1 & Q); 2110 if ((S ^ (alo>>31)) && !C && !DBZ) 2111 { 2112 DBZ = 1; 2113 } 2114 S = alo >> 31; 2115 sfi = (sfi << 1) | Q; 2116 ald = (alo << 1) | (sfi >> 31); 2117 } 2118 2119 /* Nth Loop */ 2120 alt = Q ? ~als : als; 2121 alo = ald + alt + Q; 2122 C = (((alt >> 31) & (ald >> 31)) 2123 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); 2124 C = C ^ Q; 2125 Q = ~(C ^ S) & 1; 2126 R1 = (alo == 0) ? 0 : (R1 & Q); 2127 if ((S ^ (alo>>31)) && !C) 2128 { 2129 DBZ = 1; 2130 } 2131 2132 * quotient_ptr = (sfi << 1) | Q; 2133 * remainder_ptr = Q ? alo : (alo + als); 2134 * overflow_ptr = DBZ | R1; 2135 } 2136 2137 /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */ 2138 void 2139 divn 2140 ( 2141 unsigned int N, 2142 unsigned long int als, 2143 unsigned long int sfi, 2144 signed32 /*signed long int*/ * quotient_ptr, 2145 signed32 /*signed long int*/ * remainder_ptr, 2146 int * overflow_ptr 2147 ) 2148 { 2149 unsigned long ald = (signed long) sfi >> (N - 1); 2150 unsigned long alo = als; 2151 unsigned int SS = als >> 31; 2152 unsigned int SD = sfi >> 31; 2153 unsigned int R1 = 1; 2154 unsigned int OV; 2155 unsigned int DBZ = als == 0 ? 1 : 0; 2156 unsigned int Q = ~(SS ^ SD) & 1; 2157 unsigned int C; 2158 unsigned int S; 2159 unsigned int i; 2160 unsigned long alt = Q ? ~als : als; 2161 2162 2163 /* 1st Loop */ 2164 2165 alo = ald + alt + Q; 2166 C = (((alt >> 31) & (ald >> 31)) 2167 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); 2168 Q = C ^ SS; 2169 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD))); 2170 S = alo >> 31; 2171 sfi = (sfi << (32-N+1)) | Q; 2172 ald = (alo << 1) | (sfi >> 31); 2173 if ((alo >> 31) ^ (ald >> 31)) 2174 { 2175 DBZ = 1; 2176 } 2177 2178 /* 2nd - N-1th Loop */ 2179 2180 for (i = 2; i < N; i++) 2181 { 2182 alt = Q ? ~als : als; 2183 alo = ald + alt + Q; 2184 C = (((alt >> 31) & (ald >> 31)) 2185 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); 2186 Q = C ^ SS; 2187 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD))); 2188 S = alo >> 31; 2189 sfi = (sfi << 1) | Q; 2190 ald = (alo << 1) | (sfi >> 31); 2191 if ((alo >> 31) ^ (ald >> 31)) 2192 { 2193 DBZ = 1; 2194 } 2195 } 2196 2197 /* Nth Loop */ 2198 alt = Q ? ~als : als; 2199 alo = ald + alt + Q; 2200 C = (((alt >> 31) & (ald >> 31)) 2201 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); 2202 Q = C ^ SS; 2203 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD))); 2204 sfi = (sfi << (32-N+1)); 2205 ald = alo; 2206 2207 /* End */ 2208 if (alo != 0) 2209 { 2210 alt = Q ? ~als : als; 2211 alo = ald + alt + Q; 2212 } 2213 R1 = R1 & ((~alo >> 31) ^ SD); 2214 if ((alo != 0) && ((Q ^ (SS ^ SD)) ^ R1)) alo = ald; 2215 if (N != 32) 2216 ald = sfi = (long) ((sfi >> 1) | (SS ^ SD) << 31) >> (32-N-1) | Q; 2217 else 2218 ald = sfi = sfi | Q; 2219 2220 OV = DBZ | ((alo == 0) ? 0 : R1); 2221 2222 * remainder_ptr = alo; 2223 2224 /* Adj */ 2225 if (((alo != 0) && ((SS ^ SD) ^ R1)) 2226 || ((alo == 0) && (SS ^ R1))) 2227 alo = ald + 1; 2228 else 2229 alo = ald; 2230 2231 OV = (DBZ | R1) ? OV : ((alo >> 31) & (~ald >> 31)); 2232 2233 * quotient_ptr = alo; 2234 * overflow_ptr = OV; 2235 } 2236 2237 /* sdivun imm5, reg1, reg2, reg3 */ 2238 int 2239 OP_1C207E0 (void) 2240 { 2241 unsigned32 /*unsigned long int*/ quotient; 2242 unsigned32 /*unsigned long int*/ remainder; 2243 unsigned long int divide_by; 2244 unsigned long int divide_this; 2245 int overflow = 0; 2246 unsigned int imm5; 2247 2248 trace_input ("sdivun", OP_IMM_REG_REG_REG, 0); 2249 2250 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17); 2251 2252 divide_by = State.regs[ OP[0] ]; 2253 divide_this = State.regs[ OP[1] ] << imm5; 2254 2255 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); 2256 2257 State.regs[ OP[1] ] = quotient; 2258 State.regs[ OP[2] >> 11 ] = remainder; 2259 2260 /* Set condition codes. */ 2261 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 2262 2263 if (overflow) PSW |= PSW_OV; 2264 if (quotient == 0) PSW |= PSW_Z; 2265 if (quotient & 0x80000000) PSW |= PSW_S; 2266 2267 trace_output (OP_IMM_REG_REG_REG); 2268 2269 return 4; 2270 } 2271 2272 /* sdivn imm5, reg1, reg2, reg3 */ 2273 int 2274 OP_1C007E0 (void) 2275 { 2276 signed32 /*signed long int*/ quotient; 2277 signed32 /*signed long int*/ remainder; 2278 signed long int divide_by; 2279 signed long int divide_this; 2280 int overflow = 0; 2281 unsigned int imm5; 2282 2283 trace_input ("sdivn", OP_IMM_REG_REG_REG, 0); 2284 2285 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17); 2286 2287 divide_by = (signed32) State.regs[ OP[0] ]; 2288 divide_this = (signed32) (State.regs[ OP[1] ] << imm5); 2289 2290 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); 2291 2292 State.regs[ OP[1] ] = quotient; 2293 State.regs[ OP[2] >> 11 ] = remainder; 2294 2295 /* Set condition codes. */ 2296 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 2297 2298 if (overflow) PSW |= PSW_OV; 2299 if (quotient == 0) PSW |= PSW_Z; 2300 if (quotient < 0) PSW |= PSW_S; 2301 2302 trace_output (OP_IMM_REG_REG_REG); 2303 2304 return 4; 2305 } 2306 2307 /* sdivhun imm5, reg1, reg2, reg3 */ 2308 int 2309 OP_18207E0 (void) 2310 { 2311 unsigned32 /*unsigned long int*/ quotient; 2312 unsigned32 /*unsigned long int*/ remainder; 2313 unsigned long int divide_by; 2314 unsigned long int divide_this; 2315 int overflow = 0; 2316 unsigned int imm5; 2317 2318 trace_input ("sdivhun", OP_IMM_REG_REG_REG, 0); 2319 2320 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17); 2321 2322 divide_by = State.regs[ OP[0] ] & 0xffff; 2323 divide_this = State.regs[ OP[1] ] << imm5; 2324 2325 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); 2326 2327 State.regs[ OP[1] ] = quotient; 2328 State.regs[ OP[2] >> 11 ] = remainder; 2329 2330 /* Set condition codes. */ 2331 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 2332 2333 if (overflow) PSW |= PSW_OV; 2334 if (quotient == 0) PSW |= PSW_Z; 2335 if (quotient & 0x80000000) PSW |= PSW_S; 2336 2337 trace_output (OP_IMM_REG_REG_REG); 2338 2339 return 4; 2340 } 2341 2342 /* sdivhn imm5, reg1, reg2, reg3 */ 2343 int 2344 OP_18007E0 (void) 2345 { 2346 signed32 /*signed long int*/ quotient; 2347 signed32 /*signed long int*/ remainder; 2348 signed long int divide_by; 2349 signed long int divide_this; 2350 int overflow = 0; 2351 unsigned int imm5; 2352 2353 trace_input ("sdivhn", OP_IMM_REG_REG_REG, 0); 2354 2355 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17); 2356 2357 divide_by = EXTEND16 (State.regs[ OP[0] ]); 2358 divide_this = (signed32) (State.regs[ OP[1] ] << imm5); 2359 2360 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); 2361 2362 State.regs[ OP[1] ] = quotient; 2363 State.regs[ OP[2] >> 11 ] = remainder; 2364 2365 /* Set condition codes. */ 2366 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 2367 2368 if (overflow) PSW |= PSW_OV; 2369 if (quotient == 0) PSW |= PSW_Z; 2370 if (quotient < 0) PSW |= PSW_S; 2371 2372 trace_output (OP_IMM_REG_REG_REG); 2373 2374 return 4; 2375 } 2376 2377 /* divu reg1, reg2, reg3 */ 2378 int 2379 OP_2C207E0 (void) 2380 { 2381 unsigned long int quotient; 2382 unsigned long int remainder; 2383 unsigned long int divide_by; 2384 unsigned long int divide_this; 2385 int overflow = 0; 2386 2387 trace_input ("divu", OP_REG_REG_REG, 0); 2388 2389 /* Compute the result. */ 2390 2391 divide_by = State.regs[ OP[0] ]; 2392 divide_this = State.regs[ OP[1] ]; 2393 2394 if (divide_by == 0) 2395 { 2396 PSW |= PSW_OV; 2397 } 2398 else 2399 { 2400 State.regs[ OP[1] ] = quotient = divide_this / divide_by; 2401 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by; 2402 2403 /* Set condition codes. */ 2404 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 2405 2406 if (overflow) PSW |= PSW_OV; 2407 if (quotient == 0) PSW |= PSW_Z; 2408 if (quotient & 0x80000000) PSW |= PSW_S; 2409 } 2410 2411 trace_output (OP_REG_REG_REG); 2412 2413 return 4; 2414 } 2415 2416 /* div reg1, reg2, reg3 */ 2417 int 2418 OP_2C007E0 (void) 2419 { 2420 signed long int quotient; 2421 signed long int remainder; 2422 signed long int divide_by; 2423 signed long int divide_this; 2424 2425 trace_input ("div", OP_REG_REG_REG, 0); 2426 2427 /* Compute the result. */ 2428 2429 divide_by = (signed32) State.regs[ OP[0] ]; 2430 divide_this = State.regs[ OP[1] ]; 2431 2432 if (divide_by == 0) 2433 { 2434 PSW |= PSW_OV; 2435 } 2436 else if (divide_by == -1 && divide_this == (1L << 31)) 2437 { 2438 PSW &= ~PSW_Z; 2439 PSW |= PSW_OV | PSW_S; 2440 State.regs[ OP[1] ] = (1 << 31); 2441 State.regs[ OP[2] >> 11 ] = 0; 2442 } 2443 else 2444 { 2445 divide_this = (signed32) divide_this; 2446 State.regs[ OP[1] ] = quotient = divide_this / divide_by; 2447 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by; 2448 2449 /* Set condition codes. */ 2450 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 2451 2452 if (quotient == 0) PSW |= PSW_Z; 2453 if (quotient < 0) PSW |= PSW_S; 2454 } 2455 2456 trace_output (OP_REG_REG_REG); 2457 2458 return 4; 2459 } 2460 2461 /* divhu reg1, reg2, reg3 */ 2462 int 2463 OP_28207E0 (void) 2464 { 2465 unsigned long int quotient; 2466 unsigned long int remainder; 2467 unsigned long int divide_by; 2468 unsigned long int divide_this; 2469 int overflow = 0; 2470 2471 trace_input ("divhu", OP_REG_REG_REG, 0); 2472 2473 /* Compute the result. */ 2474 2475 divide_by = State.regs[ OP[0] ] & 0xffff; 2476 divide_this = State.regs[ OP[1] ]; 2477 2478 if (divide_by == 0) 2479 { 2480 PSW |= PSW_OV; 2481 } 2482 else 2483 { 2484 State.regs[ OP[1] ] = quotient = divide_this / divide_by; 2485 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by; 2486 2487 /* Set condition codes. */ 2488 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 2489 2490 if (overflow) PSW |= PSW_OV; 2491 if (quotient == 0) PSW |= PSW_Z; 2492 if (quotient & 0x80000000) PSW |= PSW_S; 2493 } 2494 2495 trace_output (OP_REG_REG_REG); 2496 2497 return 4; 2498 } 2499 2500 /* divh reg1, reg2, reg3 */ 2501 int 2502 OP_28007E0 (void) 2503 { 2504 signed long int quotient; 2505 signed long int remainder; 2506 signed long int divide_by; 2507 signed long int divide_this; 2508 int overflow = 0; 2509 2510 trace_input ("divh", OP_REG_REG_REG, 0); 2511 2512 /* Compute the result. */ 2513 2514 divide_by = EXTEND16 (State.regs[ OP[0] ]); 2515 divide_this = State.regs[ OP[1] ]; 2516 2517 if (divide_by == 0) 2518 { 2519 PSW |= PSW_OV; 2520 } 2521 else if (divide_by == -1 && divide_this == (1L << 31)) 2522 { 2523 PSW &= ~PSW_Z; 2524 PSW |= PSW_OV | PSW_S; 2525 State.regs[ OP[1] ] = (1 << 31); 2526 State.regs[ OP[2] >> 11 ] = 0; 2527 } 2528 else 2529 { 2530 divide_this = (signed32) divide_this; 2531 State.regs[ OP[1] ] = quotient = divide_this / divide_by; 2532 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by; 2533 2534 /* Set condition codes. */ 2535 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 2536 2537 if (quotient == 0) PSW |= PSW_Z; 2538 if (quotient < 0) PSW |= PSW_S; 2539 } 2540 2541 trace_output (OP_REG_REG_REG); 2542 2543 return 4; 2544 } 2545 2546 /* mulu imm9, reg2, reg3 */ 2547 int 2548 OP_24207E0 (void) 2549 { 2550 trace_input ("mulu", OP_IMM_REG_REG, 0); 2551 2552 Multiply64 (0, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0)); 2553 2554 trace_output (OP_IMM_REG_REG); 2555 2556 return 4; 2557 } 2558 2559 /* mul imm9, reg2, reg3 */ 2560 int 2561 OP_24007E0 (void) 2562 { 2563 trace_input ("mul", OP_IMM_REG_REG, 0); 2564 2565 Multiply64 (1, SEXT9 ((OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0))); 2566 2567 trace_output (OP_IMM_REG_REG); 2568 2569 return 4; 2570 } 2571 2572 /* ld.hu */ 2573 int 2574 OP_107E0 (void) 2575 { 2576 int adr; 2577 2578 trace_input ("ld.hu", OP_LOAD32, 2); 2579 2580 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1); 2581 adr &= ~0x1; 2582 2583 State.regs[ OP[1] ] = load_mem (adr, 2); 2584 2585 trace_output (OP_LOAD32); 2586 2587 return 4; 2588 } 2589 2590 2591 /* ld.bu */ 2592 int 2593 OP_10780 (void) 2594 { 2595 int adr; 2596 2597 trace_input ("ld.bu", OP_LOAD32, 1); 2598 2599 adr = (State.regs[ OP[0] ] 2600 + (EXTEND16 (OP[2] & ~1) | ((OP[3] >> 5) & 1))); 2601 2602 State.regs[ OP[1] ] = load_mem (adr, 1); 2603 2604 trace_output (OP_LOAD32); 2605 2606 return 4; 2607 } 2608 2609 /* prepare list12, imm5, imm32 */ 2610 int 2611 OP_1B0780 (void) 2612 { 2613 int i; 2614 2615 trace_input ("prepare", OP_PUSHPOP1, 0); 2616 2617 /* Store the registers with lower number registers being placed at higher addresses. */ 2618 for (i = 0; i < 12; i++) 2619 if ((OP[3] & (1 << type1_regs[ i ]))) 2620 { 2621 SP -= 4; 2622 store_mem (SP, 4, State.regs[ 20 + i ]); 2623 } 2624 2625 SP -= (OP[3] & 0x3e) << 1; 2626 2627 EP = load_mem (PC + 4, 4); 2628 2629 trace_output (OP_PUSHPOP1); 2630 2631 return 8; 2632 } 2633 2634 /* prepare list12, imm5, imm16-32 */ 2635 int 2636 OP_130780 (void) 2637 { 2638 int i; 2639 2640 trace_input ("prepare", OP_PUSHPOP1, 0); 2641 2642 /* Store the registers with lower number registers being placed at higher addresses. */ 2643 for (i = 0; i < 12; i++) 2644 if ((OP[3] & (1 << type1_regs[ i ]))) 2645 { 2646 SP -= 4; 2647 store_mem (SP, 4, State.regs[ 20 + i ]); 2648 } 2649 2650 SP -= (OP[3] & 0x3e) << 1; 2651 2652 EP = load_mem (PC + 4, 2) << 16; 2653 2654 trace_output (OP_PUSHPOP1); 2655 2656 return 6; 2657 } 2658 2659 /* prepare list12, imm5, imm16 */ 2660 int 2661 OP_B0780 (void) 2662 { 2663 int i; 2664 2665 trace_input ("prepare", OP_PUSHPOP1, 0); 2666 2667 /* Store the registers with lower number registers being placed at higher addresses. */ 2668 for (i = 0; i < 12; i++) 2669 if ((OP[3] & (1 << type1_regs[ i ]))) 2670 { 2671 SP -= 4; 2672 store_mem (SP, 4, State.regs[ 20 + i ]); 2673 } 2674 2675 SP -= (OP[3] & 0x3e) << 1; 2676 2677 EP = EXTEND16 (load_mem (PC + 4, 2)); 2678 2679 trace_output (OP_PUSHPOP1); 2680 2681 return 6; 2682 } 2683 2684 /* prepare list12, imm5, sp */ 2685 int 2686 OP_30780 (void) 2687 { 2688 int i; 2689 2690 trace_input ("prepare", OP_PUSHPOP1, 0); 2691 2692 /* Store the registers with lower number registers being placed at higher addresses. */ 2693 for (i = 0; i < 12; i++) 2694 if ((OP[3] & (1 << type1_regs[ i ]))) 2695 { 2696 SP -= 4; 2697 store_mem (SP, 4, State.regs[ 20 + i ]); 2698 } 2699 2700 SP -= (OP[3] & 0x3e) << 1; 2701 2702 EP = SP; 2703 2704 trace_output (OP_PUSHPOP1); 2705 2706 return 4; 2707 } 2708 2709 /* mul reg1, reg2, reg3 */ 2710 int 2711 OP_22007E0 (void) 2712 { 2713 trace_input ("mul", OP_REG_REG_REG, 0); 2714 2715 Multiply64 (1, State.regs[ OP[0] ]); 2716 2717 trace_output (OP_REG_REG_REG); 2718 2719 return 4; 2720 } 2721 2722 /* popmh list18 */ 2723 int 2724 OP_307F0 (void) 2725 { 2726 int i; 2727 2728 trace_input ("popmh", OP_PUSHPOP2, 0); 2729 2730 if (OP[3] & (1 << 19)) 2731 { 2732 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0)) 2733 { 2734 FEPSW = load_mem ( SP & ~ 3, 4); 2735 FEPC = load_mem ((SP + 4) & ~ 3, 4); 2736 } 2737 else 2738 { 2739 EIPSW = load_mem ( SP & ~ 3, 4); 2740 EIPC = load_mem ((SP + 4) & ~ 3, 4); 2741 } 2742 2743 SP += 8; 2744 } 2745 2746 /* Load the registers with lower number registers being retrieved from higher addresses. */ 2747 for (i = 16; i--;) 2748 if ((OP[3] & (1 << type2_regs[ i ]))) 2749 { 2750 State.regs[ i + 16 ] = load_mem (SP & ~ 3, 4); 2751 SP += 4; 2752 } 2753 2754 trace_output (OP_PUSHPOP2); 2755 2756 return 4; 2757 } 2758 2759 /* popml lsit18 */ 2760 int 2761 OP_107F0 (void) 2762 { 2763 int i; 2764 2765 trace_input ("popml", OP_PUSHPOP3, 0); 2766 2767 if (OP[3] & (1 << 19)) 2768 { 2769 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0)) 2770 { 2771 FEPSW = load_mem ( SP & ~ 3, 4); 2772 FEPC = load_mem ((SP + 4) & ~ 3, 4); 2773 } 2774 else 2775 { 2776 EIPSW = load_mem ( SP & ~ 3, 4); 2777 EIPC = load_mem ((SP + 4) & ~ 3, 4); 2778 } 2779 2780 SP += 8; 2781 } 2782 2783 if (OP[3] & (1 << 3)) 2784 { 2785 PSW = load_mem (SP & ~ 3, 4); 2786 SP += 4; 2787 } 2788 2789 /* Load the registers with lower number registers being retrieved from higher addresses. */ 2790 for (i = 15; i--;) 2791 if ((OP[3] & (1 << type3_regs[ i ]))) 2792 { 2793 State.regs[ i + 1 ] = load_mem (SP & ~ 3, 4); 2794 SP += 4; 2795 } 2796 2797 trace_output (OP_PUSHPOP2); 2798 2799 return 4; 2800 } 2801 2802 /* pushmh list18 */ 2803 int 2804 OP_307E0 (void) 2805 { 2806 int i; 2807 2808 trace_input ("pushmh", OP_PUSHPOP2, 0); 2809 2810 /* Store the registers with lower number registers being placed at higher addresses. */ 2811 for (i = 0; i < 16; i++) 2812 if ((OP[3] & (1 << type2_regs[ i ]))) 2813 { 2814 SP -= 4; 2815 store_mem (SP & ~ 3, 4, State.regs[ i + 16 ]); 2816 } 2817 2818 if (OP[3] & (1 << 19)) 2819 { 2820 SP -= 8; 2821 2822 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0)) 2823 { 2824 store_mem ((SP + 4) & ~ 3, 4, FEPC); 2825 store_mem ( SP & ~ 3, 4, FEPSW); 2826 } 2827 else 2828 { 2829 store_mem ((SP + 4) & ~ 3, 4, EIPC); 2830 store_mem ( SP & ~ 3, 4, EIPSW); 2831 } 2832 } 2833 2834 trace_output (OP_PUSHPOP2); 2835 2836 return 4; 2837 } 2838 2839 /* V850E2R FPU functions */ 2840 /* 2841 sim_fpu_status_invalid_snan = 1, -V--- (sim spec.) 2842 sim_fpu_status_invalid_qnan = 2, ----- (sim spec.) 2843 sim_fpu_status_invalid_isi = 4, (inf - inf) -V--- 2844 sim_fpu_status_invalid_idi = 8, (inf / inf) -V--- 2845 sim_fpu_status_invalid_zdz = 16, (0 / 0) -V--- 2846 sim_fpu_status_invalid_imz = 32, (inf * 0) -V--- 2847 sim_fpu_status_invalid_cvi = 64, convert to integer -V--- 2848 sim_fpu_status_invalid_div0 = 128, (X / 0) --Z-- 2849 sim_fpu_status_invalid_cmp = 256, compare ----- (sim spec.) 2850 sim_fpu_status_invalid_sqrt = 512, -V--- 2851 sim_fpu_status_rounded = 1024, I---- 2852 sim_fpu_status_inexact = 2048, I---- (sim spec.) 2853 sim_fpu_status_overflow = 4096, I--O- 2854 sim_fpu_status_underflow = 8192, I---U 2855 sim_fpu_status_denorm = 16384, ----U (sim spec.) 2856 */ 2857 2858 void 2859 update_fpsr (SIM_DESC sd, sim_fpu_status status, unsigned int mask, unsigned int double_op_p) 2860 { 2861 unsigned int fpsr = FPSR & mask; 2862 2863 unsigned int flags = 0; 2864 2865 if (fpsr & FPSR_XEI 2866 && ((status & (sim_fpu_status_rounded 2867 | sim_fpu_status_overflow 2868 | sim_fpu_status_inexact)) 2869 || (status & sim_fpu_status_underflow 2870 && (fpsr & (FPSR_XEU | FPSR_XEI)) == 0 2871 && fpsr & FPSR_FS))) 2872 { 2873 flags |= FPSR_XCI | FPSR_XPI; 2874 } 2875 2876 if (fpsr & FPSR_XEV 2877 && (status & (sim_fpu_status_invalid_isi 2878 | sim_fpu_status_invalid_imz 2879 | sim_fpu_status_invalid_zdz 2880 | sim_fpu_status_invalid_idi 2881 | sim_fpu_status_invalid_cvi 2882 | sim_fpu_status_invalid_sqrt 2883 | sim_fpu_status_invalid_snan))) 2884 { 2885 flags |= FPSR_XCV | FPSR_XPV; 2886 } 2887 2888 if (fpsr & FPSR_XEZ 2889 && (status & sim_fpu_status_invalid_div0)) 2890 { 2891 flags |= FPSR_XCV | FPSR_XPV; 2892 } 2893 2894 if (fpsr & FPSR_XEO 2895 && (status & sim_fpu_status_overflow)) 2896 { 2897 flags |= FPSR_XCO | FPSR_XPO; 2898 } 2899 2900 if (((fpsr & FPSR_XEU) || (fpsr & FPSR_FS) == 0) 2901 && (status & (sim_fpu_status_underflow 2902 | sim_fpu_status_denorm))) 2903 { 2904 flags |= FPSR_XCU | FPSR_XPU; 2905 } 2906 2907 if (flags) 2908 { 2909 FPSR &= ~FPSR_XC; 2910 FPSR |= flags; 2911 2912 SignalExceptionFPE (sd, double_op_p); 2913 } 2914 } 2915 2916 /* Exception. */ 2917 2918 void 2919 SignalException (SIM_DESC sd) 2920 { 2921 if (MPM & MPM_AUE) 2922 { 2923 PSW = PSW & ~(PSW_NPV | PSW_DMP | PSW_IMP); 2924 } 2925 } 2926 2927 void 2928 SignalExceptionFPE (SIM_DESC sd, unsigned int double_op_p) 2929 { 2930 if (((PSW & (PSW_NP|PSW_ID)) == 0) 2931 || !(FPSR & (double_op_p ? FPSR_DEM : FPSR_SEM))) 2932 { 2933 EIPC = PC; 2934 EIPSW = PSW; 2935 EIIC = (FPSR & (double_op_p ? FPSR_DEM : FPSR_SEM)) 2936 ? 0x71 : 0x72; 2937 PSW |= (PSW_EP | PSW_ID); 2938 PC = 0x70; 2939 2940 SignalException (sd); 2941 } 2942 } 2943 2944 void 2945 check_invalid_snan (SIM_DESC sd, sim_fpu_status status, unsigned int double_op_p) 2946 { 2947 if ((FPSR & FPSR_XEI) 2948 && (status & sim_fpu_status_invalid_snan)) 2949 { 2950 FPSR &= ~FPSR_XC; 2951 FPSR |= FPSR_XCV; 2952 FPSR |= FPSR_XPV; 2953 SignalExceptionFPE (sd, double_op_p); 2954 } 2955 } 2956 2957 int 2958 v850_float_compare (SIM_DESC sd, int cmp, sim_fpu wop1, sim_fpu wop2, int double_op_p) 2959 { 2960 int result = -1; 2961 2962 if (sim_fpu_is_nan (&wop1) || sim_fpu_is_nan (&wop2)) 2963 { 2964 if (cmp & 0x8) 2965 { 2966 if (FPSR & FPSR_XEV) 2967 { 2968 FPSR |= FPSR_XCV | FPSR_XPV; 2969 SignalExceptionFPE (sd, double_op_p); 2970 } 2971 } 2972 2973 switch (cmp) 2974 { 2975 case FPU_CMP_F: 2976 result = 0; 2977 break; 2978 case FPU_CMP_UN: 2979 result = 1; 2980 break; 2981 case FPU_CMP_EQ: 2982 result = 0; 2983 break; 2984 case FPU_CMP_UEQ: 2985 result = 1; 2986 break; 2987 case FPU_CMP_OLT: 2988 result = 0; 2989 break; 2990 case FPU_CMP_ULT: 2991 result = 1; 2992 break; 2993 case FPU_CMP_OLE: 2994 result = 0; 2995 break; 2996 case FPU_CMP_ULE: 2997 result = 1; 2998 break; 2999 case FPU_CMP_SF: 3000 result = 0; 3001 break; 3002 case FPU_CMP_NGLE: 3003 result = 1; 3004 break; 3005 case FPU_CMP_SEQ: 3006 result = 0; 3007 break; 3008 case FPU_CMP_NGL: 3009 result = 1; 3010 break; 3011 case FPU_CMP_LT: 3012 result = 0; 3013 break; 3014 case FPU_CMP_NGE: 3015 result = 1; 3016 break; 3017 case FPU_CMP_LE: 3018 result = 0; 3019 break; 3020 case FPU_CMP_NGT: 3021 result = 1; 3022 break; 3023 default: 3024 abort (); 3025 } 3026 } 3027 else if (sim_fpu_is_infinity (&wop1) && sim_fpu_is_infinity (&wop2) 3028 && sim_fpu_sign (&wop1) == sim_fpu_sign (&wop2)) 3029 { 3030 switch (cmp) 3031 { 3032 case FPU_CMP_F: 3033 result = 0; 3034 break; 3035 case FPU_CMP_UN: 3036 result = 0; 3037 break; 3038 case FPU_CMP_EQ: 3039 result = 1; 3040 break; 3041 case FPU_CMP_UEQ: 3042 result = 1; 3043 break; 3044 case FPU_CMP_OLT: 3045 result = 0; 3046 break; 3047 case FPU_CMP_ULT: 3048 result = 0; 3049 break; 3050 case FPU_CMP_OLE: 3051 result = 1; 3052 break; 3053 case FPU_CMP_ULE: 3054 result = 1; 3055 break; 3056 case FPU_CMP_SF: 3057 result = 0; 3058 break; 3059 case FPU_CMP_NGLE: 3060 result = 0; 3061 break; 3062 case FPU_CMP_SEQ: 3063 result = 1; 3064 break; 3065 case FPU_CMP_NGL: 3066 result = 1; 3067 break; 3068 case FPU_CMP_LT: 3069 result = 0; 3070 break; 3071 case FPU_CMP_NGE: 3072 result = 0; 3073 break; 3074 case FPU_CMP_LE: 3075 result = 1; 3076 break; 3077 case FPU_CMP_NGT: 3078 result = 1; 3079 break; 3080 default: 3081 abort (); 3082 } 3083 } 3084 else 3085 { 3086 int gt = 0,lt = 0,eq = 0, status; 3087 3088 status = sim_fpu_cmp (&wop1, &wop2); 3089 3090 switch (status) 3091 { 3092 case SIM_FPU_IS_SNAN: 3093 case SIM_FPU_IS_QNAN: 3094 abort (); 3095 break; 3096 3097 case SIM_FPU_IS_NINF: 3098 lt = 1; 3099 break; 3100 case SIM_FPU_IS_PINF: 3101 gt = 1; 3102 break; 3103 case SIM_FPU_IS_NNUMBER: 3104 lt = 1; 3105 break; 3106 case SIM_FPU_IS_PNUMBER: 3107 gt = 1; 3108 break; 3109 case SIM_FPU_IS_NDENORM: 3110 lt = 1; 3111 break; 3112 case SIM_FPU_IS_PDENORM: 3113 gt = 1; 3114 break; 3115 case SIM_FPU_IS_NZERO: 3116 case SIM_FPU_IS_PZERO: 3117 eq = 1; 3118 break; 3119 } 3120 3121 switch (cmp) 3122 { 3123 case FPU_CMP_F: 3124 result = 0; 3125 break; 3126 case FPU_CMP_UN: 3127 result = 0; 3128 break; 3129 case FPU_CMP_EQ: 3130 result = eq; 3131 break; 3132 case FPU_CMP_UEQ: 3133 result = eq; 3134 break; 3135 case FPU_CMP_OLT: 3136 result = lt; 3137 break; 3138 case FPU_CMP_ULT: 3139 result = lt; 3140 break; 3141 case FPU_CMP_OLE: 3142 result = lt || eq; 3143 break; 3144 case FPU_CMP_ULE: 3145 result = lt || eq; 3146 break; 3147 case FPU_CMP_SF: 3148 result = 0; 3149 break; 3150 case FPU_CMP_NGLE: 3151 result = 0; 3152 break; 3153 case FPU_CMP_SEQ: 3154 result = eq; 3155 break; 3156 case FPU_CMP_NGL: 3157 result = eq; 3158 break; 3159 case FPU_CMP_LT: 3160 result = lt; 3161 break; 3162 case FPU_CMP_NGE: 3163 result = lt; 3164 break; 3165 case FPU_CMP_LE: 3166 result = lt || eq; 3167 break; 3168 case FPU_CMP_NGT: 3169 result = lt || eq; 3170 break; 3171 } 3172 } 3173 3174 ASSERT (result != -1); 3175 return result; 3176 } 3177 3178 void 3179 v850_div (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p, unsigned int *op3p) 3180 { 3181 signed long int quotient; 3182 signed long int remainder; 3183 signed long int divide_by; 3184 signed long int divide_this; 3185 bfd_boolean overflow = FALSE; 3186 3187 /* Compute the result. */ 3188 divide_by = op0; 3189 divide_this = op1; 3190 3191 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31))) 3192 { 3193 overflow = TRUE; 3194 divide_by = 1; 3195 } 3196 3197 quotient = divide_this / divide_by; 3198 remainder = divide_this % divide_by; 3199 3200 /* Set condition codes. */ 3201 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 3202 3203 if (overflow) PSW |= PSW_OV; 3204 if (quotient == 0) PSW |= PSW_Z; 3205 if (quotient < 0) PSW |= PSW_S; 3206 3207 *op2p = quotient; 3208 *op3p = remainder; 3209 } 3210 3211 void 3212 v850_divu (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p, unsigned int *op3p) 3213 { 3214 unsigned long int quotient; 3215 unsigned long int remainder; 3216 unsigned long int divide_by; 3217 unsigned long int divide_this; 3218 bfd_boolean overflow = FALSE; 3219 3220 /* Compute the result. */ 3221 3222 divide_by = op0; 3223 divide_this = op1; 3224 3225 if (divide_by == 0) 3226 { 3227 overflow = TRUE; 3228 divide_by = 1; 3229 } 3230 3231 quotient = divide_this / divide_by; 3232 remainder = divide_this % divide_by; 3233 3234 /* Set condition codes. */ 3235 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 3236 3237 if (overflow) PSW |= PSW_OV; 3238 if (quotient == 0) PSW |= PSW_Z; 3239 if (quotient & 0x80000000) PSW |= PSW_S; 3240 3241 *op2p = quotient; 3242 *op3p = remainder; 3243 } 3244 3245 void 3246 v850_sar (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p) 3247 { 3248 unsigned int result, z, s, cy; 3249 3250 op0 &= 0x1f; 3251 result = (signed)op1 >> op0; 3252 3253 /* Compute the condition codes. */ 3254 z = (result == 0); 3255 s = (result & 0x80000000); 3256 cy = (op1 & (1 << (op0 - 1))); 3257 3258 /* Store the result and condition codes. */ 3259 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); 3260 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 3261 | (cy ? PSW_CY : 0)); 3262 3263 *op2p = result; 3264 } 3265 3266 void 3267 v850_shl (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p) 3268 { 3269 unsigned int result, z, s, cy; 3270 3271 op0 &= 0x1f; 3272 result = op1 << op0; 3273 3274 /* Compute the condition codes. */ 3275 z = (result == 0); 3276 s = (result & 0x80000000); 3277 cy = (op1 & (1 << (32 - op0))); 3278 3279 /* Store the result and condition codes. */ 3280 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); 3281 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 3282 | (cy ? PSW_CY : 0)); 3283 3284 *op2p = result; 3285 } 3286 3287 void 3288 v850_rotl (SIM_DESC sd, unsigned int amount, unsigned int src, unsigned int * dest) 3289 { 3290 unsigned int result, z, s, cy; 3291 3292 amount &= 0x1f; 3293 result = src << amount; 3294 result |= src >> (32 - amount); 3295 3296 /* Compute the condition codes. */ 3297 z = (result == 0); 3298 s = (result & 0x80000000); 3299 cy = ! (result & 1); 3300 3301 /* Store the result and condition codes. */ 3302 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); 3303 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 3304 | (cy ? PSW_CY : 0)); 3305 3306 * dest = result; 3307 } 3308 3309 void 3310 v850_bins (SIM_DESC sd, unsigned int source, unsigned int lsb, unsigned int msb, 3311 unsigned int * dest) 3312 { 3313 unsigned int mask; 3314 unsigned int result, pos, width; 3315 unsigned int z, s; 3316 3317 pos = lsb; 3318 width = (msb - lsb) + 1; 3319 3320 mask = ~ (-(1 << width)); 3321 source &= mask; 3322 mask <<= pos; 3323 result = (* dest) & ~ mask; 3324 result |= source << pos; 3325 3326 /* Compute the condition codes. */ 3327 z = (result == 0); 3328 s = result & 0x80000000; 3329 3330 /* Store the result and condition codes. */ 3331 PSW &= ~(PSW_Z | PSW_S | PSW_OV ); 3332 PSW |= (z ? PSW_Z : 0) | (s ? PSW_S : 0); 3333 3334 * dest = result; 3335 } 3336 3337 void 3338 v850_shr (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p) 3339 { 3340 unsigned int result, z, s, cy; 3341 3342 op0 &= 0x1f; 3343 result = op1 >> op0; 3344 3345 /* Compute the condition codes. */ 3346 z = (result == 0); 3347 s = (result & 0x80000000); 3348 cy = (op1 & (1 << (op0 - 1))); 3349 3350 /* Store the result and condition codes. */ 3351 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); 3352 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 3353 | (cy ? PSW_CY : 0)); 3354 3355 *op2p = result; 3356 } 3357 3358 void 3359 v850_satadd (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p) 3360 { 3361 unsigned int result, z, s, cy, ov, sat; 3362 3363 result = op0 + op1; 3364 3365 /* Compute the condition codes. */ 3366 z = (result == 0); 3367 s = (result & 0x80000000); 3368 cy = (result < op0 || result < op1); 3369 ov = ((op0 & 0x80000000) == (op1 & 0x80000000) 3370 && (op0 & 0x80000000) != (result & 0x80000000)); 3371 sat = ov; 3372 3373 /* Store the result and condition codes. */ 3374 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 3375 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 3376 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) 3377 | (sat ? PSW_SAT : 0)); 3378 3379 /* Handle saturated results. */ 3380 if (sat && s) 3381 { 3382 result = 0x7fffffff; 3383 PSW &= ~PSW_S; 3384 } 3385 else if (sat) 3386 { 3387 result = 0x80000000; 3388 PSW |= PSW_S; 3389 } 3390 3391 *op2p = result; 3392 } 3393 3394 void 3395 v850_satsub (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p) 3396 { 3397 unsigned int result, z, s, cy, ov, sat; 3398 3399 /* Compute the result. */ 3400 result = op1 - op0; 3401 3402 /* Compute the condition codes. */ 3403 z = (result == 0); 3404 s = (result & 0x80000000); 3405 cy = (op1 < op0); 3406 ov = ((op1 & 0x80000000) != (op0 & 0x80000000) 3407 && (op1 & 0x80000000) != (result & 0x80000000)); 3408 sat = ov; 3409 3410 /* Store the result and condition codes. */ 3411 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 3412 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 3413 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) 3414 | (sat ? PSW_SAT : 0)); 3415 3416 /* Handle saturated results. */ 3417 if (sat && s) 3418 { 3419 result = 0x7fffffff; 3420 PSW &= ~PSW_S; 3421 } 3422 else if (sat) 3423 { 3424 result = 0x80000000; 3425 PSW |= PSW_S; 3426 } 3427 3428 *op2p = result; 3429 } 3430 3431 unsigned32 3432 load_data_mem (SIM_DESC sd, 3433 SIM_ADDR addr, 3434 int len) 3435 { 3436 uint32 data; 3437 3438 switch (len) 3439 { 3440 case 1: 3441 data = sim_core_read_unaligned_1 (STATE_CPU (sd, 0), 3442 PC, read_map, addr); 3443 break; 3444 case 2: 3445 data = sim_core_read_unaligned_2 (STATE_CPU (sd, 0), 3446 PC, read_map, addr); 3447 break; 3448 case 4: 3449 data = sim_core_read_unaligned_4 (STATE_CPU (sd, 0), 3450 PC, read_map, addr); 3451 break; 3452 default: 3453 abort (); 3454 } 3455 return data; 3456 } 3457 3458 void 3459 store_data_mem (SIM_DESC sd, 3460 SIM_ADDR addr, 3461 int len, 3462 unsigned32 data) 3463 { 3464 switch (len) 3465 { 3466 case 1: 3467 store_mem (addr, 1, data); 3468 break; 3469 case 2: 3470 store_mem (addr, 2, data); 3471 break; 3472 case 4: 3473 store_mem (addr, 4, data); 3474 break; 3475 default: 3476 abort (); 3477 } 3478 } 3479 3480 int 3481 mpu_load_mem_test (SIM_DESC sd, unsigned int addr, int size, int base_reg) 3482 { 3483 int result = 1; 3484 3485 if (PSW & PSW_DMP) 3486 { 3487 if (IPE0 && addr >= IPA2ADDR (IPA0L) && addr <= IPA2ADDR (IPA0L) && IPR0) 3488 { 3489 /* text area */ 3490 } 3491 else if (IPE1 && addr >= IPA2ADDR (IPA1L) && addr <= IPA2ADDR (IPA1L) && IPR1) 3492 { 3493 /* text area */ 3494 } 3495 else if (IPE2 && addr >= IPA2ADDR (IPA2L) && addr <= IPA2ADDR (IPA2L) && IPR2) 3496 { 3497 /* text area */ 3498 } 3499 else if (IPE3 && addr >= IPA2ADDR (IPA3L) && addr <= IPA2ADDR (IPA3L) && IPR3) 3500 { 3501 /* text area */ 3502 } 3503 else if (addr >= PPA2ADDR (PPA & ~PPM) && addr <= DPA2ADDR (PPA | PPM)) 3504 { 3505 /* preifarallel area */ 3506 } 3507 else if (addr >= PPA2ADDR (SPAL) && addr <= DPA2ADDR (SPAU)) 3508 { 3509 /* stack area */ 3510 } 3511 else if (DPE0 && addr >= DPA2ADDR (DPA0L) && addr <= DPA2ADDR (DPA0L) && DPR0 3512 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1)) 3513 { 3514 /* data area */ 3515 } 3516 else if (DPE1 && addr >= DPA2ADDR (DPA1L) && addr <= DPA2ADDR (DPA1L) && DPR1 3517 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1)) 3518 { 3519 /* data area */ 3520 } 3521 else if (DPE2 && addr >= DPA2ADDR (DPA2L) && addr <= DPA2ADDR (DPA2L) && DPR2 3522 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1)) 3523 { 3524 /* data area */ 3525 } 3526 else if (DPE3 && addr >= DPA2ADDR (DPA3L) && addr <= DPA2ADDR (DPA3L) && DPR3 3527 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1)) 3528 { 3529 /* data area */ 3530 } 3531 else 3532 { 3533 VMECR &= ~(VMECR_VMW | VMECR_VMX); 3534 VMECR |= VMECR_VMR; 3535 VMADR = addr; 3536 VMTID = TID; 3537 FEIC = 0x431; 3538 3539 PC = 0x30; 3540 3541 SignalException (sd); 3542 result = 0; 3543 } 3544 } 3545 3546 return result; 3547 } 3548 3549 int 3550 mpu_store_mem_test (SIM_DESC sd, unsigned int addr, int size, int base_reg) 3551 { 3552 int result = 1; 3553 3554 if (PSW & PSW_DMP) 3555 { 3556 if (addr >= PPA2ADDR (PPA & ~PPM) && addr <= DPA2ADDR (PPA | PPM)) 3557 { 3558 /* preifarallel area */ 3559 } 3560 else if (addr >= PPA2ADDR (SPAL) && addr <= DPA2ADDR (SPAU)) 3561 { 3562 /* stack area */ 3563 } 3564 else if (DPE0 && addr >= DPA2ADDR (DPA0L) && addr <= DPA2ADDR (DPA0L) && DPW0 3565 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1)) 3566 { 3567 /* data area */ 3568 } 3569 else if (DPE1 && addr >= DPA2ADDR (DPA1L) && addr <= DPA2ADDR (DPA1L) && DPW1 3570 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1)) 3571 { 3572 /* data area */ 3573 } 3574 else if (DPE2 && addr >= DPA2ADDR (DPA2L) && addr <= DPA2ADDR (DPA2L) && DPW2 3575 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1)) 3576 { 3577 /* data area */ 3578 } 3579 else if (DPE3 && addr >= DPA2ADDR (DPA3L) && addr <= DPA2ADDR (DPA3L) && DPW3 3580 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1)) 3581 { 3582 /* data area */ 3583 } 3584 else 3585 { 3586 if (addr >= PPA2ADDR (PPA & ~PPM) && addr <= DPA2ADDR (PPA | PPM)) 3587 { 3588 FEIC = 0x432; 3589 VPTID = TID; 3590 VPADR = PC; 3591 #ifdef NOT_YET 3592 VIP_PP; 3593 VPECR; 3594 #endif 3595 } 3596 else 3597 { 3598 FEIC = 0x431; 3599 VMTID = TID; 3600 VMADR = VMECR; 3601 VMECR &= ~(VMECR_VMW | VMECR_VMX); 3602 VMECR |= VMECR_VMR; 3603 PC = 0x30; 3604 } 3605 result = 0; 3606 } 3607 } 3608 3609 return result; 3610 } 3611 3612