1 /* This must come before any other includes. */ 2 #include "defs.h" 3 4 #include "sim-main.h" 5 #include "sim-options.h" 6 #include "v850-sim.h" 7 #include "sim-assert.h" 8 #include "itable.h" 9 10 #include <stdlib.h> 11 #include <string.h> 12 13 #include "bfd.h" 14 15 #include "target-newlib-syscall.h" 16 17 static const char * get_insn_name (sim_cpu *, int); 18 19 /* For compatibility. */ 20 SIM_DESC simulator; 21 22 /* V850 interrupt model. */ 23 24 enum interrupt_type 25 { 26 int_reset, 27 int_nmi, 28 int_intov1, 29 int_intp10, 30 int_intp11, 31 int_intp12, 32 int_intp13, 33 int_intcm4, 34 num_int_types 35 }; 36 37 const char *interrupt_names[] = 38 { 39 "reset", 40 "nmi", 41 "intov1", 42 "intp10", 43 "intp11", 44 "intp12", 45 "intp13", 46 "intcm4", 47 NULL 48 }; 49 50 static void 51 do_interrupt (SIM_DESC sd, void *data) 52 { 53 sim_cpu *cpu = STATE_CPU (sd, 0); 54 struct v850_sim_cpu *v850_cpu = V850_SIM_CPU (cpu); 55 const char **interrupt_name = (const char**)data; 56 enum interrupt_type inttype; 57 inttype = (interrupt_name - STATE_WATCHPOINTS (sd)->interrupt_names); 58 59 /* For a hardware reset, drop everything and jump to the start 60 address */ 61 if (inttype == int_reset) 62 { 63 PC = 0; 64 PSW = 0x20; 65 ECR = 0; 66 sim_engine_restart (sd, NULL, NULL, NULL_CIA); 67 } 68 69 /* Deliver an NMI when allowed */ 70 if (inttype == int_nmi) 71 { 72 if (PSW & PSW_NP) 73 { 74 /* We're already working on an NMI, so this one must wait 75 around until the previous one is done. The processor 76 ignores subsequent NMIs, so we don't need to count them. 77 Just keep re-scheduling a single NMI until it manages to 78 be delivered */ 79 if (v850_cpu->pending_nmi != NULL) 80 sim_events_deschedule (sd, v850_cpu->pending_nmi); 81 v850_cpu->pending_nmi = 82 sim_events_schedule (sd, 1, do_interrupt, data); 83 return; 84 } 85 else 86 { 87 /* NMI can be delivered. Do not deschedule pending_nmi as 88 that, if still in the event queue, is a second NMI that 89 needs to be delivered later. */ 90 FEPC = PC; 91 FEPSW = PSW; 92 /* Set the FECC part of the ECR. */ 93 ECR &= 0x0000ffff; 94 ECR |= 0x10; 95 PSW |= PSW_NP; 96 PSW &= ~PSW_EP; 97 PSW |= PSW_ID; 98 PC = 0x10; 99 sim_engine_restart (sd, NULL, NULL, NULL_CIA); 100 } 101 } 102 103 /* deliver maskable interrupt when allowed */ 104 if (inttype > int_nmi && inttype < num_int_types) 105 { 106 if ((PSW & PSW_NP) || (PSW & PSW_ID)) 107 { 108 /* Can't deliver this interrupt, reschedule it for later */ 109 sim_events_schedule (sd, 1, do_interrupt, data); 110 return; 111 } 112 else 113 { 114 /* save context */ 115 EIPC = PC; 116 EIPSW = PSW; 117 /* Disable further interrupts. */ 118 PSW |= PSW_ID; 119 /* Indicate that we're doing interrupt not exception processing. */ 120 PSW &= ~PSW_EP; 121 /* Clear the EICC part of the ECR, will set below. */ 122 ECR &= 0xffff0000; 123 switch (inttype) 124 { 125 case int_intov1: 126 PC = 0x80; 127 ECR |= 0x80; 128 break; 129 case int_intp10: 130 PC = 0x90; 131 ECR |= 0x90; 132 break; 133 case int_intp11: 134 PC = 0xa0; 135 ECR |= 0xa0; 136 break; 137 case int_intp12: 138 PC = 0xb0; 139 ECR |= 0xb0; 140 break; 141 case int_intp13: 142 PC = 0xc0; 143 ECR |= 0xc0; 144 break; 145 case int_intcm4: 146 PC = 0xd0; 147 ECR |= 0xd0; 148 break; 149 default: 150 /* Should never be possible. */ 151 sim_engine_abort (sd, NULL, NULL_CIA, 152 "do_interrupt - internal error - bad switch"); 153 break; 154 } 155 } 156 sim_engine_restart (sd, NULL, NULL, NULL_CIA); 157 } 158 159 /* some other interrupt? */ 160 sim_engine_abort (sd, NULL, NULL_CIA, 161 "do_interrupt - internal error - interrupt %d unknown", 162 inttype); 163 } 164 165 /* Return name of an insn, used by insn profiling. */ 166 167 static const char * 168 get_insn_name (sim_cpu *cpu, int i) 169 { 170 return itable[i].name; 171 } 172 173 /* These default values correspond to expected usage for the chip. */ 174 175 uint32_t OP[4]; 176 177 static sim_cia 178 v850_pc_get (sim_cpu *cpu) 179 { 180 return PC; 181 } 182 183 static void 184 v850_pc_set (sim_cpu *cpu, sim_cia pc) 185 { 186 PC = pc; 187 } 188 189 static int v850_reg_fetch (SIM_CPU *, int, void *, int); 190 static int v850_reg_store (SIM_CPU *, int, const void *, int); 191 192 SIM_DESC 193 sim_open (SIM_OPEN_KIND kind, 194 host_callback * cb, 195 struct bfd * abfd, 196 char * const * argv) 197 { 198 int i; 199 SIM_DESC sd = sim_state_alloc (kind, cb); 200 int mach; 201 202 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); 203 204 /* Set default options before parsing user options. */ 205 current_target_byte_order = BFD_ENDIAN_LITTLE; 206 cb->syscall_map = cb_v850_syscall_map; 207 208 /* The cpu data is kept in a separately allocated chunk of memory. */ 209 if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct v850_sim_cpu)) 210 != SIM_RC_OK) 211 return 0; 212 213 /* for compatibility */ 214 simulator = sd; 215 216 /* FIXME: should be better way of setting up interrupts */ 217 STATE_WATCHPOINTS (sd)->interrupt_handler = do_interrupt; 218 STATE_WATCHPOINTS (sd)->interrupt_names = interrupt_names; 219 220 /* Initialize the mechanism for doing insn profiling. */ 221 CPU_INSN_NAME (STATE_CPU (sd, 0)) = get_insn_name; 222 CPU_MAX_INSNS (STATE_CPU (sd, 0)) = nr_itable_entries; 223 224 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) 225 return 0; 226 227 /* Allocate core managed memory */ 228 229 /* "Mirror" the ROM addresses below 1MB. */ 230 sim_do_commandf (sd, "memory region 0,0x100000,0x%x", V850_ROM_SIZE); 231 /* Chunk of ram adjacent to rom */ 232 sim_do_commandf (sd, "memory region 0x100000,0x%x", V850_LOW_END-0x100000); 233 /* peripheral I/O region - mirror 1K across 4k (0x1000) */ 234 sim_do_command (sd, "memory region 0xfff000,0x1000,1024"); 235 /* similarly if in the internal RAM region */ 236 sim_do_command (sd, "memory region 0xffe000,0x1000,1024"); 237 238 /* The parser will print an error message for us, so we silently return. */ 239 if (sim_parse_args (sd, argv) != SIM_RC_OK) 240 { 241 /* Uninstall the modules to avoid memory leaks, 242 file descriptor leaks, etc. */ 243 sim_module_uninstall (sd); 244 return 0; 245 } 246 247 /* check for/establish the a reference program image */ 248 if (sim_analyze_program (sd, STATE_PROG_FILE (sd), abfd) != SIM_RC_OK) 249 { 250 sim_module_uninstall (sd); 251 return 0; 252 } 253 254 /* establish any remaining configuration options */ 255 if (sim_config (sd) != SIM_RC_OK) 256 { 257 sim_module_uninstall (sd); 258 return 0; 259 } 260 261 if (sim_post_argv_init (sd) != SIM_RC_OK) 262 { 263 /* Uninstall the modules to avoid memory leaks, 264 file descriptor leaks, etc. */ 265 sim_module_uninstall (sd); 266 return 0; 267 } 268 269 270 /* determine the machine type */ 271 if (STATE_ARCHITECTURE (sd) != NULL 272 && (STATE_ARCHITECTURE (sd)->arch == bfd_arch_v850 273 || STATE_ARCHITECTURE (sd)->arch == bfd_arch_v850_rh850)) 274 mach = STATE_ARCHITECTURE (sd)->mach; 275 else 276 mach = bfd_mach_v850; /* default */ 277 278 /* set machine specific configuration */ 279 switch (mach) 280 { 281 case bfd_mach_v850: 282 case bfd_mach_v850e: 283 case bfd_mach_v850e1: 284 case bfd_mach_v850e2: 285 case bfd_mach_v850e2v3: 286 case bfd_mach_v850e3v5: 287 V850_SIM_CPU (STATE_CPU (sd, 0))->psw_mask = 288 (PSW_NP | PSW_EP | PSW_ID | PSW_SAT | PSW_CY | PSW_OV | PSW_S | PSW_Z); 289 break; 290 } 291 292 /* CPU specific initialization. */ 293 for (i = 0; i < MAX_NR_PROCESSORS; ++i) 294 { 295 SIM_CPU *cpu = STATE_CPU (sd, i); 296 297 CPU_REG_FETCH (cpu) = v850_reg_fetch; 298 CPU_REG_STORE (cpu) = v850_reg_store; 299 CPU_PC_FETCH (cpu) = v850_pc_get; 300 CPU_PC_STORE (cpu) = v850_pc_set; 301 } 302 303 return sd; 304 } 305 306 SIM_RC 307 sim_create_inferior (SIM_DESC sd, 308 struct bfd * prog_bfd, 309 char * const *argv, 310 char * const *env) 311 { 312 memset (&State, 0, sizeof (State)); 313 if (prog_bfd != NULL) 314 PC = bfd_get_start_address (prog_bfd); 315 return SIM_RC_OK; 316 } 317 318 static int 319 v850_reg_fetch (SIM_CPU *cpu, int rn, void *memory, int length) 320 { 321 *(uint32_t*)memory = H2T_4 (State.regs[rn]); 322 return -1; 323 } 324 325 static int 326 v850_reg_store (SIM_CPU *cpu, int rn, const void *memory, int length) 327 { 328 State.regs[rn] = T2H_4 (*(uint32_t *) memory); 329 return length; 330 } 331