1# frv testcase for smuli $GRi,$GRj,$GRk 2# mach: all 3 4 .include "testutils.inc" 5 6 start 7 8 .global smuli 9smuli: 10 ; Positive operands 11 set_gr_immed 3,gr7 ; multiply small numbers 12 set_icc 0x0,0 13 smuli gr7,2,gr8 14 test_icc 0 0 0 0 icc0 15 test_gr_immed 0,gr8 16 test_gr_immed 6,gr9 17 18 set_gr_immed 1,gr7 ; multiply by 1 19 set_icc 0x1,0 20 smuli gr7,2,gr8 21 test_icc 0 0 0 1 icc0 22 test_gr_immed 0,gr8 23 test_gr_immed 2,gr9 24 25 set_gr_immed 2,gr7 ; multiply by 1 26 set_icc 0x2,0 27 smuli gr7,1,gr8 28 test_icc 0 0 1 0 icc0 29 test_gr_immed 0,gr8 30 test_gr_immed 2,gr9 31 32 set_gr_immed 0,gr7 ; multiply by 0 33 set_icc 0x3,0 34 smuli gr7,2,gr8 35 test_icc 0 0 1 1 icc0 36 test_gr_immed 0,gr8 37 test_gr_immed 0,gr9 38 39 set_gr_immed 2,gr7 ; multiply by 0 40 set_icc 0x4,0 41 smuli gr7,0,gr8 42 test_icc 0 1 0 0 icc0 43 test_gr_immed 0,gr8 44 test_gr_immed 0,gr9 45 46 set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result 47 set_icc 0x5,0 48 smuli gr7,2,gr8 49 test_icc 0 1 0 1 icc0 50 test_gr_immed 0,gr8 51 test_gr_limmed 0x7fff,0xfffe,gr9 52 53 set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result 54 set_icc 0x6,0 55 smuli gr7,2,gr8 56 test_icc 0 1 1 0 icc0 57 test_gr_immed 0,gr8 58 test_gr_limmed 0x8000,0x0000,gr9 59 60 set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result 61 set_icc 0x7,0 62 smuli gr7,4,gr8 63 test_icc 0 1 1 1 icc0 64 test_gr_immed 1,gr8 65 test_gr_limmed 0x0000,0x0000,gr9 66 67 set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result 68 set_icc 0x8,0 69 smuli gr7,0x7ff,gr8 70 test_icc 1 0 0 0 icc0 71 test_gr_immed 0x3ff,gr8 72 test_gr_limmed 0x7fff,0xf801,gr9 73 74 ; Mixed operands 75 set_gr_immed -3,gr7 ; multiply small numbers 76 set_icc 0x9,0 77 smuli gr7,2,gr8 78 test_icc 1 0 0 1 icc0 79 test_gr_immed -1,gr8 80 test_gr_immed -6,gr9 81 82 set_gr_immed 3,gr7 ; multiply small numbers 83 set_icc 0xa,0 84 smuli gr7,-2,gr8 85 test_icc 1 0 1 0 icc0 86 test_gr_immed -1,gr8 87 test_gr_immed -6,gr9 88 89 set_gr_immed 1,gr7 ; multiply by 1 90 set_icc 0xb,0 91 smuli gr7,-2,gr8 92 test_icc 1 0 1 1 icc0 93 test_gr_immed -1,gr8 94 test_gr_immed -2,gr9 95 96 set_gr_immed -2,gr7 ; multiply by 1 97 set_icc 0xc,0 98 smuli gr7,1,gr8 99 test_icc 1 1 0 0 icc0 100 test_gr_immed -1,gr8 101 test_gr_immed -2,gr9 102 103 set_gr_immed 0,gr7 ; multiply by 0 104 set_icc 0xd,0 105 smuli gr7,-2,gr8 106 test_icc 1 1 0 1 icc0 107 test_gr_immed 0,gr8 108 test_gr_immed 0,gr9 109 110 set_gr_immed -2,gr7 ; multiply by 0 111 set_icc 0xe,0 112 smuli gr7,0,gr8 113 test_icc 1 1 1 0 icc0 114 test_gr_immed 0,gr8 115 test_gr_immed 0,gr9 116 117 set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result 118 set_icc 0xf,0 119 smuli gr7,-2,gr8 120 test_icc 1 1 1 1 icc0 121 test_gr_limmed 0xffff,0xffff,gr8 122 test_gr_limmed 0xbfff,0xfffe,gr9 123 124 set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result 125 set_icc 0x0,0 126 smuli gr7,-2,gr8 127 test_icc 0 0 0 0 icc0 128 test_gr_limmed 0xffff,0xffff,gr8 129 test_gr_limmed 0x8000,0x0000,gr9 130 131 set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result 132 set_icc 0x1,0 133 smuli gr7,-2,gr8 134 test_icc 0 0 0 1 icc0 135 test_gr_limmed 0xffff,0xffff,gr8 136 test_gr_limmed 0x7fff,0xfffe,gr9 137 138 set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result 139 set_icc 0x2,0 140 smuli gr7,-4,gr8 141 test_icc 0 0 1 0 icc0 142 test_gr_limmed 0xffff,0xffff,gr8 143 test_gr_limmed 0x0000,0x0000,gr9 144 145 set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result 146 set_icc 0x3,0 147 smuli gr7,-2048,gr8 148 test_icc 0 0 1 1 icc0 149 test_gr_limmed 0xffff,0xfc00,gr8 150 test_gr_limmed 0x0000,0x0800,gr9 151 152 ; Negative operands 153 set_gr_immed -3,gr7 ; multiply small numbers 154 set_icc 0x4,0 155 smuli gr7,-2,gr8 156 test_icc 0 1 0 0 icc0 157 test_gr_immed 0,gr8 158 test_gr_immed 6,gr9 159 160 set_gr_immed -1,gr7 ; multiply by 1 161 set_icc 0x5,0 162 smuli gr7,-2,gr8 163 test_icc 0 1 0 1 icc0 164 test_gr_immed 0,gr8 165 test_gr_immed 2,gr9 166 167 set_gr_immed -2,gr7 ; multiply by 1 168 set_icc 0x6,0 169 smuli gr7,-1,gr8 170 test_icc 0 1 1 0 icc0 171 test_gr_immed 0,gr8 172 test_gr_immed 2,gr9 173 174 set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result 175 set_icc 0x7,0 176 smuli gr7,-2,gr8 177 test_icc 0 1 1 1 icc0 178 test_gr_immed 0,gr8 179 test_gr_limmed 0x7fff,0xfffe,gr9 180 181 set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result 182 set_icc 0x8,0 183 smuli gr7,-2,gr8 184 test_icc 1 0 0 0 icc0 185 test_gr_immed 0,gr8 186 test_gr_limmed 0x8000,0x0000,gr9 187 188 set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result 189 set_icc 0x9,0 190 smuli gr7,-4,gr8 191 test_icc 1 0 0 1 icc0 192 test_gr_immed 1,gr8 193 test_gr_immed 0x00000000,gr9 194 195 set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result 196 set_icc 0xa,0 197 smuli gr7,-2048,gr8 198 test_icc 1 0 1 0 icc0 199 test_gr_limmed 0x0000,0x03ff,gr8 200 test_gr_limmed 0xffff,0xf800,gr9 201 202 203 set_gr_limmed 0x8000,0x0000,gr7 ; max positive result 204 set_icc 0xb,0 205 smuli gr7,-2048,gr8 206 test_icc 1 0 1 1 icc0 207 test_gr_limmed 0x0000,0x0400,gr8 208 test_gr_limmed 0x0000,0x0000,gr9 209 210 pass 211