1# frv testcase for maddhus $FRi,$FRj,$FRj 2# mach: frv fr500 fr400 3 4 .include "testutils.inc" 5 6 start 7 8 .global maddhus 9maddhus: 10 set_fr_iimmed 0x0000,0x0000,fr10 11 set_fr_iimmed 0x0000,0x0000,fr11 12 maddhus fr10,fr11,fr12 13 test_fr_limmed 0x0000,0x0000,fr12 14 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 15 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 16 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 17 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 18 19 set_fr_iimmed 0xdead,0x0000,fr10 20 set_fr_iimmed 0x0000,0xbeef,fr11 21 maddhus fr10,fr11,fr12 22 test_fr_limmed 0xdead,0xbeef,fr12 23 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 24 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 25 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 26 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 27 28 set_fr_iimmed 0x0000,0xdead,fr10 29 set_fr_iimmed 0xbeef,0x0000,fr11 30 maddhus fr10,fr11,fr12 31 test_fr_limmed 0xbeef,0xdead,fr12 32 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 33 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 34 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 35 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 36 37 set_fr_iimmed 0x1234,0x5678,fr10 38 set_fr_iimmed 0x1111,0x1111,fr11 39 maddhus fr10,fr11,fr12 40 test_fr_limmed 0x2345,0x6789,fr12 41 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 42 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 43 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 44 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 45 46 set_fr_iimmed 0x7ffe,0x7ffe,fr10 47 set_fr_iimmed 0x0002,0x0001,fr11 48 maddhus fr10,fr11,fr12 49 test_fr_limmed 0x8000,0x7fff,fr12 50 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 51 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 52 test_spr_bits 1,0,0,msr0 ; msr0.aovf set 53 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 54 55 set_fr_iimmed 0xfffe,0xfffe,fr10 56 set_fr_iimmed 0x0001,0x0002,fr11 57 maddhus fr10,fr11,fr12 58 test_fr_limmed 0xffff,0xffff,fr12 59 test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set 60 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 61 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 62 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 63 64 set_spr_immed 0,msr0 65 set_fr_iimmed 0x0002,0x0001,fr10 66 set_fr_iimmed 0xfffe,0xfffe,fr11 67 maddhus fr10,fr11,fr12 68 test_fr_limmed 0xffff,0xffff,fr12 69 test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set 70 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 71 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 72 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 73 74 set_spr_immed 0,msr0 75 set_spr_immed 0,msr1 76 set_fr_iimmed 0x0001,0x0001,fr10 77 set_fr_iimmed 0x8000,0x8000,fr11 78 maddhus.p fr10,fr10,fr12 79 maddhus fr11,fr11,fr13 80 test_fr_limmed 0x0002,0x0002,fr12 81 test_fr_limmed 0xffff,0xffff,fr13 82 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 83 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 84 test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set 85 test_spr_bits 2,1,1,msr1 ; msr1.ovf set 86 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 87 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 88 89 pass 90