1*4b169a6bSchristos# frv testcase for mp_exception 2*4b169a6bSchristos# mach: fr500 fr550 frv 3*4b169a6bSchristos# xerror: 4*4b169a6bSchristos 5*4b169a6bSchristos# This program no longer assembles because the assembler 6*4b169a6bSchristos# now detects the unaligned registers. For this reason 7*4b169a6bSchristos# this test is now marked as "xerror" and prints the 8*4b169a6bSchristos# expected message "fail" 9*4b169a6bSchristos 10*4b169a6bSchristos .include "testutils.inc" 11*4b169a6bSchristos 12*4b169a6bSchristos start 13*4b169a6bSchristos 14*4b169a6bSchristos .global mp_exception 15*4b169a6bSchristosmpx: 16*4b169a6bSchristos.if 1 17*4b169a6bSchristos fail 18*4b169a6bSchristos.else 19*4b169a6bSchristos or_spr_immed 2,msr0 ; Set msr0.ovf 20*4b169a6bSchristos or_spr_immed 2,msr1 ; Set msr1.ovf 21*4b169a6bSchristos and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt 22*4b169a6bSchristos mcmpsh fr10,fr11,fcc1 ; mp_exception: cr-not-aligned 23*4b169a6bSchristos test_spr_bits 0x7000,12,3,msr0; msr0.mtt is set 24*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear 25*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear 26*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear 27*4b169a6bSchristos test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf is set 28*4b169a6bSchristos 29*4b169a6bSchristos or_spr_immed 2,msr0 ; Set msr0.ovf 30*4b169a6bSchristos or_spr_immed 2,msr1 ; Set msr1.ovf 31*4b169a6bSchristos and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt 32*4b169a6bSchristos mcmpsh.p fr10,fr11,fcc0 ; no exception 33*4b169a6bSchristos mcmpsh fr10,fr11,fcc2 ; no exception 34*4b169a6bSchristos test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear 35*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear 36*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear 37*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear 38*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear 39*4b169a6bSchristos 40*4b169a6bSchristos mmulhs.p fr10,fr11,acc3 ; no exception 41*4b169a6bSchristos mmulhs fr10,fr11,acc1 ; mp_exception: acc-not-aligned 42*4b169a6bSchristos test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set 43*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear 44*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear 45*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear 46*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear 47*4b169a6bSchristos 48*4b169a6bSchristos or_spr_immed 2,msr0 ; Set msr0.ovf 49*4b169a6bSchristos or_spr_immed 2,msr1 ; Set msr1.ovf 50*4b169a6bSchristos and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt 51*4b169a6bSchristos mmulhu fr10,fr11,acc0 ; no exception 52*4b169a6bSchristos test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear 53*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear 54*4b169a6bSchristos test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set 55*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear 56*4b169a6bSchristos test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set 57*4b169a6bSchristos 58*4b169a6bSchristos set_spr_immed 0,msr0 59*4b169a6bSchristos set_spr_immed 0,msr1 60*4b169a6bSchristos mmulxhs.p fr10,fr11,acc3 ; no exception 61*4b169a6bSchristos mmulxhs fr10,fr11,acc1 ; mp_exception: acc-not-aligned 62*4b169a6bSchristos test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set 63*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear 64*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear 65*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear 66*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear 67*4b169a6bSchristos 68*4b169a6bSchristos or_spr_immed 2,msr0 ; Set msr0.ovf 69*4b169a6bSchristos or_spr_immed 2,msr1 ; Set msr1.ovf 70*4b169a6bSchristos and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt 71*4b169a6bSchristos mmulxhu fr10,fr11,acc0 ; no exception 72*4b169a6bSchristos test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear 73*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear 74*4b169a6bSchristos test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set 75*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear 76*4b169a6bSchristos test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set 77*4b169a6bSchristos 78*4b169a6bSchristos set_spr_immed 0,msr0 79*4b169a6bSchristos set_spr_immed 0,msr1 80*4b169a6bSchristos mmachs.p fr10,fr11,acc3 ; no exception 81*4b169a6bSchristos mmachs fr10,fr11,acc1 ; mp_exception: acc-not-aligned 82*4b169a6bSchristos test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set 83*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear 84*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear 85*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear 86*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear 87*4b169a6bSchristos 88*4b169a6bSchristos or_spr_immed 2,msr0 ; Set msr0.ovf 89*4b169a6bSchristos or_spr_immed 2,msr1 ; Set msr1.ovf 90*4b169a6bSchristos and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt 91*4b169a6bSchristos mmachu fr10,fr11,acc0 ; no exception 92*4b169a6bSchristos test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear 93*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear 94*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear 95*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear 96*4b169a6bSchristos test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set 97*4b169a6bSchristos 98*4b169a6bSchristos set_spr_immed 0,msr0 99*4b169a6bSchristos set_spr_immed 0,msr1 100*4b169a6bSchristos mqaddhss.p fr10,fr12,fr17 ; mp_exception: register-not-aligned 101*4b169a6bSchristos mqaddhss fr10,fr12,fr14 ; no exception 102*4b169a6bSchristos test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set 103*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear 104*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear 105*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear 106*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear 107*4b169a6bSchristos 108*4b169a6bSchristos set_spr_immed 0,msr0 109*4b169a6bSchristos set_spr_immed 0,msr1 110*4b169a6bSchristos mqaddhss.p fr10,fr12,fr14 ; no exception 111*4b169a6bSchristos mqaddhss fr10,fr13,fr16 ; mp_exception: register-not-aligned 112*4b169a6bSchristos test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set 113*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear 114*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear 115*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear 116*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear 117*4b169a6bSchristos 118*4b169a6bSchristos set_spr_immed 0,msr0 119*4b169a6bSchristos set_spr_immed 0,msr1 120*4b169a6bSchristos mqaddhss.p fr19,fr12,fr14 ; mp_exception: register-not-aligned 121*4b169a6bSchristos mqaddhss fr10,fr13,fr16 ; mp_exception: register-not-aligned 122*4b169a6bSchristos test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set 123*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear 124*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear 125*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear 126*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear 127*4b169a6bSchristos 128*4b169a6bSchristos or_spr_immed 2,msr0 ; Set msr0.ovf 129*4b169a6bSchristos or_spr_immed 2,msr1 ; Set msr1.ovf 130*4b169a6bSchristos and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt 131*4b169a6bSchristos mqaddhss fr10,fr12,fr14 ; no exception 132*4b169a6bSchristos test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear 133*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear 134*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear 135*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear 136*4b169a6bSchristos test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set 137*4b169a6bSchristos 138*4b169a6bSchristos set_spr_immed 0,msr0 139*4b169a6bSchristos set_spr_immed 0,msr1 140*4b169a6bSchristos mqmulhs.p fr10,fr11,acc3 ; no exception 141*4b169a6bSchristos mqmulhs fr10,fr11,acc2 ; mp_exception: acc-not-aligned 142*4b169a6bSchristos test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set 143*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear 144*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear 145*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear 146*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear 147*4b169a6bSchristos 148*4b169a6bSchristos or_spr_immed 2,msr0 ; Set msr0.ovf 149*4b169a6bSchristos or_spr_immed 2,msr1 ; Set msr1.ovf 150*4b169a6bSchristos and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt 151*4b169a6bSchristos mqmulhu fr10,fr11,acc0 ; mp_exception: register_not_aligned 152*4b169a6bSchristos test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set 153*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear 154*4b169a6bSchristos test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set 155*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear 156*4b169a6bSchristos test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set 157*4b169a6bSchristos 158*4b169a6bSchristos and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt 159*4b169a6bSchristos mqmulhu fr10,fr12,acc0 ; no exception 160*4b169a6bSchristos test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear 161*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear 162*4b169a6bSchristos test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set 163*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear 164*4b169a6bSchristos test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set 165*4b169a6bSchristos 166*4b169a6bSchristos set_spr_immed 0,msr0 167*4b169a6bSchristos set_spr_immed 0,msr1 168*4b169a6bSchristos mqmulxhs.p fr10,fr11,acc3 ; no exception 169*4b169a6bSchristos mqmulxhs fr10,fr11,acc2 ; mp_exception: acc-not-aligned 170*4b169a6bSchristos test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set 171*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear 172*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear 173*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear 174*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear 175*4b169a6bSchristos 176*4b169a6bSchristos or_spr_immed 2,msr0 ; Set msr0.ovf 177*4b169a6bSchristos or_spr_immed 2,msr1 ; Set msr1.ovf 178*4b169a6bSchristos and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt 179*4b169a6bSchristos mqmulxhu fr10,fr11,acc0 ; mp_exception: register-not-aligned 180*4b169a6bSchristos test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set 181*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear 182*4b169a6bSchristos test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set 183*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear 184*4b169a6bSchristos test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set 185*4b169a6bSchristos 186*4b169a6bSchristos and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt 187*4b169a6bSchristos mqmulxhu fr10,fr12,acc0 ; no exception 188*4b169a6bSchristos test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear 189*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear 190*4b169a6bSchristos test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set 191*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear 192*4b169a6bSchristos test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set 193*4b169a6bSchristos 194*4b169a6bSchristos set_spr_immed 0,msr0 195*4b169a6bSchristos set_spr_immed 0,msr1 196*4b169a6bSchristos mqmachs.p fr10,fr12,acc3 ; no exception 197*4b169a6bSchristos mqmachs fr10,fr12,acc2 ; mp_exception: acc-not-aligned 198*4b169a6bSchristos test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set 199*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear 200*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear 201*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear 202*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear 203*4b169a6bSchristos 204*4b169a6bSchristos and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt 205*4b169a6bSchristos mqmachu.p fr19,fr12,acc0 ; mp_exception: register-not-aligned 206*4b169a6bSchristos mqmachu fr10,fr12,acc0 ; no exception 207*4b169a6bSchristos test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set 208*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear 209*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear 210*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear 211*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear 212*4b169a6bSchristos 213*4b169a6bSchristos and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt 214*4b169a6bSchristos mqmachu.p fr10,fr12,acc0 ; no exception 215*4b169a6bSchristos mqmachu fr19,fr12,acc0 ; mp_exception: register-not-aligned 216*4b169a6bSchristos test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set 217*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear 218*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear 219*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear 220*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear 221*4b169a6bSchristos 222*4b169a6bSchristos and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt 223*4b169a6bSchristos mqmachu.p fr19,fr12,acc0 ; mp_exception: register-not-aligned 224*4b169a6bSchristos mqmachu fr19,fr12,acc0 ; mp_exception: register-not-aligned 225*4b169a6bSchristos test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set 226*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear 227*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear 228*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear 229*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear 230*4b169a6bSchristos 231*4b169a6bSchristos or_spr_immed 2,msr0 ; Set msr0.ovf 232*4b169a6bSchristos or_spr_immed 2,msr1 ; Set msr1.ovf 233*4b169a6bSchristos and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt 234*4b169a6bSchristos mqmachu fr10,fr12,acc0 ; no exception 235*4b169a6bSchristos test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear 236*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear 237*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear 238*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear 239*4b169a6bSchristos test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set 240*4b169a6bSchristos 241*4b169a6bSchristos set_spr_immed 0,msr0 242*4b169a6bSchristos set_spr_immed 0,msr1 243*4b169a6bSchristos mqcpxrs.p fr10,fr12,acc0 ; no exception 244*4b169a6bSchristos mqcpxrs fr10,fr12,acc1 ; mp_exception: acc-not-aligned 245*4b169a6bSchristos test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set 246*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear 247*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear 248*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear 249*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear 250*4b169a6bSchristos 251*4b169a6bSchristos and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt 252*4b169a6bSchristos mqcpxru.p fr19,fr12,acc0 ; mp_exception: register-not-aligned 253*4b169a6bSchristos mqcpxru fr10,fr12,acc0 ; no exception 254*4b169a6bSchristos test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set 255*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear 256*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear 257*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear 258*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear 259*4b169a6bSchristos 260*4b169a6bSchristos and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt 261*4b169a6bSchristos mqcpxru.p fr10,fr12,acc0 ; no exception 262*4b169a6bSchristos mqcpxru fr19,fr12,acc0 ; mp_exception: register-not-aligned 263*4b169a6bSchristos test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set 264*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear 265*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear 266*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear 267*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear 268*4b169a6bSchristos 269*4b169a6bSchristos and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt 270*4b169a6bSchristos mqcpxru.p fr19,fr12,acc0 ; mp_exception: register-not-aligned 271*4b169a6bSchristos mqcpxru fr19,fr12,acc0 ; mp_exception: register-not-aligned 272*4b169a6bSchristos test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set 273*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear 274*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear 275*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear 276*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear 277*4b169a6bSchristos 278*4b169a6bSchristos or_spr_immed 2,msr0 ; Set msr0.ovf 279*4b169a6bSchristos or_spr_immed 2,msr1 ; Set msr1.ovf 280*4b169a6bSchristos and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt 281*4b169a6bSchristos mqcpxru fr10,fr12,acc0 ; no exception 282*4b169a6bSchristos test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear 283*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear 284*4b169a6bSchristos test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear 285*4b169a6bSchristos test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear 286*4b169a6bSchristos test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set 287*4b169a6bSchristos 288*4b169a6bSchristos pass 289*4b169a6bSchristos.endif 290