1*4b169a6bSchristos# frv testcase to generate fp_exception 2*4b169a6bSchristos# mach: fr550 3*4b169a6bSchristos .include "testutils.inc" 4*4b169a6bSchristos 5*4b169a6bSchristos float_constants 6*4b169a6bSchristos start 7*4b169a6bSchristos load_float_constants 8*4b169a6bSchristos 9*4b169a6bSchristos .global align 10*4b169a6bSchristosalign: 11*4b169a6bSchristos ; clear the packing bit if the insn at 'pack:'. We can't simply use 12*4b169a6bSchristos ; '.p' because the assembler will catch the error. 13*4b169a6bSchristos set_gr_mem pack,gr10 14*4b169a6bSchristos and_gr_immed 0x7fffffff,gr10 15*4b169a6bSchristos set_mem_gr gr10,pack 16*4b169a6bSchristos set_gr_addr pack,gr10 17*4b169a6bSchristos flush_data_cache gr10 18*4b169a6bSchristos 19*4b169a6bSchristos ; Make the the source register number odd at badst. We can't simply 20*4b169a6bSchristos ; code an odd register number because the assembler will catch the 21*4b169a6bSchristos ; error. 22*4b169a6bSchristos set_gr_mem badst,gr10 23*4b169a6bSchristos or_gr_immed 0x02000000,gr10 24*4b169a6bSchristos set_mem_gr gr10,badst 25*4b169a6bSchristos set_gr_addr badst,gr10 26*4b169a6bSchristos flush_data_cache gr10 27*4b169a6bSchristos 28*4b169a6bSchristos ; Make the the dest register number odd at badld. We can't simply 29*4b169a6bSchristos ; code an odd register number because the assembler will catch the 30*4b169a6bSchristos ; error. 31*4b169a6bSchristos set_gr_mem badld,gr10 32*4b169a6bSchristos or_gr_immed 0x02000000,gr10 33*4b169a6bSchristos set_mem_gr gr10,badld 34*4b169a6bSchristos set_gr_addr badld,gr10 35*4b169a6bSchristos flush_data_cache gr10 36*4b169a6bSchristos 37*4b169a6bSchristos and_spr_immed -4081,tbr ; clear tbr.tt 38*4b169a6bSchristos set_gr_spr tbr,gr17 39*4b169a6bSchristos inc_gr_immed 0x070,gr17 ; address of exception handler 40*4b169a6bSchristos set_bctrlr_0_0 gr17 41*4b169a6bSchristos inc_gr_immed 0x060,gr17 ; address of exception handler 42*4b169a6bSchristos set_bctrlr_0_0 gr17 43*4b169a6bSchristos set_spr_immed 128,lcr 44*4b169a6bSchristos set_spr_addr ok1,lr 45*4b169a6bSchristos set_psr_et 1 46*4b169a6bSchristos inc_gr_immed -4,sp ; for alignment 47*4b169a6bSchristos 48*4b169a6bSchristos set_gr_immed 0,gr20 ; PC increment 49*4b169a6bSchristos set_gr_immed 0,gr15 50*4b169a6bSchristos 51*4b169a6bSchristos set_spr_addr ok3,lr 52*4b169a6bSchristos set_gr_immed 4,gr20 ; PC increment 53*4b169a6bSchristosbadst: stdfi fr0,@(sp,0) ; misaligned reg -- slot I0 54*4b169a6bSchristos test_gr_immed 1,gr15 55*4b169a6bSchristos 56*4b169a6bSchristos set_spr_addr ok4,lr 57*4b169a6bSchristos set_gr_immed 8,gr20 ; PC increment 58*4b169a6bSchristos nop.p 59*4b169a6bSchristosbadld: lddfi @(sp,0),fr8 ; misaligned reg -- slot I1 60*4b169a6bSchristos test_gr_immed 2,gr15 61*4b169a6bSchristos 62*4b169a6bSchristos set_spr_addr ok5,lr 63*4b169a6bSchristos set_gr_immed 20,gr20 ; PC increment 64*4b169a6bSchristos fnegs.p fr9,fr9 65*4b169a6bSchristos fnegs.p fr9,fr10 66*4b169a6bSchristos fnegs.p fr9,fr11 67*4b169a6bSchristospack: fnegs fr10,fr12 68*4b169a6bSchristos fnegs fr10,fr13 ; packing violation 69*4b169a6bSchristos test_gr_immed 3,gr15 70*4b169a6bSchristos 71*4b169a6bSchristos set_spr_addr ok1,lr 72*4b169a6bSchristos set_gr_immed 4,gr20 ; PC increment 73*4b169a6bSchristosbad: .word 0x83e502c4 ; fmadds fr16,fr4,fr1 (unimplemented) 74*4b169a6bSchristos test_gr_immed 4,gr15 75*4b169a6bSchristos 76*4b169a6bSchristos and_spr_immed 0xfbffffff,fsr0 ; disable div/0 fp_exception 77*4b169a6bSchristos set_fr_iimmed 0x7f7f,0xffff,fr0 78*4b169a6bSchristos set_fr_iimmed 0x0000,0x0000,fr1 79*4b169a6bSchristos fdivs fr0,fr1,fr2 ; div/0 -- no exception 80*4b169a6bSchristos test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is never set 81*4b169a6bSchristos test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set 82*4b169a6bSchristos test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear 83*4b169a6bSchristos 84*4b169a6bSchristos set_spr_addr ok2,lr 85*4b169a6bSchristos set_gr_immed 0,gr20 ; PC increment 86*4b169a6bSchristos or_spr_immed 0x04000000,fsr0 ; enable div/0 fp_exception 87*4b169a6bSchristos set_fr_iimmed 0xdead,0xbeef,fr2 88*4b169a6bSchristosdiv0: fdivs fr0,fr1,fr2 ; fp_exception - div/0 89*4b169a6bSchristos test_fr_iimmed 0xdeadbeef,fr2 ; fr2 not updated 90*4b169a6bSchristos test_gr_immed 5,gr15 91*4b169a6bSchristos 92*4b169a6bSchristos and_spr_immed 0xfdffffff,fsr0 ; disable inexact fp_exception 93*4b169a6bSchristos fsqrts fr32,fr2 ; inexact -- no exception 94*4b169a6bSchristos test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is never set 95*4b169a6bSchristos test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is set 96*4b169a6bSchristos test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear 97*4b169a6bSchristos 98*4b169a6bSchristos set_fr_fr fr2,fr3 ; sqrt 2 99*4b169a6bSchristos set_fr_iimmed 0xdead,0xbeef,fr2 100*4b169a6bSchristos set_spr_addr ok6,lr 101*4b169a6bSchristos or_spr_immed 0x02000000,fsr0 ; enable inexact fp_exception 102*4b169a6bSchristosinxt1: fsqrts fr32,fr2 ; fp_exception - inexact 103*4b169a6bSchristos test_gr_immed 6,gr15 ; handler called 104*4b169a6bSchristos test_fr_fr fr2,fr3 ; fr2 updated 105*4b169a6bSchristos 106*4b169a6bSchristos set_fr_iimmed 0xdead,0xbeef,fr2 107*4b169a6bSchristos set_spr_addr ok7,lr 108*4b169a6bSchristosinxt2: fsqrts fr32,fr2 ; fp_exception - inexact again 109*4b169a6bSchristos test_gr_immed 7,gr15 ; handler called 110*4b169a6bSchristos test_fr_fr fr2,fr3 ; fr2 updated 111*4b169a6bSchristos 112*4b169a6bSchristos pass 113*4b169a6bSchristos 114*4b169a6bSchristos; exception handler 1 -- illegal_instruction: bad insn 115*4b169a6bSchristosok1: 116*4b169a6bSchristos test_spr_immed 1,esfr1 ; esr0 active 117*4b169a6bSchristos test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set 118*4b169a6bSchristos test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set 119*4b169a6bSchristos bra ret 120*4b169a6bSchristos 121*4b169a6bSchristos; exception handler 2 - fp_exception: divide by 0 122*4b169a6bSchristosok2: 123*4b169a6bSchristos test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear 124*4b169a6bSchristos test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set 125*4b169a6bSchristos test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set 126*4b169a6bSchristos 127*4b169a6bSchristos test_spr_immed 4,esfr1 ; esr2 active 128*4b169a6bSchristos test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set 129*4b169a6bSchristos test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set 130*4b169a6bSchristos test_spr_addr div0,epcr2 ; epcr2 is set 131*4b169a6bSchristos bra ret 132*4b169a6bSchristos 133*4b169a6bSchristos; exception handler 3 - illegal_instruction: register exception 134*4b169a6bSchristosok3: 135*4b169a6bSchristos test_spr_immed 1,esfr1 ; esr0 active 136*4b169a6bSchristos test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set 137*4b169a6bSchristos test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set 138*4b169a6bSchristos bra ret 139*4b169a6bSchristos 140*4b169a6bSchristos; exception handler 4 - illegal_instruction: register exception 141*4b169a6bSchristosok4: 142*4b169a6bSchristos test_spr_immed 1,esfr1 ; esr0 active 143*4b169a6bSchristos test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set 144*4b169a6bSchristos test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set 145*4b169a6bSchristos bra ret 146*4b169a6bSchristos 147*4b169a6bSchristos; exception handler 5 - illegal_instruction: sequence violation 148*4b169a6bSchristosok5: 149*4b169a6bSchristos test_spr_immed 1,esfr1 ; esr0 active 150*4b169a6bSchristos test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set 151*4b169a6bSchristos test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set 152*4b169a6bSchristos bra ret 153*4b169a6bSchristos 154*4b169a6bSchristos; exception handler 6 - fp_exception: inexact 155*4b169a6bSchristosok6: 156*4b169a6bSchristos test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear 157*4b169a6bSchristos test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set 158*4b169a6bSchristos test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set 159*4b169a6bSchristos 160*4b169a6bSchristos test_spr_immed 4,esfr1 ; esr2 active 161*4b169a6bSchristos test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set 162*4b169a6bSchristos test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set 163*4b169a6bSchristos test_spr_addr inxt1,epcr2 ; epcr2 is set 164*4b169a6bSchristos bra ret 165*4b169a6bSchristos 166*4b169a6bSchristos; exception handler 7 - fp_exception: inexact again 167*4b169a6bSchristosok7: 168*4b169a6bSchristos test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear 169*4b169a6bSchristos test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set 170*4b169a6bSchristos test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set 171*4b169a6bSchristos 172*4b169a6bSchristos test_spr_immed 4,esfr1 ; esr2 active 173*4b169a6bSchristos test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set 174*4b169a6bSchristos test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set 175*4b169a6bSchristos test_spr_addr inxt2,epcr2 ; epcr2 is set 176*4b169a6bSchristos bra ret 177*4b169a6bSchristos 178*4b169a6bSchristosret: 179*4b169a6bSchristos inc_gr_immed 1,gr15 180*4b169a6bSchristos movsg pcsr,gr60 181*4b169a6bSchristos add gr60,gr20,gr60 182*4b169a6bSchristos movgs gr60,pcsr 183*4b169a6bSchristos rett 0 184*4b169a6bSchristos fail 185*4b169a6bSchristos 186