1# frv testcase for cmmachs $GRi,$GRj,$ACCk,$CCi,$cond 2# mach: all 3 4 .include "../testutils.inc" 5 6 start 7 8 .global cmmachs 9cmmachs: 10 set_spr_immed 0x1b1b,cccr 11 12 ; Positive operands 13 set_spr_immed 0x0,msr0 14 set_accg_immed 0x0,accg0 15 set_acc_immed 0x0,acc0 16 set_accg_immed 0x0,accg1 17 set_acc_immed 0x0,acc1 18 set_fr_iimmed 2,3,fr7 ; multiply small numbers 19 set_fr_iimmed 3,2,fr8 20 cmmachs fr7,fr8,acc0,cc0,1 21 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 22 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 23 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 24 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 25 test_accg_immed 0,accg0 26 test_acc_immed 6,acc0 27 test_accg_immed 0,accg1 28 test_acc_immed 6,acc1 29 30 set_fr_iimmed 0,1,fr7 ; multiply by 0 31 set_fr_iimmed 2,0,fr8 32 cmmachs fr7,fr8,acc0,cc0,1 33 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 34 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 35 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 36 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 37 test_accg_immed 0,accg0 38 test_acc_immed 6,acc0 39 test_accg_immed 0,accg1 40 test_acc_immed 6,acc1 41 42 set_fr_iimmed 2,1,fr7 ; multiply by 1 43 set_fr_iimmed 1,2,fr8 44 cmmachs fr7,fr8,acc0,cc0,1 45 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 46 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 47 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 48 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 49 test_accg_immed 0,accg0 50 test_acc_immed 8,acc0 51 test_accg_immed 0,accg1 52 test_acc_immed 8,acc1 53 54 set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result 55 set_fr_iimmed 2,0x3fff,fr8 56 cmmachs fr7,fr8,acc0,cc0,1 57 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 58 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 59 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 60 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 61 test_accg_immed 0,accg0 62 test_acc_limmed 0,0x8006,acc0 63 test_accg_immed 0,accg1 64 test_acc_limmed 0,0x8006,acc1 65 66 set_fr_iimmed 0x4000,2,fr7 ; 16 bit result 67 set_fr_iimmed 2,0x4000,fr8 68 cmmachs fr7,fr8,acc0,cc0,1 69 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 70 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 71 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 72 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 73 test_accg_immed 0,accg0 74 test_acc_limmed 0x0001,0x0006,acc0 75 test_accg_immed 0,accg1 76 test_acc_limmed 0x0001,0x0006,acc1 77 78 set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result 79 set_fr_iimmed 0x7fff,0x7fff,fr8 80 cmmachs fr7,fr8,acc0,cc0,1 81 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 82 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 83 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 84 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 85 test_accg_immed 0,accg0 86 test_acc_limmed 0x4000,0x0007,acc0 87 test_accg_immed 0,accg1 88 test_acc_limmed 0x4000,0x0007,acc1 89 90 ; Mixed operands 91 set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers 92 set_fr_iimmed 0xfffd,2,fr8 93 cmmachs fr7,fr8,acc0,cc0,1 94 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 95 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 96 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 97 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 98 test_accg_immed 0,accg0 99 test_acc_limmed 0x4000,0x0001,acc0 100 test_accg_immed 0,accg1 101 test_acc_limmed 0x4000,0x0001,acc1 102 103 set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 104 set_fr_iimmed 1,0xfffe,fr8 105 cmmachs fr7,fr8,acc0,cc0,1 106 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 107 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 108 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 109 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 110 test_accg_immed 0,accg0 111 test_acc_limmed 0x3fff,0xffff,acc0 112 test_accg_immed 0,accg1 113 test_acc_limmed 0x3fff,0xffff,acc1 114 115 set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 116 set_fr_iimmed 0,0xfffe,fr8 117 cmmachs fr7,fr8,acc0,cc0,1 118 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 119 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 120 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 121 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 122 test_accg_immed 0,accg0 123 test_acc_limmed 0x3fff,0xffff,acc0 124 test_accg_immed 0,accg1 125 test_acc_limmed 0x3fff,0xffff,acc1 126 127 set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result 128 set_fr_iimmed 0xfffe,0x2001,fr8 129 cmmachs fr7,fr8,acc0,cc0,1 130 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 131 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 132 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 133 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 134 test_accg_immed 0,accg0 135 test_acc_limmed 0x3fff,0xbffd,acc0 136 test_accg_immed 0,accg1 137 test_acc_limmed 0x3fff,0xbffd,acc1 138 139 set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result 140 set_fr_iimmed 0xfffe,0x4000,fr8 141 cmmachs fr7,fr8,acc0,cc4,1 142 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 143 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 144 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 145 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 146 test_accg_immed 0,accg0 147 test_acc_limmed 0x3fff,0x3ffd,acc0 148 test_accg_immed 0,accg1 149 test_acc_limmed 0x3fff,0x3ffd,acc1 150 151 set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result 152 set_fr_iimmed 0x8000,0x7fff,fr8 153 cmmachs fr7,fr8,acc0,cc4,1 154 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 155 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 156 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 157 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 158 test_accg_immed 0xff,accg0 159 test_acc_limmed 0xffff,0xbffd,acc0 160 test_accg_immed 0xff,accg1 161 test_acc_limmed 0xffff,0xbffd,acc1 162 163 ; Negative operands 164 set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers 165 set_fr_iimmed 0xfffd,0xfffe,fr8 166 cmmachs fr7,fr8,acc0,cc4,1 167 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 168 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 169 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 170 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 171 test_accg_immed 0xff,accg0 172 test_acc_limmed 0xffff,0xc003,acc0 173 test_accg_immed 0xff,accg1 174 test_acc_limmed 0xffff,0xc003,acc1 175 176 set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 177 set_fr_iimmed 0xfffe,0xffff,fr8 178 cmmachs fr7,fr8,acc0,cc4,1 179 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 180 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 181 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 182 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 183 test_accg_immed 0xff,accg0 184 test_acc_limmed 0xffff,0xc005,acc0 185 test_accg_immed 0xff,accg1 186 test_acc_limmed 0xffff,0xc005,acc1 187 188 set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result 189 set_fr_iimmed 0x8001,0x8001,fr8 190 cmmachs fr7,fr8,acc0,cc4,1 191 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 192 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 193 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 194 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 195 test_accg_immed 0,accg0 196 test_acc_immed 0x3ffec006,acc0 197 test_accg_immed 0,accg1 198 test_acc_immed 0x3ffec006,acc1 199 200 set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result 201 set_fr_iimmed 0x8000,0x8000,fr8 202 cmmachs fr7,fr8,acc0,cc4,1 203 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 204 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 205 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 206 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 207 test_accg_immed 0,accg0 208 test_acc_immed 0x7ffec006,acc0 209 test_accg_immed 0,accg1 210 test_acc_immed 0x7ffec006,acc1 211 212 set_accg_immed 0x7f,accg0 ; saturation 213 set_acc_immed 0xffffffff,acc0 214 set_accg_immed 0x7f,accg1 215 set_acc_immed 0xffffffff,acc1 216 set_fr_iimmed 1,1,fr7 217 set_fr_iimmed 1,1,fr8 218 cmmachs fr7,fr8,acc0,cc4,1 219;;;;;;;;;;;; 220 test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set 221 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set 222 test_spr_bits 1,0,1,msr0 ; msr0.aovf is set 223 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set 224 test_accg_immed 0x7f,accg0 225 test_acc_limmed 0xffff,0xffff,acc0 226 test_accg_immed 0x7f,accg1 227 test_acc_limmed 0xffff,0xffff,acc1 228 229 set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation 230 set_fr_iimmed 0x7fff,0x7fff,fr8 231 cmmachs fr7,fr8,acc0,cc4,1 232 test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set 233 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set 234 test_spr_bits 1,0,1,msr0 ; msr0.aovf is set 235 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set 236 test_accg_immed 0x7f,accg0 237 test_acc_limmed 0xffff,0xffff,acc0 238 test_accg_immed 0x7f,accg1 239 test_acc_limmed 0xffff,0xffff,acc1 240 241 set_accg_immed -128,accg0 ; saturation 242 set_acc_immed 0,acc0 243 set_accg_immed -128,accg1 244 set_acc_immed 0,acc1 245 set_fr_iimmed 0xffff,0,fr7 246 set_fr_iimmed 1,0xffff,fr8 247 cmmachs fr7,fr8,acc0,cc4,1 248 test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set 249 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set 250 test_spr_bits 1,0,1,msr0 ; msr0.aovf is set 251 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set 252 test_accg_immed 0x80,accg0 253 test_acc_immed 0,acc0 254 test_accg_immed 0x80,accg1 255 test_acc_immed 0,acc1 256 257 set_fr_iimmed 0x0000,0x8000,fr7 ; saturation 258 set_fr_iimmed 0x7fff,0x7fff,fr8 259 cmmachs fr7,fr8,acc0,cc4,1 260 test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set 261 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set 262 test_spr_bits 1,0,1,msr0 ; msr0.aovf is set 263 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set 264 test_accg_immed 0x80,accg0 265 test_acc_immed 0,acc0 266 test_accg_immed 0x80,accg1 267 test_acc_immed 0,acc1 268 269 ; Positive operands 270 set_spr_immed 0x0,msr0 271 set_accg_immed 0x0,accg0 ; saturation 272 set_acc_immed 0x0,acc0 273 set_accg_immed 0x0,accg1 274 set_acc_immed 0x0,acc1 275 set_fr_iimmed 2,3,fr7 ; multiply small numbers 276 set_fr_iimmed 3,2,fr8 277 cmmachs fr7,fr8,acc0,cc1,0 278 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 279 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 280 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 281 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 282 test_accg_immed 0,accg0 283 test_acc_immed 6,acc0 284 test_accg_immed 0,accg1 285 test_acc_immed 6,acc1 286 287 set_fr_iimmed 0,1,fr7 ; multiply by 0 288 set_fr_iimmed 2,0,fr8 289 cmmachs fr7,fr8,acc0,cc1,0 290 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 291 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 292 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 293 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 294 test_accg_immed 0,accg0 295 test_acc_immed 6,acc0 296 test_accg_immed 0,accg1 297 test_acc_immed 6,acc1 298 299 set_fr_iimmed 2,1,fr7 ; multiply by 1 300 set_fr_iimmed 1,2,fr8 301 cmmachs fr7,fr8,acc0,cc1,0 302 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 303 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 304 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 305 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 306 test_accg_immed 0,accg0 307 test_acc_immed 8,acc0 308 test_accg_immed 0,accg1 309 test_acc_immed 8,acc1 310 311 set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result 312 set_fr_iimmed 2,0x3fff,fr8 313 cmmachs fr7,fr8,acc0,cc1,0 314 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 315 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 316 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 317 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 318 test_accg_immed 0,accg0 319 test_acc_limmed 0,0x8006,acc0 320 test_accg_immed 0,accg1 321 test_acc_limmed 0,0x8006,acc1 322 323 set_fr_iimmed 0x4000,2,fr7 ; 16 bit result 324 set_fr_iimmed 2,0x4000,fr8 325 cmmachs fr7,fr8,acc0,cc1,0 326 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 327 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 328 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 329 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 330 test_accg_immed 0,accg0 331 test_acc_limmed 0x0001,0x0006,acc0 332 test_accg_immed 0,accg1 333 test_acc_limmed 0x0001,0x0006,acc1 334 335 set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result 336 set_fr_iimmed 0x7fff,0x7fff,fr8 337 cmmachs fr7,fr8,acc0,cc1,0 338 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 339 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 340 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 341 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 342 test_accg_immed 0,accg0 343 test_acc_limmed 0x4000,0x0007,acc0 344 test_accg_immed 0,accg1 345 test_acc_limmed 0x4000,0x0007,acc1 346 347 ; Mixed operands 348 set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers 349 set_fr_iimmed 0xfffd,2,fr8 350 cmmachs fr7,fr8,acc0,cc1,0 351 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 352 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 353 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 354 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 355 test_accg_immed 0,accg0 356 test_acc_limmed 0x4000,0x0001,acc0 357 test_accg_immed 0,accg1 358 test_acc_limmed 0x4000,0x0001,acc1 359 360 set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 361 set_fr_iimmed 1,0xfffe,fr8 362 cmmachs fr7,fr8,acc0,cc1,0 363 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 364 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 365 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 366 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 367 test_accg_immed 0,accg0 368 test_acc_limmed 0x3fff,0xffff,acc0 369 test_accg_immed 0,accg1 370 test_acc_limmed 0x3fff,0xffff,acc1 371 372 set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 373 set_fr_iimmed 0,0xfffe,fr8 374 cmmachs fr7,fr8,acc0,cc1,0 375 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 376 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 377 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 378 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 379 test_accg_immed 0,accg0 380 test_acc_limmed 0x3fff,0xffff,acc0 381 test_accg_immed 0,accg1 382 test_acc_limmed 0x3fff,0xffff,acc1 383 384 set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result 385 set_fr_iimmed 0xfffe,0x2001,fr8 386 cmmachs fr7,fr8,acc0,cc1,0 387 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 388 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 389 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 390 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 391 test_accg_immed 0,accg0 392 test_acc_limmed 0x3fff,0xbffd,acc0 393 test_accg_immed 0,accg1 394 test_acc_limmed 0x3fff,0xbffd,acc1 395 396 set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result 397 set_fr_iimmed 0xfffe,0x4000,fr8 398 cmmachs fr7,fr8,acc0,cc5,0 399 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 400 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 401 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 402 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 403 test_accg_immed 0,accg0 404 test_acc_limmed 0x3fff,0x3ffd,acc0 405 test_accg_immed 0,accg1 406 test_acc_limmed 0x3fff,0x3ffd,acc1 407 408 set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result 409 set_fr_iimmed 0x8000,0x7fff,fr8 410 cmmachs fr7,fr8,acc0,cc5,0 411 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 412 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 413 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 414 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 415 test_accg_immed 0xff,accg0 416 test_acc_limmed 0xffff,0xbffd,acc0 417 test_accg_immed 0xff,accg1 418 test_acc_limmed 0xffff,0xbffd,acc1 419 420 ; Negative operands 421 set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers 422 set_fr_iimmed 0xfffd,0xfffe,fr8 423 cmmachs fr7,fr8,acc0,cc5,0 424 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 425 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 426 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 427 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 428 test_accg_immed 0xff,accg0 429 test_acc_limmed 0xffff,0xc003,acc0 430 test_accg_immed 0xff,accg1 431 test_acc_limmed 0xffff,0xc003,acc1 432 433 set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 434 set_fr_iimmed 0xfffe,0xffff,fr8 435 cmmachs fr7,fr8,acc0,cc5,0 436 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 437 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 438 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 439 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 440 test_accg_immed 0xff,accg0 441 test_acc_limmed 0xffff,0xc005,acc0 442 test_accg_immed 0xff,accg1 443 test_acc_limmed 0xffff,0xc005,acc1 444 445 set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result 446 set_fr_iimmed 0x8001,0x8001,fr8 447 cmmachs fr7,fr8,acc0,cc5,0 448 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 449 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 450 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 451 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 452 test_accg_immed 0,accg0 453 test_acc_immed 0x3ffec006,acc0 454 test_accg_immed 0,accg1 455 test_acc_immed 0x3ffec006,acc1 456 457 set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result 458 set_fr_iimmed 0x8000,0x8000,fr8 459 cmmachs fr7,fr8,acc0,cc5,0 460 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 461 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 462 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 463 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 464 test_accg_immed 0,accg0 465 test_acc_immed 0x7ffec006,acc0 466 test_accg_immed 0,accg1 467 test_acc_immed 0x7ffec006,acc1 468 469 set_accg_immed 0x7f,accg0 ; saturation 470 set_acc_immed 0xffffffff,acc0 471 set_accg_immed 0x7f,accg1 472 set_acc_immed 0xffffffff,acc1 473 set_fr_iimmed 1,1,fr7 474 set_fr_iimmed 1,1,fr8 475 cmmachs fr7,fr8,acc0,cc5,0 476 test_accg_immed 0x7f,accg0 477 test_acc_limmed 0xffff,0xffff,acc0 478 test_accg_immed 0x7f,accg1 479 test_acc_limmed 0xffff,0xffff,acc1 480 481 set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation 482 set_fr_iimmed 0x7fff,0x7fff,fr8 483 cmmachs fr7,fr8,acc0,cc5,0 484 test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set 485 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set 486 test_spr_bits 1,0,1,msr0 ; msr0.aovf is set 487 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set 488 test_accg_immed 0x7f,accg0 489 test_acc_limmed 0xffff,0xffff,acc0 490 test_accg_immed 0x7f,accg1 491 test_acc_limmed 0xffff,0xffff,acc1 492 493 set_accg_immed 0x80,accg0 ; saturation 494 set_acc_immed 0,acc0 495 set_accg_immed 0x80,accg1 496 set_acc_immed 0,acc1 497 set_fr_iimmed 0xffff,0,fr7 498 set_fr_iimmed 1,0xffff,fr8 499 cmmachs fr7,fr8,acc0,cc5,0 500 test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set 501 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set 502 test_spr_bits 1,0,1,msr0 ; msr0.aovf is set 503 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set 504 test_accg_immed 0x80,accg0 505 test_acc_immed 0,acc0 506 test_accg_immed 0x80,accg1 507 test_acc_immed 0,acc1 508 509 set_fr_iimmed 0x0000,0x8000,fr7 ; saturation 510 set_fr_iimmed 0x7fff,0x7fff,fr8 511 cmmachs fr7,fr8,acc0,cc5,0 512 test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set 513 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set 514 test_spr_bits 1,0,1,msr0 ; msr0.aovf is set 515 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set 516 test_accg_immed 0x80,accg0 517 test_acc_immed 0,acc0 518 test_accg_immed 0x80,accg1 519 test_acc_immed 0,acc1 520 521 ; Positive operands 522 set_spr_immed 0x0,msr0 523 set_accg_immed 0x0,accg0 524 set_acc_immed 0x0,acc0 525 set_accg_immed 0x0,accg1 526 set_acc_immed 0x0,acc1 527 set_fr_iimmed 2,3,fr7 ; multiply small numbers 528 set_fr_iimmed 3,2,fr8 529 cmmachs fr7,fr8,acc0,cc0,0 530 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 531 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 532 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 533 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 534 test_accg_immed 0,accg0 535 test_acc_immed 0,acc0 536 test_accg_immed 0,accg1 537 test_acc_immed 0,acc1 538 539 set_fr_iimmed 0,1,fr7 ; multiply by 0 540 set_fr_iimmed 2,0,fr8 541 cmmachs fr7,fr8,acc0,cc0,0 542 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 543 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 544 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 545 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 546 test_accg_immed 0,accg0 547 test_acc_immed 0,acc0 548 test_accg_immed 0,accg1 549 test_acc_immed 0,acc1 550 551 set_fr_iimmed 2,1,fr7 ; multiply by 1 552 set_fr_iimmed 1,2,fr8 553 cmmachs fr7,fr8,acc0,cc0,0 554 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 555 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 556 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 557 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 558 test_accg_immed 0,accg0 559 test_acc_immed 0,acc0 560 test_accg_immed 0,accg1 561 test_acc_immed 0,acc1 562 563 set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result 564 set_fr_iimmed 2,0x3fff,fr8 565 cmmachs fr7,fr8,acc0,cc0,0 566 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 567 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 568 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 569 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 570 test_accg_immed 0,accg0 571 test_acc_immed 0,acc0 572 test_accg_immed 0,accg1 573 test_acc_immed 0,acc1 574 575 set_fr_iimmed 0x4000,2,fr7 ; 16 bit result 576 set_fr_iimmed 2,0x4000,fr8 577 cmmachs fr7,fr8,acc0,cc0,0 578 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 579 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 580 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 581 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 582 test_accg_immed 0,accg0 583 test_acc_immed 0,acc0 584 test_accg_immed 0,accg1 585 test_acc_immed 0,acc1 586 587 set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result 588 set_fr_iimmed 0x7fff,0x7fff,fr8 589 cmmachs fr7,fr8,acc0,cc0,0 590 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 591 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 592 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 593 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 594 test_accg_immed 0,accg0 595 test_acc_immed 0,acc0 596 test_accg_immed 0,accg1 597 test_acc_immed 0,acc1 598 599 ; Mixed operands 600 set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers 601 set_fr_iimmed 0xfffd,2,fr8 602 cmmachs fr7,fr8,acc0,cc0,0 603 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 604 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 605 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 606 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 607 test_accg_immed 0,accg0 608 test_acc_immed 0,acc0 609 test_accg_immed 0,accg1 610 test_acc_immed 0,acc1 611 612 set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 613 set_fr_iimmed 1,0xfffe,fr8 614 cmmachs fr7,fr8,acc0,cc0,0 615 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 616 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 617 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 618 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 619 test_accg_immed 0,accg0 620 test_acc_immed 0,acc0 621 test_accg_immed 0,accg1 622 test_acc_immed 0,acc1 623 624 set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 625 set_fr_iimmed 0,0xfffe,fr8 626 cmmachs fr7,fr8,acc0,cc0,0 627 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 628 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 629 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 630 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 631 test_accg_immed 0,accg0 632 test_acc_immed 0,acc0 633 test_accg_immed 0,accg1 634 test_acc_immed 0,acc1 635 636 set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result 637 set_fr_iimmed 0xfffe,0x2001,fr8 638 cmmachs fr7,fr8,acc0,cc0,0 639 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 640 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 641 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 642 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 643 test_accg_immed 0,accg0 644 test_acc_immed 0,acc0 645 test_accg_immed 0,accg1 646 test_acc_immed 0,acc1 647 648 set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result 649 set_fr_iimmed 0xfffe,0x4000,fr8 650 cmmachs fr7,fr8,acc0,cc4,0 651 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 652 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 653 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 654 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 655 test_accg_immed 0,accg0 656 test_acc_immed 0,acc0 657 test_accg_immed 0,accg1 658 test_acc_immed 0,acc1 659 660 set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result 661 set_fr_iimmed 0x8000,0x7fff,fr8 662 cmmachs fr7,fr8,acc0,cc4,0 663 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 664 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 665 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 666 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 667 test_accg_immed 0,accg0 668 test_acc_immed 0,acc0 669 test_accg_immed 0,accg1 670 test_acc_immed 0,acc1 671 672 ; Negative operands 673 set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers 674 set_fr_iimmed 0xfffd,0xfffe,fr8 675 cmmachs fr7,fr8,acc0,cc4,0 676 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 677 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 678 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 679 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 680 test_accg_immed 0,accg0 681 test_acc_immed 0,acc0 682 test_accg_immed 0,accg1 683 test_acc_immed 0,acc1 684 685 set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 686 set_fr_iimmed 0xfffe,0xffff,fr8 687 cmmachs fr7,fr8,acc0,cc4,0 688 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 689 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 690 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 691 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 692 test_accg_immed 0,accg0 693 test_acc_immed 0,acc0 694 test_accg_immed 0,accg1 695 test_acc_immed 0,acc1 696 697 set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result 698 set_fr_iimmed 0x8001,0x8001,fr8 699 cmmachs fr7,fr8,acc0,cc4,0 700 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 701 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 702 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 703 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 704 test_accg_immed 0,accg0 705 test_acc_immed 0,acc0 706 test_accg_immed 0,accg1 707 test_acc_immed 0,acc1 708 709 set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result 710 set_fr_iimmed 0x8000,0x8000,fr8 711 cmmachs fr7,fr8,acc0,cc4,0 712 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 713 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 714 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 715 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 716 test_accg_immed 0,accg0 717 test_acc_immed 0,acc0 718 test_accg_immed 0,accg1 719 test_acc_immed 0,acc1 720 721 set_accg_immed 0x7f,accg0 ; saturation 722 set_acc_immed 0xffffffff,acc0 723 set_accg_immed 0x7f,accg1 724 set_acc_immed 0xffffffff,acc1 725 set_fr_iimmed 1,1,fr7 726 set_fr_iimmed 1,1,fr8 727 cmmachs fr7,fr8,acc0,cc4,0 728 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 729 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 730 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 731 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 732 test_accg_immed 0x7f,accg0 ; saturation 733 test_acc_immed 0xffffffff,acc0 734 test_accg_immed 0x7f,accg1 735 test_acc_immed 0xffffffff,acc1 736 737 set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation 738 set_fr_iimmed 0x7fff,0x7fff,fr8 739 cmmachs fr7,fr8,acc0,cc4,0 740 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 741 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 742 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 743 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 744 test_accg_immed 0x7f,accg0 ; saturation 745 test_acc_immed 0xffffffff,acc0 746 test_accg_immed 0x7f,accg1 747 test_acc_immed 0xffffffff,acc1 748 749 set_accg_immed 0x80,accg0 ; saturation 750 set_acc_immed 0,acc0 751 set_accg_immed 0x80,accg1 752 set_acc_immed 0,acc1 753 set_fr_iimmed 0xffff,0,fr7 754 set_fr_iimmed 1,0xffff,fr8 755 cmmachs fr7,fr8,acc0,cc4,0 756 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 757 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 758 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 759 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 760 test_accg_immed 0x80,accg0 ; saturation 761 test_acc_immed 0,acc0 762 test_accg_immed 0x80,accg1 763 test_acc_immed 0,acc1 764 765 set_fr_iimmed 0x0000,0x8000,fr7 ; saturation 766 set_fr_iimmed 0x7fff,0x7fff,fr8 767 cmmachs fr7,fr8,acc0,cc4,0 768 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 769 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 770 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 771 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 772 test_accg_immed 0x80,accg0 ; saturation 773 test_acc_immed 0,acc0 774 test_accg_immed 0x80,accg1 775 test_acc_immed 0,acc1 776 777 ; Positive operands 778 set_spr_immed 0x0,msr0 779 set_accg_immed 0x0,accg0 780 set_acc_immed 0x0,acc0 781 set_accg_immed 0x0,accg1 782 set_acc_immed 0x0,acc1 783 set_fr_iimmed 2,3,fr7 ; multiply small numbers 784 set_fr_iimmed 3,2,fr8 785 cmmachs fr7,fr8,acc0,cc1,1 786 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 787 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 788 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 789 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 790 test_accg_immed 0,accg0 791 test_acc_immed 0,acc0 792 test_accg_immed 0,accg1 793 test_acc_immed 0,acc1 794 795 set_fr_iimmed 0,1,fr7 ; multiply by 0 796 set_fr_iimmed 2,0,fr8 797 cmmachs fr7,fr8,acc0,cc1,1 798 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 799 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 800 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 801 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 802 test_accg_immed 0,accg0 803 test_acc_immed 0,acc0 804 test_accg_immed 0,accg1 805 test_acc_immed 0,acc1 806 807 set_fr_iimmed 2,1,fr7 ; multiply by 1 808 set_fr_iimmed 1,2,fr8 809 cmmachs fr7,fr8,acc0,cc1,1 810 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 811 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 812 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 813 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 814 test_accg_immed 0,accg0 815 test_acc_immed 0,acc0 816 test_accg_immed 0,accg1 817 test_acc_immed 0,acc1 818 819 set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result 820 set_fr_iimmed 2,0x3fff,fr8 821 cmmachs fr7,fr8,acc0,cc1,1 822 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 823 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 824 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 825 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 826 test_accg_immed 0,accg0 827 test_acc_immed 0,acc0 828 test_accg_immed 0,accg1 829 test_acc_immed 0,acc1 830 831 set_fr_iimmed 0x4000,2,fr7 ; 16 bit result 832 set_fr_iimmed 2,0x4000,fr8 833 cmmachs fr7,fr8,acc0,cc1,1 834 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 835 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 836 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 837 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 838 test_accg_immed 0,accg0 839 test_acc_immed 0,acc0 840 test_accg_immed 0,accg1 841 test_acc_immed 0,acc1 842 843 set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result 844 set_fr_iimmed 0x7fff,0x7fff,fr8 845 cmmachs fr7,fr8,acc0,cc1,1 846 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 847 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 848 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 849 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 850 test_accg_immed 0,accg0 851 test_acc_immed 0,acc0 852 test_accg_immed 0,accg1 853 test_acc_immed 0,acc1 854 855 ; Mixed operands 856 set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers 857 set_fr_iimmed 0xfffd,2,fr8 858 cmmachs fr7,fr8,acc0,cc1,1 859 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 860 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 861 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 862 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 863 test_accg_immed 0,accg0 864 test_acc_immed 0,acc0 865 test_accg_immed 0,accg1 866 test_acc_immed 0,acc1 867 868 set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 869 set_fr_iimmed 1,0xfffe,fr8 870 cmmachs fr7,fr8,acc0,cc1,1 871 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 872 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 873 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 874 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 875 test_accg_immed 0,accg0 876 test_acc_immed 0,acc0 877 test_accg_immed 0,accg1 878 test_acc_immed 0,acc1 879 880 set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 881 set_fr_iimmed 0,0xfffe,fr8 882 cmmachs fr7,fr8,acc0,cc1,1 883 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 884 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 885 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 886 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 887 test_accg_immed 0,accg0 888 test_acc_immed 0,acc0 889 test_accg_immed 0,accg1 890 test_acc_immed 0,acc1 891 892 set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result 893 set_fr_iimmed 0xfffe,0x2001,fr8 894 cmmachs fr7,fr8,acc0,cc1,1 895 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 896 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 897 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 898 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 899 test_accg_immed 0,accg0 900 test_acc_immed 0,acc0 901 test_accg_immed 0,accg1 902 test_acc_immed 0,acc1 903 904 set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result 905 set_fr_iimmed 0xfffe,0x4000,fr8 906 cmmachs fr7,fr8,acc0,cc5,1 907 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 908 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 909 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 910 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 911 test_accg_immed 0,accg0 912 test_acc_immed 0,acc0 913 test_accg_immed 0,accg1 914 test_acc_immed 0,acc1 915 916 set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result 917 set_fr_iimmed 0x8000,0x7fff,fr8 918 cmmachs fr7,fr8,acc0,cc5,1 919 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 920 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 921 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 922 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 923 test_accg_immed 0,accg0 924 test_acc_immed 0,acc0 925 test_accg_immed 0,accg1 926 test_acc_immed 0,acc1 927 928 ; Negative operands 929 set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers 930 set_fr_iimmed 0xfffd,0xfffe,fr8 931 cmmachs fr7,fr8,acc0,cc5,1 932 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 933 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 934 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 935 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 936 test_accg_immed 0,accg0 937 test_acc_immed 0,acc0 938 test_accg_immed 0,accg1 939 test_acc_immed 0,acc1 940 941 set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 942 set_fr_iimmed 0xfffe,0xffff,fr8 943 cmmachs fr7,fr8,acc0,cc5,1 944 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 945 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 946 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 947 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 948 test_accg_immed 0,accg0 949 test_acc_immed 0,acc0 950 test_accg_immed 0,accg1 951 test_acc_immed 0,acc1 952 953 set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result 954 set_fr_iimmed 0x8001,0x8001,fr8 955 cmmachs fr7,fr8,acc0,cc5,1 956 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 957 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 958 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 959 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 960 test_accg_immed 0,accg0 961 test_acc_immed 0,acc0 962 test_accg_immed 0,accg1 963 test_acc_immed 0,acc1 964 965 set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result 966 set_fr_iimmed 0x8000,0x8000,fr8 967 cmmachs fr7,fr8,acc0,cc5,1 968 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 969 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 970 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 971 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 972 test_accg_immed 0,accg0 973 test_acc_immed 0,acc0 974 test_accg_immed 0,accg1 975 test_acc_immed 0,acc1 976 977 set_accg_immed 0x7f,accg0 ; saturation 978 set_acc_immed 0xffffffff,acc0 979 set_accg_immed 0x7f,accg1 980 set_acc_immed 0xffffffff,acc1 981 set_fr_iimmed 1,1,fr7 982 set_fr_iimmed 1,1,fr8 983 cmmachs fr7,fr8,acc0,cc5,1 984 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 985 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 986 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 987 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 988 test_accg_immed 0x7f,accg0 ; saturation 989 test_acc_immed 0xffffffff,acc0 990 test_accg_immed 0x7f,accg1 991 test_acc_immed 0xffffffff,acc1 992 993 set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation 994 set_fr_iimmed 0x7fff,0x7fff,fr8 995 cmmachs fr7,fr8,acc0,cc5,1 996 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 997 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 998 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 999 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1000 test_accg_immed 0x7f,accg0 ; saturation 1001 test_acc_immed 0xffffffff,acc0 1002 test_accg_immed 0x7f,accg1 1003 test_acc_immed 0xffffffff,acc1 1004 1005 set_accg_immed 0x80,accg0 ; saturation 1006 set_acc_immed 0,acc0 1007 set_accg_immed 0x80,accg1 1008 set_acc_immed 0,acc1 1009 set_fr_iimmed 0xffff,0,fr7 1010 set_fr_iimmed 1,0xffff,fr8 1011 cmmachs fr7,fr8,acc0,cc5,1 1012 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1013 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1014 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1015 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1016 test_accg_immed 0x80,accg0 ; saturation 1017 test_acc_immed 0,acc0 1018 test_accg_immed 0x80,accg1 1019 test_acc_immed 0,acc1 1020 1021 set_fr_iimmed 0x0000,0x8000,fr7 ; saturation 1022 set_fr_iimmed 0x7fff,0x7fff,fr8 1023 cmmachs fr7,fr8,acc0,cc5,1 1024 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1025 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1026 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1027 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1028 test_accg_immed 0x80,accg0 ; saturation 1029 test_acc_immed 0,acc0 1030 test_accg_immed 0x80,accg1 1031 test_acc_immed 0,acc1 1032 1033 ; Positive operands 1034 set_spr_immed 0x0,msr0 1035 set_accg_immed 0x0,accg0 1036 set_acc_immed 0x0,acc0 1037 set_accg_immed 0x0,accg1 1038 set_acc_immed 0x0,acc1 1039 set_fr_iimmed 2,3,fr7 ; multiply small numbers 1040 set_fr_iimmed 3,2,fr8 1041 cmmachs fr7,fr8,acc0,cc2,1 1042 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1043 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1044 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1045 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1046 test_accg_immed 0,accg0 1047 test_acc_immed 0,acc0 1048 test_accg_immed 0,accg1 1049 test_acc_immed 0,acc1 1050 1051 set_fr_iimmed 0,1,fr7 ; multiply by 0 1052 set_fr_iimmed 2,0,fr8 1053 cmmachs fr7,fr8,acc0,cc2,0 1054 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1055 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1056 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1057 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1058 test_accg_immed 0,accg0 1059 test_acc_immed 0,acc0 1060 test_accg_immed 0,accg1 1061 test_acc_immed 0,acc1 1062 1063 set_fr_iimmed 2,1,fr7 ; multiply by 1 1064 set_fr_iimmed 1,2,fr8 1065 cmmachs fr7,fr8,acc0,cc2,1 1066 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1067 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1068 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1069 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1070 test_accg_immed 0,accg0 1071 test_acc_immed 0,acc0 1072 test_accg_immed 0,accg1 1073 test_acc_immed 0,acc1 1074 1075 set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result 1076 set_fr_iimmed 2,0x3fff,fr8 1077 cmmachs fr7,fr8,acc0,cc2,0 1078 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1079 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1080 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1081 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1082 test_accg_immed 0,accg0 1083 test_acc_immed 0,acc0 1084 test_accg_immed 0,accg1 1085 test_acc_immed 0,acc1 1086 1087 set_fr_iimmed 0x4000,2,fr7 ; 16 bit result 1088 set_fr_iimmed 2,0x4000,fr8 1089 cmmachs fr7,fr8,acc0,cc2,1 1090 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1091 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1092 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1093 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1094 test_accg_immed 0,accg0 1095 test_acc_immed 0,acc0 1096 test_accg_immed 0,accg1 1097 test_acc_immed 0,acc1 1098 1099 set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result 1100 set_fr_iimmed 0x7fff,0x7fff,fr8 1101 cmmachs fr7,fr8,acc0,cc2,0 1102 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1103 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1104 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1105 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1106 test_accg_immed 0,accg0 1107 test_acc_immed 0,acc0 1108 test_accg_immed 0,accg1 1109 test_acc_immed 0,acc1 1110 1111 ; Mixed operands 1112 set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers 1113 set_fr_iimmed 0xfffd,2,fr8 1114 cmmachs fr7,fr8,acc0,cc2,1 1115 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1116 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1117 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1118 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1119 test_accg_immed 0,accg0 1120 test_acc_immed 0,acc0 1121 test_accg_immed 0,accg1 1122 test_acc_immed 0,acc1 1123 1124 set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 1125 set_fr_iimmed 1,0xfffe,fr8 1126 cmmachs fr7,fr8,acc0,cc2,0 1127 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1128 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1129 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1130 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1131 test_accg_immed 0,accg0 1132 test_acc_immed 0,acc0 1133 test_accg_immed 0,accg1 1134 test_acc_immed 0,acc1 1135 1136 set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 1137 set_fr_iimmed 0,0xfffe,fr8 1138 cmmachs fr7,fr8,acc0,cc2,1 1139 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1140 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1141 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1142 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1143 test_accg_immed 0,accg0 1144 test_acc_immed 0,acc0 1145 test_accg_immed 0,accg1 1146 test_acc_immed 0,acc1 1147 1148 set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result 1149 set_fr_iimmed 0xfffe,0x2001,fr8 1150 cmmachs fr7,fr8,acc0,cc2,0 1151 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1152 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1153 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1154 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1155 test_accg_immed 0,accg0 1156 test_acc_immed 0,acc0 1157 test_accg_immed 0,accg1 1158 test_acc_immed 0,acc1 1159 1160 set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result 1161 set_fr_iimmed 0xfffe,0x4000,fr8 1162 cmmachs fr7,fr8,acc0,cc6,1 1163 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1164 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1165 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1166 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1167 test_accg_immed 0,accg0 1168 test_acc_immed 0,acc0 1169 test_accg_immed 0,accg1 1170 test_acc_immed 0,acc1 1171 1172 set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result 1173 set_fr_iimmed 0x8000,0x7fff,fr8 1174 cmmachs fr7,fr8,acc0,cc6,0 1175 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1176 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1177 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1178 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1179 test_accg_immed 0,accg0 1180 test_acc_immed 0,acc0 1181 test_accg_immed 0,accg1 1182 test_acc_immed 0,acc1 1183 1184 ; Negative operands 1185 set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers 1186 set_fr_iimmed 0xfffd,0xfffe,fr8 1187 cmmachs fr7,fr8,acc0,cc6,1 1188 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1189 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1190 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1191 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1192 test_accg_immed 0,accg0 1193 test_acc_immed 0,acc0 1194 test_accg_immed 0,accg1 1195 test_acc_immed 0,acc1 1196 1197 set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 1198 set_fr_iimmed 0xfffe,0xffff,fr8 1199 cmmachs fr7,fr8,acc0,cc6,0 1200 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1201 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1202 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1203 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1204 test_accg_immed 0,accg0 1205 test_acc_immed 0,acc0 1206 test_accg_immed 0,accg1 1207 test_acc_immed 0,acc1 1208 1209 set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result 1210 set_fr_iimmed 0x8001,0x8001,fr8 1211 cmmachs fr7,fr8,acc0,cc6,1 1212 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1213 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1214 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1215 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1216 test_accg_immed 0,accg0 1217 test_acc_immed 0,acc0 1218 test_accg_immed 0,accg1 1219 test_acc_immed 0,acc1 1220 1221 set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result 1222 set_fr_iimmed 0x8000,0x8000,fr8 1223 cmmachs fr7,fr8,acc0,cc6,0 1224 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1225 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1226 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1227 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1228 test_accg_immed 0,accg0 1229 test_acc_immed 0,acc0 1230 test_accg_immed 0,accg1 1231 test_acc_immed 0,acc1 1232 1233 set_accg_immed 0x7f,accg0 ; saturation 1234 set_acc_immed 0xffffffff,acc0 1235 set_accg_immed 0x7f,accg1 1236 set_acc_immed 0xffffffff,acc1 1237 set_fr_iimmed 1,1,fr7 1238 set_fr_iimmed 1,1,fr8 1239 cmmachs fr7,fr8,acc0,cc6,1 1240 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1241 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1242 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1243 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1244 test_accg_immed 0x7f,accg0 ; saturation 1245 test_acc_immed 0xffffffff,acc0 1246 test_accg_immed 0x7f,accg1 1247 test_acc_immed 0xffffffff,acc1 1248 1249 set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation 1250 set_fr_iimmed 0x7fff,0x7fff,fr8 1251 cmmachs fr7,fr8,acc0,cc6,0 1252 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1253 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1254 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1255 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1256 test_accg_immed 0x7f,accg0 ; saturation 1257 test_acc_immed 0xffffffff,acc0 1258 test_accg_immed 0x7f,accg1 1259 test_acc_immed 0xffffffff,acc1 1260 1261 set_accg_immed 0x80,accg0 ; saturation 1262 set_acc_immed 0,acc0 1263 set_accg_immed 0x80,accg1 1264 set_acc_immed 0,acc1 1265 set_fr_iimmed 0xffff,0,fr7 1266 set_fr_iimmed 1,0xffff,fr8 1267 cmmachs fr7,fr8,acc0,cc6,1 1268 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1269 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1270 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1271 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1272 test_accg_immed 0x80,accg0 ; saturation 1273 test_acc_immed 0,acc0 1274 test_accg_immed 0x80,accg1 1275 test_acc_immed 0,acc1 1276 1277 set_fr_iimmed 0x0000,0x8000,fr7 ; saturation 1278 set_fr_iimmed 0x7fff,0x7fff,fr8 1279 cmmachs fr7,fr8,acc0,cc6,0 1280 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1281 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1282 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1283 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1284 test_accg_immed 0x80,accg0 ; saturation 1285 test_acc_immed 0,acc0 1286 test_accg_immed 0x80,accg1 1287 test_acc_immed 0,acc1 1288; 1289 ; Positive operands 1290 set_spr_immed 0x0,msr0 1291 set_accg_immed 0x0,accg0 1292 set_acc_immed 0x0,acc0 1293 set_accg_immed 0x0,accg1 1294 set_acc_immed 0x0,acc1 1295 set_fr_iimmed 2,3,fr7 ; multiply small numbers 1296 set_fr_iimmed 3,2,fr8 1297 cmmachs fr7,fr8,acc0,cc3,1 1298 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1299 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1300 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1301 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1302 test_accg_immed 0,accg0 1303 test_acc_immed 0,acc0 1304 test_accg_immed 0,accg1 1305 test_acc_immed 0,acc1 1306 1307 set_fr_iimmed 0,1,fr7 ; multiply by 0 1308 set_fr_iimmed 2,0,fr8 1309 cmmachs fr7,fr8,acc0,cc3,0 1310 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1311 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1312 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1313 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1314 test_accg_immed 0,accg0 1315 test_acc_immed 0,acc0 1316 test_accg_immed 0,accg1 1317 test_acc_immed 0,acc1 1318 1319 set_fr_iimmed 2,1,fr7 ; multiply by 1 1320 set_fr_iimmed 1,2,fr8 1321 cmmachs fr7,fr8,acc0,cc3,1 1322 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1323 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1324 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1325 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1326 test_accg_immed 0,accg0 1327 test_acc_immed 0,acc0 1328 test_accg_immed 0,accg1 1329 test_acc_immed 0,acc1 1330 1331 set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result 1332 set_fr_iimmed 2,0x3fff,fr8 1333 cmmachs fr7,fr8,acc0,cc3,0 1334 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1335 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1336 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1337 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1338 test_accg_immed 0,accg0 1339 test_acc_immed 0,acc0 1340 test_accg_immed 0,accg1 1341 test_acc_immed 0,acc1 1342 1343 set_fr_iimmed 0x4000,2,fr7 ; 16 bit result 1344 set_fr_iimmed 2,0x4000,fr8 1345 cmmachs fr7,fr8,acc0,cc3,1 1346 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1347 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1348 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1349 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1350 test_accg_immed 0,accg0 1351 test_acc_immed 0,acc0 1352 test_accg_immed 0,accg1 1353 test_acc_immed 0,acc1 1354 1355 set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result 1356 set_fr_iimmed 0x7fff,0x7fff,fr8 1357 cmmachs fr7,fr8,acc0,cc3,0 1358 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1359 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1360 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1361 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1362 test_accg_immed 0,accg0 1363 test_acc_immed 0,acc0 1364 test_accg_immed 0,accg1 1365 test_acc_immed 0,acc1 1366 1367 ; Mixed operands 1368 set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers 1369 set_fr_iimmed 0xfffd,2,fr8 1370 cmmachs fr7,fr8,acc0,cc3,1 1371 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1372 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1373 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1374 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1375 test_accg_immed 0,accg0 1376 test_acc_immed 0,acc0 1377 test_accg_immed 0,accg1 1378 test_acc_immed 0,acc1 1379 1380 set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 1381 set_fr_iimmed 1,0xfffe,fr8 1382 cmmachs fr7,fr8,acc0,cc3,0 1383 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1384 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1385 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1386 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1387 test_accg_immed 0,accg0 1388 test_acc_immed 0,acc0 1389 test_accg_immed 0,accg1 1390 test_acc_immed 0,acc1 1391 1392 set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 1393 set_fr_iimmed 0,0xfffe,fr8 1394 cmmachs fr7,fr8,acc0,cc3,1 1395 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1396 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1397 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1398 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1399 test_accg_immed 0,accg0 1400 test_acc_immed 0,acc0 1401 test_accg_immed 0,accg1 1402 test_acc_immed 0,acc1 1403 1404 set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result 1405 set_fr_iimmed 0xfffe,0x2001,fr8 1406 cmmachs fr7,fr8,acc0,cc3,0 1407 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1408 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1409 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1410 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1411 test_accg_immed 0,accg0 1412 test_acc_immed 0,acc0 1413 test_accg_immed 0,accg1 1414 test_acc_immed 0,acc1 1415 1416 set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result 1417 set_fr_iimmed 0xfffe,0x4000,fr8 1418 cmmachs fr7,fr8,acc0,cc7,1 1419 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1420 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1421 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1422 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1423 test_accg_immed 0,accg0 1424 test_acc_immed 0,acc0 1425 test_accg_immed 0,accg1 1426 test_acc_immed 0,acc1 1427 1428 set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result 1429 set_fr_iimmed 0x8000,0x7fff,fr8 1430 cmmachs fr7,fr8,acc0,cc7,0 1431 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1432 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1433 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1434 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1435 test_accg_immed 0,accg0 1436 test_acc_immed 0,acc0 1437 test_accg_immed 0,accg1 1438 test_acc_immed 0,acc1 1439 1440 ; Negative operands 1441 set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers 1442 set_fr_iimmed 0xfffd,0xfffe,fr8 1443 cmmachs fr7,fr8,acc0,cc7,1 1444 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1445 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1446 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1447 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1448 test_accg_immed 0,accg0 1449 test_acc_immed 0,acc0 1450 test_accg_immed 0,accg1 1451 test_acc_immed 0,acc1 1452 1453 set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 1454 set_fr_iimmed 0xfffe,0xffff,fr8 1455 cmmachs fr7,fr8,acc0,cc7,0 1456 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1457 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1458 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1459 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1460 test_accg_immed 0,accg0 1461 test_acc_immed 0,acc0 1462 test_accg_immed 0,accg1 1463 test_acc_immed 0,acc1 1464 1465 set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result 1466 set_fr_iimmed 0x8001,0x8001,fr8 1467 cmmachs fr7,fr8,acc0,cc7,1 1468 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1469 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1470 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1471 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1472 test_accg_immed 0,accg0 1473 test_acc_immed 0,acc0 1474 test_accg_immed 0,accg1 1475 test_acc_immed 0,acc1 1476 1477 set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result 1478 set_fr_iimmed 0x8000,0x8000,fr8 1479 cmmachs fr7,fr8,acc0,cc7,0 1480 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1481 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1482 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1483 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1484 test_accg_immed 0,accg0 1485 test_acc_immed 0,acc0 1486 test_accg_immed 0,accg1 1487 test_acc_immed 0,acc1 1488 1489 set_accg_immed 0x7f,accg0 ; saturation 1490 set_acc_immed 0xffffffff,acc0 1491 set_accg_immed 0x7f,accg1 1492 set_acc_immed 0xffffffff,acc1 1493 set_fr_iimmed 1,1,fr7 1494 set_fr_iimmed 1,1,fr8 1495 cmmachs fr7,fr8,acc0,cc7,1 1496 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1497 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1498 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1499 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1500 test_accg_immed 0x7f,accg0 ; saturation 1501 test_acc_immed 0xffffffff,acc0 1502 test_accg_immed 0x7f,accg1 1503 test_acc_immed 0xffffffff,acc1 1504 1505 set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation 1506 set_fr_iimmed 0x7fff,0x7fff,fr8 1507 cmmachs fr7,fr8,acc0,cc7,0 1508 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1509 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1510 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1511 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1512 test_accg_immed 0x7f,accg0 ; saturation 1513 test_acc_immed 0xffffffff,acc0 1514 test_accg_immed 0x7f,accg1 1515 test_acc_immed 0xffffffff,acc1 1516 1517 set_accg_immed 0x80,accg0 ; saturation 1518 set_acc_immed 0,acc0 1519 set_accg_immed 0x80,accg1 1520 set_acc_immed 0,acc1 1521 set_fr_iimmed 0xffff,0,fr7 1522 set_fr_iimmed 1,0xffff,fr8 1523 cmmachs fr7,fr8,acc0,cc7,1 1524 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1525 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1526 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1527 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1528 test_accg_immed 0x80,accg0 ; saturation 1529 test_acc_immed 0,acc0 1530 test_accg_immed 0x80,accg1 1531 test_acc_immed 0,acc1 1532 1533 set_fr_iimmed 0x0000,0x8000,fr7 ; saturation 1534 set_fr_iimmed 0x7fff,0x7fff,fr8 1535 cmmachs fr7,fr8,acc0,cc7,0 1536 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1537 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1538 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1539 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 1540 test_accg_immed 0x80,accg0 ; saturation 1541 test_acc_immed 0,acc0 1542 test_accg_immed 0x80,accg1 1543 test_acc_immed 0,acc1 1544 1545 pass 1546