1# frv testcase for cmmachs $GRi,$GRj,$ACCk,$CCi,$cond 2# mach: frv fr500 fr400 3 4 .include "testutils.inc" 5 6 start 7 8 .global cmmachs 9cmmachs: 10 set_spr_immed 0x1b1b,cccr 11 12 ; Positive operands 13 set_spr_immed 0x0,msr0 14 set_spr_immed 0x0,msr1 15 set_accg_immed 0x0,accg0 16 set_acc_immed 0x0,acc0 17 set_accg_immed 0x0,accg1 18 set_acc_immed 0x0,acc1 19 set_fr_iimmed 2,3,fr7 ; multiply small numbers 20 set_fr_iimmed 3,2,fr8 21 cmmachs fr7,fr8,acc0,cc0,1 22 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 23 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 24 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 25 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 26 test_accg_immed 0,accg0 27 test_acc_immed 6,acc0 28 test_accg_immed 0,accg1 29 test_acc_immed 6,acc1 30 31 set_fr_iimmed 0,1,fr7 ; multiply by 0 32 set_fr_iimmed 2,0,fr8 33 cmmachs fr7,fr8,acc0,cc0,1 34 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 35 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 36 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 37 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 38 test_accg_immed 0,accg0 39 test_acc_immed 6,acc0 40 test_accg_immed 0,accg1 41 test_acc_immed 6,acc1 42 43 set_fr_iimmed 2,1,fr7 ; multiply by 1 44 set_fr_iimmed 1,2,fr8 45 cmmachs fr7,fr8,acc0,cc0,1 46 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 47 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 48 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 49 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 50 test_accg_immed 0,accg0 51 test_acc_immed 8,acc0 52 test_accg_immed 0,accg1 53 test_acc_immed 8,acc1 54 55 set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result 56 set_fr_iimmed 2,0x3fff,fr8 57 cmmachs fr7,fr8,acc0,cc0,1 58 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 59 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 60 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 61 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 62 test_accg_immed 0,accg0 63 test_acc_limmed 0,0x8006,acc0 64 test_accg_immed 0,accg1 65 test_acc_limmed 0,0x8006,acc1 66 67 set_fr_iimmed 0x4000,2,fr7 ; 16 bit result 68 set_fr_iimmed 2,0x4000,fr8 69 cmmachs fr7,fr8,acc0,cc0,1 70 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 71 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 72 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 73 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 74 test_accg_immed 0,accg0 75 test_acc_limmed 0x0001,0x0006,acc0 76 test_accg_immed 0,accg1 77 test_acc_limmed 0x0001,0x0006,acc1 78 79 set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result 80 set_fr_iimmed 0x7fff,0x7fff,fr8 81 cmmachs fr7,fr8,acc0,cc0,1 82 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 83 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 84 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 85 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 86 test_accg_immed 0,accg0 87 test_acc_limmed 0x4000,0x0007,acc0 88 test_accg_immed 0,accg1 89 test_acc_limmed 0x4000,0x0007,acc1 90 91 ; Mixed operands 92 set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers 93 set_fr_iimmed 0xfffd,2,fr8 94 cmmachs fr7,fr8,acc0,cc0,1 95 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 96 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 97 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 98 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 99 test_accg_immed 0,accg0 100 test_acc_limmed 0x4000,0x0001,acc0 101 test_accg_immed 0,accg1 102 test_acc_limmed 0x4000,0x0001,acc1 103 104 set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 105 set_fr_iimmed 1,0xfffe,fr8 106 cmmachs fr7,fr8,acc0,cc0,1 107 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 108 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 109 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 110 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 111 test_accg_immed 0,accg0 112 test_acc_limmed 0x3fff,0xffff,acc0 113 test_accg_immed 0,accg1 114 test_acc_limmed 0x3fff,0xffff,acc1 115 116 set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 117 set_fr_iimmed 0,0xfffe,fr8 118 cmmachs fr7,fr8,acc0,cc0,1 119 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 120 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 121 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 122 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 123 test_accg_immed 0,accg0 124 test_acc_limmed 0x3fff,0xffff,acc0 125 test_accg_immed 0,accg1 126 test_acc_limmed 0x3fff,0xffff,acc1 127 128 set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result 129 set_fr_iimmed 0xfffe,0x2001,fr8 130 cmmachs fr7,fr8,acc0,cc0,1 131 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 132 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 133 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 134 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 135 test_accg_immed 0,accg0 136 test_acc_limmed 0x3fff,0xbffd,acc0 137 test_accg_immed 0,accg1 138 test_acc_limmed 0x3fff,0xbffd,acc1 139 140 set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result 141 set_fr_iimmed 0xfffe,0x4000,fr8 142 cmmachs fr7,fr8,acc0,cc4,1 143 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 144 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 145 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 146 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 147 test_accg_immed 0,accg0 148 test_acc_limmed 0x3fff,0x3ffd,acc0 149 test_accg_immed 0,accg1 150 test_acc_limmed 0x3fff,0x3ffd,acc1 151 152 set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result 153 set_fr_iimmed 0x8000,0x7fff,fr8 154 cmmachs fr7,fr8,acc0,cc4,1 155 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 156 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 157 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 158 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 159 test_accg_immed 0xff,accg0 160 test_acc_limmed 0xffff,0xbffd,acc0 161 test_accg_immed 0xff,accg1 162 test_acc_limmed 0xffff,0xbffd,acc1 163 164 ; Negative operands 165 set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers 166 set_fr_iimmed 0xfffd,0xfffe,fr8 167 cmmachs fr7,fr8,acc0,cc4,1 168 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 169 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 170 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 171 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 172 test_accg_immed 0xff,accg0 173 test_acc_limmed 0xffff,0xc003,acc0 174 test_accg_immed 0xff,accg1 175 test_acc_limmed 0xffff,0xc003,acc1 176 177 set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 178 set_fr_iimmed 0xfffe,0xffff,fr8 179 cmmachs fr7,fr8,acc0,cc4,1 180 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 181 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 182 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 183 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 184 test_accg_immed 0xff,accg0 185 test_acc_limmed 0xffff,0xc005,acc0 186 test_accg_immed 0xff,accg1 187 test_acc_limmed 0xffff,0xc005,acc1 188 189 set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result 190 set_fr_iimmed 0x8001,0x8001,fr8 191 cmmachs fr7,fr8,acc0,cc4,1 192 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 193 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 194 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 195 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 196 test_accg_immed 0,accg0 197 test_acc_immed 0x3ffec006,acc0 198 test_accg_immed 0,accg1 199 test_acc_immed 0x3ffec006,acc1 200 201 set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result 202 set_fr_iimmed 0x8000,0x8000,fr8 203 cmmachs fr7,fr8,acc0,cc4,1 204 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 205 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 206 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 207 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 208 test_accg_immed 0,accg0 209 test_acc_immed 0x7ffec006,acc0 210 test_accg_immed 0,accg1 211 test_acc_immed 0x7ffec006,acc1 212 213 set_accg_immed 0x7f,accg0 ; saturation 214 set_acc_immed 0xffffffff,acc0 215 set_accg_immed 0x7f,accg1 216 set_acc_immed 0xffffffff,acc1 217 set_fr_iimmed 1,1,fr7 218 set_fr_iimmed 1,1,fr8 219 cmmachs fr7,fr8,acc0,cc4,1 220;;;;;;;;;;;; 221 test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set 222 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set 223 test_spr_bits 1,0,1,msr0 ; msr0.aovf is set 224 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set 225 test_accg_immed 0x7f,accg0 226 test_acc_limmed 0xffff,0xffff,acc0 227 test_accg_immed 0x7f,accg1 228 test_acc_limmed 0xffff,0xffff,acc1 229 230 set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation 231 set_fr_iimmed 0x7fff,0x7fff,fr8 232 cmmachs fr7,fr8,acc0,cc4,1 233 test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set 234 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set 235 test_spr_bits 1,0,1,msr0 ; msr0.aovf is set 236 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set 237 test_accg_immed 0x7f,accg0 238 test_acc_limmed 0xffff,0xffff,acc0 239 test_accg_immed 0x7f,accg1 240 test_acc_limmed 0xffff,0xffff,acc1 241 242 set_accg_immed -128,accg0 ; saturation 243 set_acc_immed 0,acc0 244 set_accg_immed -128,accg1 245 set_acc_immed 0,acc1 246 set_fr_iimmed 0xffff,0,fr7 247 set_fr_iimmed 1,0xffff,fr8 248 cmmachs fr7,fr8,acc0,cc4,1 249 test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set 250 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set 251 test_spr_bits 1,0,1,msr0 ; msr0.aovf is set 252 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set 253 test_accg_immed 0x80,accg0 254 test_acc_immed 0,acc0 255 test_accg_immed 0x80,accg1 256 test_acc_immed 0,acc1 257 258 set_fr_iimmed 0x0000,0x8000,fr7 ; saturation 259 set_fr_iimmed 0x7fff,0x7fff,fr8 260 cmmachs fr7,fr8,acc0,cc4,1 261 test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set 262 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set 263 test_spr_bits 1,0,1,msr0 ; msr0.aovf is set 264 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set 265 test_accg_immed 0x80,accg0 266 test_acc_immed 0,acc0 267 test_accg_immed 0x80,accg1 268 test_acc_immed 0,acc1 269 270 ; Positive operands 271 set_spr_immed 0x0,msr0 272 set_spr_immed 0x0,msr1 273 set_accg_immed 0x0,accg0 ; saturation 274 set_acc_immed 0x0,acc0 275 set_accg_immed 0x0,accg1 276 set_acc_immed 0x0,acc1 277 set_fr_iimmed 2,3,fr7 ; multiply small numbers 278 set_fr_iimmed 3,2,fr8 279 cmmachs fr7,fr8,acc0,cc1,0 280 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 281 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 282 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 283 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 284 test_accg_immed 0,accg0 285 test_acc_immed 6,acc0 286 test_accg_immed 0,accg1 287 test_acc_immed 6,acc1 288 289 set_fr_iimmed 0,1,fr7 ; multiply by 0 290 set_fr_iimmed 2,0,fr8 291 cmmachs fr7,fr8,acc0,cc1,0 292 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 293 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 294 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 295 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 296 test_accg_immed 0,accg0 297 test_acc_immed 6,acc0 298 test_accg_immed 0,accg1 299 test_acc_immed 6,acc1 300 301 set_fr_iimmed 2,1,fr7 ; multiply by 1 302 set_fr_iimmed 1,2,fr8 303 cmmachs fr7,fr8,acc0,cc1,0 304 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 305 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 306 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 307 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 308 test_accg_immed 0,accg0 309 test_acc_immed 8,acc0 310 test_accg_immed 0,accg1 311 test_acc_immed 8,acc1 312 313 set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result 314 set_fr_iimmed 2,0x3fff,fr8 315 cmmachs fr7,fr8,acc0,cc1,0 316 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 317 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 318 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 319 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 320 test_accg_immed 0,accg0 321 test_acc_limmed 0,0x8006,acc0 322 test_accg_immed 0,accg1 323 test_acc_limmed 0,0x8006,acc1 324 325 set_fr_iimmed 0x4000,2,fr7 ; 16 bit result 326 set_fr_iimmed 2,0x4000,fr8 327 cmmachs fr7,fr8,acc0,cc1,0 328 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 329 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 330 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 331 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 332 test_accg_immed 0,accg0 333 test_acc_limmed 0x0001,0x0006,acc0 334 test_accg_immed 0,accg1 335 test_acc_limmed 0x0001,0x0006,acc1 336 337 set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result 338 set_fr_iimmed 0x7fff,0x7fff,fr8 339 cmmachs fr7,fr8,acc0,cc1,0 340 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 341 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 342 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 343 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 344 test_accg_immed 0,accg0 345 test_acc_limmed 0x4000,0x0007,acc0 346 test_accg_immed 0,accg1 347 test_acc_limmed 0x4000,0x0007,acc1 348 349 ; Mixed operands 350 set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers 351 set_fr_iimmed 0xfffd,2,fr8 352 cmmachs fr7,fr8,acc0,cc1,0 353 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 354 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 355 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 356 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 357 test_accg_immed 0,accg0 358 test_acc_limmed 0x4000,0x0001,acc0 359 test_accg_immed 0,accg1 360 test_acc_limmed 0x4000,0x0001,acc1 361 362 set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 363 set_fr_iimmed 1,0xfffe,fr8 364 cmmachs fr7,fr8,acc0,cc1,0 365 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 366 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 367 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 368 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 369 test_accg_immed 0,accg0 370 test_acc_limmed 0x3fff,0xffff,acc0 371 test_accg_immed 0,accg1 372 test_acc_limmed 0x3fff,0xffff,acc1 373 374 set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 375 set_fr_iimmed 0,0xfffe,fr8 376 cmmachs fr7,fr8,acc0,cc1,0 377 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 378 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 379 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 380 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 381 test_accg_immed 0,accg0 382 test_acc_limmed 0x3fff,0xffff,acc0 383 test_accg_immed 0,accg1 384 test_acc_limmed 0x3fff,0xffff,acc1 385 386 set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result 387 set_fr_iimmed 0xfffe,0x2001,fr8 388 cmmachs fr7,fr8,acc0,cc1,0 389 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 390 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 391 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 392 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 393 test_accg_immed 0,accg0 394 test_acc_limmed 0x3fff,0xbffd,acc0 395 test_accg_immed 0,accg1 396 test_acc_limmed 0x3fff,0xbffd,acc1 397 398 set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result 399 set_fr_iimmed 0xfffe,0x4000,fr8 400 cmmachs fr7,fr8,acc0,cc5,0 401 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 402 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 403 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 404 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 405 test_accg_immed 0,accg0 406 test_acc_limmed 0x3fff,0x3ffd,acc0 407 test_accg_immed 0,accg1 408 test_acc_limmed 0x3fff,0x3ffd,acc1 409 410 set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result 411 set_fr_iimmed 0x8000,0x7fff,fr8 412 cmmachs fr7,fr8,acc0,cc5,0 413 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 414 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 415 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 416 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 417 test_accg_immed 0xff,accg0 418 test_acc_limmed 0xffff,0xbffd,acc0 419 test_accg_immed 0xff,accg1 420 test_acc_limmed 0xffff,0xbffd,acc1 421 422 ; Negative operands 423 set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers 424 set_fr_iimmed 0xfffd,0xfffe,fr8 425 cmmachs fr7,fr8,acc0,cc5,0 426 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 427 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 428 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 429 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 430 test_accg_immed 0xff,accg0 431 test_acc_limmed 0xffff,0xc003,acc0 432 test_accg_immed 0xff,accg1 433 test_acc_limmed 0xffff,0xc003,acc1 434 435 set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 436 set_fr_iimmed 0xfffe,0xffff,fr8 437 cmmachs fr7,fr8,acc0,cc5,0 438 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 439 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 440 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 441 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 442 test_accg_immed 0xff,accg0 443 test_acc_limmed 0xffff,0xc005,acc0 444 test_accg_immed 0xff,accg1 445 test_acc_limmed 0xffff,0xc005,acc1 446 447 set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result 448 set_fr_iimmed 0x8001,0x8001,fr8 449 cmmachs fr7,fr8,acc0,cc5,0 450 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 451 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 452 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 453 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 454 test_accg_immed 0,accg0 455 test_acc_immed 0x3ffec006,acc0 456 test_accg_immed 0,accg1 457 test_acc_immed 0x3ffec006,acc1 458 459 set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result 460 set_fr_iimmed 0x8000,0x8000,fr8 461 cmmachs fr7,fr8,acc0,cc5,0 462 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 463 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 464 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 465 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 466 test_accg_immed 0,accg0 467 test_acc_immed 0x7ffec006,acc0 468 test_accg_immed 0,accg1 469 test_acc_immed 0x7ffec006,acc1 470 471 set_accg_immed 0x7f,accg0 ; saturation 472 set_acc_immed 0xffffffff,acc0 473 set_accg_immed 0x7f,accg1 474 set_acc_immed 0xffffffff,acc1 475 set_fr_iimmed 1,1,fr7 476 set_fr_iimmed 1,1,fr8 477 cmmachs fr7,fr8,acc0,cc5,0 478 test_accg_immed 0x7f,accg0 479 test_acc_limmed 0xffff,0xffff,acc0 480 test_accg_immed 0x7f,accg1 481 test_acc_limmed 0xffff,0xffff,acc1 482 483 set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation 484 set_fr_iimmed 0x7fff,0x7fff,fr8 485 cmmachs fr7,fr8,acc0,cc5,0 486 test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set 487 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set 488 test_spr_bits 1,0,1,msr0 ; msr0.aovf is set 489 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set 490 test_accg_immed 0x7f,accg0 491 test_acc_limmed 0xffff,0xffff,acc0 492 test_accg_immed 0x7f,accg1 493 test_acc_limmed 0xffff,0xffff,acc1 494 495 set_accg_immed 0x80,accg0 ; saturation 496 set_acc_immed 0,acc0 497 set_accg_immed 0x80,accg1 498 set_acc_immed 0,acc1 499 set_fr_iimmed 0xffff,0,fr7 500 set_fr_iimmed 1,0xffff,fr8 501 cmmachs fr7,fr8,acc0,cc5,0 502 test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set 503 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set 504 test_spr_bits 1,0,1,msr0 ; msr0.aovf is set 505 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set 506 test_accg_immed 0x80,accg0 507 test_acc_immed 0,acc0 508 test_accg_immed 0x80,accg1 509 test_acc_immed 0,acc1 510 511 set_fr_iimmed 0x0000,0x8000,fr7 ; saturation 512 set_fr_iimmed 0x7fff,0x7fff,fr8 513 cmmachs fr7,fr8,acc0,cc5,0 514 test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set 515 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set 516 test_spr_bits 1,0,1,msr0 ; msr0.aovf is set 517 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set 518 test_accg_immed 0x80,accg0 519 test_acc_immed 0,acc0 520 test_accg_immed 0x80,accg1 521 test_acc_immed 0,acc1 522 523 ; Positive operands 524 set_spr_immed 0x0,msr0 525 set_spr_immed 0x0,msr1 526 set_accg_immed 0x0,accg0 527 set_acc_immed 0x0,acc0 528 set_accg_immed 0x0,accg1 529 set_acc_immed 0x0,acc1 530 set_fr_iimmed 2,3,fr7 ; multiply small numbers 531 set_fr_iimmed 3,2,fr8 532 cmmachs fr7,fr8,acc0,cc0,0 533 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 534 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 535 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 536 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 537 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 538 test_accg_immed 0,accg0 539 test_acc_immed 0,acc0 540 test_accg_immed 0,accg1 541 test_acc_immed 0,acc1 542 543 set_fr_iimmed 0,1,fr7 ; multiply by 0 544 set_fr_iimmed 2,0,fr8 545 cmmachs fr7,fr8,acc0,cc0,0 546 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 547 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 548 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 549 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 550 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 551 test_accg_immed 0,accg0 552 test_acc_immed 0,acc0 553 test_accg_immed 0,accg1 554 test_acc_immed 0,acc1 555 556 set_fr_iimmed 2,1,fr7 ; multiply by 1 557 set_fr_iimmed 1,2,fr8 558 cmmachs fr7,fr8,acc0,cc0,0 559 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 560 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 561 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 562 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 563 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 564 test_accg_immed 0,accg0 565 test_acc_immed 0,acc0 566 test_accg_immed 0,accg1 567 test_acc_immed 0,acc1 568 569 set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result 570 set_fr_iimmed 2,0x3fff,fr8 571 cmmachs fr7,fr8,acc0,cc0,0 572 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 573 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 574 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 575 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 576 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 577 test_accg_immed 0,accg0 578 test_acc_immed 0,acc0 579 test_accg_immed 0,accg1 580 test_acc_immed 0,acc1 581 582 set_fr_iimmed 0x4000,2,fr7 ; 16 bit result 583 set_fr_iimmed 2,0x4000,fr8 584 cmmachs fr7,fr8,acc0,cc0,0 585 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 586 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 587 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 588 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 589 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 590 test_accg_immed 0,accg0 591 test_acc_immed 0,acc0 592 test_accg_immed 0,accg1 593 test_acc_immed 0,acc1 594 595 set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result 596 set_fr_iimmed 0x7fff,0x7fff,fr8 597 cmmachs fr7,fr8,acc0,cc0,0 598 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 599 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 600 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 601 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 602 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 603 test_accg_immed 0,accg0 604 test_acc_immed 0,acc0 605 test_accg_immed 0,accg1 606 test_acc_immed 0,acc1 607 608 ; Mixed operands 609 set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers 610 set_fr_iimmed 0xfffd,2,fr8 611 cmmachs fr7,fr8,acc0,cc0,0 612 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 613 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 614 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 615 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 616 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 617 test_accg_immed 0,accg0 618 test_acc_immed 0,acc0 619 test_accg_immed 0,accg1 620 test_acc_immed 0,acc1 621 622 set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 623 set_fr_iimmed 1,0xfffe,fr8 624 cmmachs fr7,fr8,acc0,cc0,0 625 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 626 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 627 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 628 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 629 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 630 test_accg_immed 0,accg0 631 test_acc_immed 0,acc0 632 test_accg_immed 0,accg1 633 test_acc_immed 0,acc1 634 635 set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 636 set_fr_iimmed 0,0xfffe,fr8 637 cmmachs fr7,fr8,acc0,cc0,0 638 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 639 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 640 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 641 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 642 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 643 test_accg_immed 0,accg0 644 test_acc_immed 0,acc0 645 test_accg_immed 0,accg1 646 test_acc_immed 0,acc1 647 648 set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result 649 set_fr_iimmed 0xfffe,0x2001,fr8 650 cmmachs fr7,fr8,acc0,cc0,0 651 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 652 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 653 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 654 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 655 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 656 test_accg_immed 0,accg0 657 test_acc_immed 0,acc0 658 test_accg_immed 0,accg1 659 test_acc_immed 0,acc1 660 661 set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result 662 set_fr_iimmed 0xfffe,0x4000,fr8 663 cmmachs fr7,fr8,acc0,cc4,0 664 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 665 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 666 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 667 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 668 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 669 test_accg_immed 0,accg0 670 test_acc_immed 0,acc0 671 test_accg_immed 0,accg1 672 test_acc_immed 0,acc1 673 674 set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result 675 set_fr_iimmed 0x8000,0x7fff,fr8 676 cmmachs fr7,fr8,acc0,cc4,0 677 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 678 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 679 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 680 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 681 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 682 test_accg_immed 0,accg0 683 test_acc_immed 0,acc0 684 test_accg_immed 0,accg1 685 test_acc_immed 0,acc1 686 687 ; Negative operands 688 set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers 689 set_fr_iimmed 0xfffd,0xfffe,fr8 690 cmmachs fr7,fr8,acc0,cc4,0 691 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 692 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 693 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 694 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 695 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 696 test_accg_immed 0,accg0 697 test_acc_immed 0,acc0 698 test_accg_immed 0,accg1 699 test_acc_immed 0,acc1 700 701 set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 702 set_fr_iimmed 0xfffe,0xffff,fr8 703 cmmachs fr7,fr8,acc0,cc4,0 704 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 705 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 706 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 707 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 708 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 709 test_accg_immed 0,accg0 710 test_acc_immed 0,acc0 711 test_accg_immed 0,accg1 712 test_acc_immed 0,acc1 713 714 set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result 715 set_fr_iimmed 0x8001,0x8001,fr8 716 cmmachs fr7,fr8,acc0,cc4,0 717 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 718 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 719 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 720 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 721 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 722 test_accg_immed 0,accg0 723 test_acc_immed 0,acc0 724 test_accg_immed 0,accg1 725 test_acc_immed 0,acc1 726 727 set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result 728 set_fr_iimmed 0x8000,0x8000,fr8 729 cmmachs fr7,fr8,acc0,cc4,0 730 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 731 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 732 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 733 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 734 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 735 test_accg_immed 0,accg0 736 test_acc_immed 0,acc0 737 test_accg_immed 0,accg1 738 test_acc_immed 0,acc1 739 740 set_accg_immed 0x7f,accg0 ; saturation 741 set_acc_immed 0xffffffff,acc0 742 set_accg_immed 0x7f,accg1 743 set_acc_immed 0xffffffff,acc1 744 set_fr_iimmed 1,1,fr7 745 set_fr_iimmed 1,1,fr8 746 cmmachs fr7,fr8,acc0,cc4,0 747 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 748 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 749 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 750 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 751 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 752 test_accg_immed 0x7f,accg0 ; saturation 753 test_acc_immed 0xffffffff,acc0 754 test_accg_immed 0x7f,accg1 755 test_acc_immed 0xffffffff,acc1 756 757 set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation 758 set_fr_iimmed 0x7fff,0x7fff,fr8 759 cmmachs fr7,fr8,acc0,cc4,0 760 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 761 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 762 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 763 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 764 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 765 test_accg_immed 0x7f,accg0 ; saturation 766 test_acc_immed 0xffffffff,acc0 767 test_accg_immed 0x7f,accg1 768 test_acc_immed 0xffffffff,acc1 769 770 set_accg_immed 0x80,accg0 ; saturation 771 set_acc_immed 0,acc0 772 set_accg_immed 0x80,accg1 773 set_acc_immed 0,acc1 774 set_fr_iimmed 0xffff,0,fr7 775 set_fr_iimmed 1,0xffff,fr8 776 cmmachs fr7,fr8,acc0,cc4,0 777 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 778 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 779 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 780 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 781 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 782 test_accg_immed 0x80,accg0 ; saturation 783 test_acc_immed 0,acc0 784 test_accg_immed 0x80,accg1 785 test_acc_immed 0,acc1 786 787 set_fr_iimmed 0x0000,0x8000,fr7 ; saturation 788 set_fr_iimmed 0x7fff,0x7fff,fr8 789 cmmachs fr7,fr8,acc0,cc4,0 790 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 791 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 792 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 793 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 794 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 795 test_accg_immed 0x80,accg0 ; saturation 796 test_acc_immed 0,acc0 797 test_accg_immed 0x80,accg1 798 test_acc_immed 0,acc1 799 800 ; Positive operands 801 set_spr_immed 0x0,msr0 802 set_spr_immed 0x0,msr1 803 set_accg_immed 0x0,accg0 804 set_acc_immed 0x0,acc0 805 set_accg_immed 0x0,accg1 806 set_acc_immed 0x0,acc1 807 set_fr_iimmed 2,3,fr7 ; multiply small numbers 808 set_fr_iimmed 3,2,fr8 809 cmmachs fr7,fr8,acc0,cc1,1 810 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 811 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 812 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 813 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 814 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 815 test_accg_immed 0,accg0 816 test_acc_immed 0,acc0 817 test_accg_immed 0,accg1 818 test_acc_immed 0,acc1 819 820 set_fr_iimmed 0,1,fr7 ; multiply by 0 821 set_fr_iimmed 2,0,fr8 822 cmmachs fr7,fr8,acc0,cc1,1 823 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 824 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 825 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 826 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 827 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 828 test_accg_immed 0,accg0 829 test_acc_immed 0,acc0 830 test_accg_immed 0,accg1 831 test_acc_immed 0,acc1 832 833 set_fr_iimmed 2,1,fr7 ; multiply by 1 834 set_fr_iimmed 1,2,fr8 835 cmmachs fr7,fr8,acc0,cc1,1 836 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 837 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 838 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 839 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 840 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 841 test_accg_immed 0,accg0 842 test_acc_immed 0,acc0 843 test_accg_immed 0,accg1 844 test_acc_immed 0,acc1 845 846 set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result 847 set_fr_iimmed 2,0x3fff,fr8 848 cmmachs fr7,fr8,acc0,cc1,1 849 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 850 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 851 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 852 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 853 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 854 test_accg_immed 0,accg0 855 test_acc_immed 0,acc0 856 test_accg_immed 0,accg1 857 test_acc_immed 0,acc1 858 859 set_fr_iimmed 0x4000,2,fr7 ; 16 bit result 860 set_fr_iimmed 2,0x4000,fr8 861 cmmachs fr7,fr8,acc0,cc1,1 862 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 863 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 864 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 865 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 866 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 867 test_accg_immed 0,accg0 868 test_acc_immed 0,acc0 869 test_accg_immed 0,accg1 870 test_acc_immed 0,acc1 871 872 set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result 873 set_fr_iimmed 0x7fff,0x7fff,fr8 874 cmmachs fr7,fr8,acc0,cc1,1 875 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 876 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 877 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 878 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 879 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 880 test_accg_immed 0,accg0 881 test_acc_immed 0,acc0 882 test_accg_immed 0,accg1 883 test_acc_immed 0,acc1 884 885 ; Mixed operands 886 set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers 887 set_fr_iimmed 0xfffd,2,fr8 888 cmmachs fr7,fr8,acc0,cc1,1 889 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 890 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 891 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 892 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 893 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 894 test_accg_immed 0,accg0 895 test_acc_immed 0,acc0 896 test_accg_immed 0,accg1 897 test_acc_immed 0,acc1 898 899 set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 900 set_fr_iimmed 1,0xfffe,fr8 901 cmmachs fr7,fr8,acc0,cc1,1 902 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 903 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 904 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 905 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 906 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 907 test_accg_immed 0,accg0 908 test_acc_immed 0,acc0 909 test_accg_immed 0,accg1 910 test_acc_immed 0,acc1 911 912 set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 913 set_fr_iimmed 0,0xfffe,fr8 914 cmmachs fr7,fr8,acc0,cc1,1 915 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 916 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 917 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 918 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 919 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 920 test_accg_immed 0,accg0 921 test_acc_immed 0,acc0 922 test_accg_immed 0,accg1 923 test_acc_immed 0,acc1 924 925 set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result 926 set_fr_iimmed 0xfffe,0x2001,fr8 927 cmmachs fr7,fr8,acc0,cc1,1 928 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 929 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 930 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 931 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 932 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 933 test_accg_immed 0,accg0 934 test_acc_immed 0,acc0 935 test_accg_immed 0,accg1 936 test_acc_immed 0,acc1 937 938 set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result 939 set_fr_iimmed 0xfffe,0x4000,fr8 940 cmmachs fr7,fr8,acc0,cc5,1 941 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 942 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 943 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 944 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 945 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 946 test_accg_immed 0,accg0 947 test_acc_immed 0,acc0 948 test_accg_immed 0,accg1 949 test_acc_immed 0,acc1 950 951 set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result 952 set_fr_iimmed 0x8000,0x7fff,fr8 953 cmmachs fr7,fr8,acc0,cc5,1 954 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 955 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 956 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 957 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 958 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 959 test_accg_immed 0,accg0 960 test_acc_immed 0,acc0 961 test_accg_immed 0,accg1 962 test_acc_immed 0,acc1 963 964 ; Negative operands 965 set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers 966 set_fr_iimmed 0xfffd,0xfffe,fr8 967 cmmachs fr7,fr8,acc0,cc5,1 968 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 969 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 970 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 971 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 972 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 973 test_accg_immed 0,accg0 974 test_acc_immed 0,acc0 975 test_accg_immed 0,accg1 976 test_acc_immed 0,acc1 977 978 set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 979 set_fr_iimmed 0xfffe,0xffff,fr8 980 cmmachs fr7,fr8,acc0,cc5,1 981 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 982 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 983 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 984 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 985 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 986 test_accg_immed 0,accg0 987 test_acc_immed 0,acc0 988 test_accg_immed 0,accg1 989 test_acc_immed 0,acc1 990 991 set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result 992 set_fr_iimmed 0x8001,0x8001,fr8 993 cmmachs fr7,fr8,acc0,cc5,1 994 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 995 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 996 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 997 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 998 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 999 test_accg_immed 0,accg0 1000 test_acc_immed 0,acc0 1001 test_accg_immed 0,accg1 1002 test_acc_immed 0,acc1 1003 1004 set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result 1005 set_fr_iimmed 0x8000,0x8000,fr8 1006 cmmachs fr7,fr8,acc0,cc5,1 1007 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1008 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1009 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1010 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1011 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1012 test_accg_immed 0,accg0 1013 test_acc_immed 0,acc0 1014 test_accg_immed 0,accg1 1015 test_acc_immed 0,acc1 1016 1017 set_accg_immed 0x7f,accg0 ; saturation 1018 set_acc_immed 0xffffffff,acc0 1019 set_accg_immed 0x7f,accg1 1020 set_acc_immed 0xffffffff,acc1 1021 set_fr_iimmed 1,1,fr7 1022 set_fr_iimmed 1,1,fr8 1023 cmmachs fr7,fr8,acc0,cc5,1 1024 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1025 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1026 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1027 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1028 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1029 test_accg_immed 0x7f,accg0 ; saturation 1030 test_acc_immed 0xffffffff,acc0 1031 test_accg_immed 0x7f,accg1 1032 test_acc_immed 0xffffffff,acc1 1033 1034 set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation 1035 set_fr_iimmed 0x7fff,0x7fff,fr8 1036 cmmachs fr7,fr8,acc0,cc5,1 1037 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1038 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1039 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1040 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1041 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1042 test_accg_immed 0x7f,accg0 ; saturation 1043 test_acc_immed 0xffffffff,acc0 1044 test_accg_immed 0x7f,accg1 1045 test_acc_immed 0xffffffff,acc1 1046 1047 set_accg_immed 0x80,accg0 ; saturation 1048 set_acc_immed 0,acc0 1049 set_accg_immed 0x80,accg1 1050 set_acc_immed 0,acc1 1051 set_fr_iimmed 0xffff,0,fr7 1052 set_fr_iimmed 1,0xffff,fr8 1053 cmmachs fr7,fr8,acc0,cc5,1 1054 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1055 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1056 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1057 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1058 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1059 test_accg_immed 0x80,accg0 ; saturation 1060 test_acc_immed 0,acc0 1061 test_accg_immed 0x80,accg1 1062 test_acc_immed 0,acc1 1063 1064 set_fr_iimmed 0x0000,0x8000,fr7 ; saturation 1065 set_fr_iimmed 0x7fff,0x7fff,fr8 1066 cmmachs fr7,fr8,acc0,cc5,1 1067 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1068 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1069 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1070 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1071 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1072 test_accg_immed 0x80,accg0 ; saturation 1073 test_acc_immed 0,acc0 1074 test_accg_immed 0x80,accg1 1075 test_acc_immed 0,acc1 1076 1077 ; Positive operands 1078 set_spr_immed 0x0,msr0 1079 set_spr_immed 0x0,msr1 1080 set_accg_immed 0x0,accg0 1081 set_acc_immed 0x0,acc0 1082 set_accg_immed 0x0,accg1 1083 set_acc_immed 0x0,acc1 1084 set_fr_iimmed 2,3,fr7 ; multiply small numbers 1085 set_fr_iimmed 3,2,fr8 1086 cmmachs fr7,fr8,acc0,cc2,1 1087 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1088 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1089 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1090 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1091 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1092 test_accg_immed 0,accg0 1093 test_acc_immed 0,acc0 1094 test_accg_immed 0,accg1 1095 test_acc_immed 0,acc1 1096 1097 set_fr_iimmed 0,1,fr7 ; multiply by 0 1098 set_fr_iimmed 2,0,fr8 1099 cmmachs fr7,fr8,acc0,cc2,0 1100 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1101 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1102 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1103 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1104 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1105 test_accg_immed 0,accg0 1106 test_acc_immed 0,acc0 1107 test_accg_immed 0,accg1 1108 test_acc_immed 0,acc1 1109 1110 set_fr_iimmed 2,1,fr7 ; multiply by 1 1111 set_fr_iimmed 1,2,fr8 1112 cmmachs fr7,fr8,acc0,cc2,1 1113 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1114 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1115 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1116 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1117 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1118 test_accg_immed 0,accg0 1119 test_acc_immed 0,acc0 1120 test_accg_immed 0,accg1 1121 test_acc_immed 0,acc1 1122 1123 set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result 1124 set_fr_iimmed 2,0x3fff,fr8 1125 cmmachs fr7,fr8,acc0,cc2,0 1126 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1127 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1128 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1129 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1130 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1131 test_accg_immed 0,accg0 1132 test_acc_immed 0,acc0 1133 test_accg_immed 0,accg1 1134 test_acc_immed 0,acc1 1135 1136 set_fr_iimmed 0x4000,2,fr7 ; 16 bit result 1137 set_fr_iimmed 2,0x4000,fr8 1138 cmmachs fr7,fr8,acc0,cc2,1 1139 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1140 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1141 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1142 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1143 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1144 test_accg_immed 0,accg0 1145 test_acc_immed 0,acc0 1146 test_accg_immed 0,accg1 1147 test_acc_immed 0,acc1 1148 1149 set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result 1150 set_fr_iimmed 0x7fff,0x7fff,fr8 1151 cmmachs fr7,fr8,acc0,cc2,0 1152 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1153 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1154 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1155 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1156 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1157 test_accg_immed 0,accg0 1158 test_acc_immed 0,acc0 1159 test_accg_immed 0,accg1 1160 test_acc_immed 0,acc1 1161 1162 ; Mixed operands 1163 set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers 1164 set_fr_iimmed 0xfffd,2,fr8 1165 cmmachs fr7,fr8,acc0,cc2,1 1166 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1167 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1168 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1169 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1170 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1171 test_accg_immed 0,accg0 1172 test_acc_immed 0,acc0 1173 test_accg_immed 0,accg1 1174 test_acc_immed 0,acc1 1175 1176 set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 1177 set_fr_iimmed 1,0xfffe,fr8 1178 cmmachs fr7,fr8,acc0,cc2,0 1179 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1180 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1181 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1182 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1183 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1184 test_accg_immed 0,accg0 1185 test_acc_immed 0,acc0 1186 test_accg_immed 0,accg1 1187 test_acc_immed 0,acc1 1188 1189 set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 1190 set_fr_iimmed 0,0xfffe,fr8 1191 cmmachs fr7,fr8,acc0,cc2,1 1192 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1193 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1194 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1195 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1196 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1197 test_accg_immed 0,accg0 1198 test_acc_immed 0,acc0 1199 test_accg_immed 0,accg1 1200 test_acc_immed 0,acc1 1201 1202 set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result 1203 set_fr_iimmed 0xfffe,0x2001,fr8 1204 cmmachs fr7,fr8,acc0,cc2,0 1205 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1206 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1207 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1208 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1209 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1210 test_accg_immed 0,accg0 1211 test_acc_immed 0,acc0 1212 test_accg_immed 0,accg1 1213 test_acc_immed 0,acc1 1214 1215 set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result 1216 set_fr_iimmed 0xfffe,0x4000,fr8 1217 cmmachs fr7,fr8,acc0,cc6,1 1218 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1219 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1220 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1221 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1222 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1223 test_accg_immed 0,accg0 1224 test_acc_immed 0,acc0 1225 test_accg_immed 0,accg1 1226 test_acc_immed 0,acc1 1227 1228 set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result 1229 set_fr_iimmed 0x8000,0x7fff,fr8 1230 cmmachs fr7,fr8,acc0,cc6,0 1231 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1232 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1233 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1234 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1235 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1236 test_accg_immed 0,accg0 1237 test_acc_immed 0,acc0 1238 test_accg_immed 0,accg1 1239 test_acc_immed 0,acc1 1240 1241 ; Negative operands 1242 set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers 1243 set_fr_iimmed 0xfffd,0xfffe,fr8 1244 cmmachs fr7,fr8,acc0,cc6,1 1245 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1246 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1247 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1248 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1249 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1250 test_accg_immed 0,accg0 1251 test_acc_immed 0,acc0 1252 test_accg_immed 0,accg1 1253 test_acc_immed 0,acc1 1254 1255 set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 1256 set_fr_iimmed 0xfffe,0xffff,fr8 1257 cmmachs fr7,fr8,acc0,cc6,0 1258 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1259 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1260 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1261 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1262 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1263 test_accg_immed 0,accg0 1264 test_acc_immed 0,acc0 1265 test_accg_immed 0,accg1 1266 test_acc_immed 0,acc1 1267 1268 set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result 1269 set_fr_iimmed 0x8001,0x8001,fr8 1270 cmmachs fr7,fr8,acc0,cc6,1 1271 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1272 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1273 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1274 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1275 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1276 test_accg_immed 0,accg0 1277 test_acc_immed 0,acc0 1278 test_accg_immed 0,accg1 1279 test_acc_immed 0,acc1 1280 1281 set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result 1282 set_fr_iimmed 0x8000,0x8000,fr8 1283 cmmachs fr7,fr8,acc0,cc6,0 1284 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1285 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1286 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1287 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1288 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1289 test_accg_immed 0,accg0 1290 test_acc_immed 0,acc0 1291 test_accg_immed 0,accg1 1292 test_acc_immed 0,acc1 1293 1294 set_accg_immed 0x7f,accg0 ; saturation 1295 set_acc_immed 0xffffffff,acc0 1296 set_accg_immed 0x7f,accg1 1297 set_acc_immed 0xffffffff,acc1 1298 set_fr_iimmed 1,1,fr7 1299 set_fr_iimmed 1,1,fr8 1300 cmmachs fr7,fr8,acc0,cc6,1 1301 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1302 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1303 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1304 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1305 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1306 test_accg_immed 0x7f,accg0 ; saturation 1307 test_acc_immed 0xffffffff,acc0 1308 test_accg_immed 0x7f,accg1 1309 test_acc_immed 0xffffffff,acc1 1310 1311 set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation 1312 set_fr_iimmed 0x7fff,0x7fff,fr8 1313 cmmachs fr7,fr8,acc0,cc6,0 1314 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1315 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1316 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1317 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1318 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1319 test_accg_immed 0x7f,accg0 ; saturation 1320 test_acc_immed 0xffffffff,acc0 1321 test_accg_immed 0x7f,accg1 1322 test_acc_immed 0xffffffff,acc1 1323 1324 set_accg_immed 0x80,accg0 ; saturation 1325 set_acc_immed 0,acc0 1326 set_accg_immed 0x80,accg1 1327 set_acc_immed 0,acc1 1328 set_fr_iimmed 0xffff,0,fr7 1329 set_fr_iimmed 1,0xffff,fr8 1330 cmmachs fr7,fr8,acc0,cc6,1 1331 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1332 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1333 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1334 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1335 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1336 test_accg_immed 0x80,accg0 ; saturation 1337 test_acc_immed 0,acc0 1338 test_accg_immed 0x80,accg1 1339 test_acc_immed 0,acc1 1340 1341 set_fr_iimmed 0x0000,0x8000,fr7 ; saturation 1342 set_fr_iimmed 0x7fff,0x7fff,fr8 1343 cmmachs fr7,fr8,acc0,cc6,0 1344 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1345 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1346 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1347 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1348 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1349 test_accg_immed 0x80,accg0 ; saturation 1350 test_acc_immed 0,acc0 1351 test_accg_immed 0x80,accg1 1352 test_acc_immed 0,acc1 1353; 1354 ; Positive operands 1355 set_spr_immed 0x0,msr0 1356 set_spr_immed 0x0,msr1 1357 set_accg_immed 0x0,accg0 1358 set_acc_immed 0x0,acc0 1359 set_accg_immed 0x0,accg1 1360 set_acc_immed 0x0,acc1 1361 set_fr_iimmed 2,3,fr7 ; multiply small numbers 1362 set_fr_iimmed 3,2,fr8 1363 cmmachs fr7,fr8,acc0,cc3,1 1364 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1365 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1366 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1367 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1368 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1369 test_accg_immed 0,accg0 1370 test_acc_immed 0,acc0 1371 test_accg_immed 0,accg1 1372 test_acc_immed 0,acc1 1373 1374 set_fr_iimmed 0,1,fr7 ; multiply by 0 1375 set_fr_iimmed 2,0,fr8 1376 cmmachs fr7,fr8,acc0,cc3,0 1377 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1378 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1379 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1380 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1381 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1382 test_accg_immed 0,accg0 1383 test_acc_immed 0,acc0 1384 test_accg_immed 0,accg1 1385 test_acc_immed 0,acc1 1386 1387 set_fr_iimmed 2,1,fr7 ; multiply by 1 1388 set_fr_iimmed 1,2,fr8 1389 cmmachs fr7,fr8,acc0,cc3,1 1390 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1391 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1392 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1393 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1394 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1395 test_accg_immed 0,accg0 1396 test_acc_immed 0,acc0 1397 test_accg_immed 0,accg1 1398 test_acc_immed 0,acc1 1399 1400 set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result 1401 set_fr_iimmed 2,0x3fff,fr8 1402 cmmachs fr7,fr8,acc0,cc3,0 1403 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1404 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1405 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1406 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1407 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1408 test_accg_immed 0,accg0 1409 test_acc_immed 0,acc0 1410 test_accg_immed 0,accg1 1411 test_acc_immed 0,acc1 1412 1413 set_fr_iimmed 0x4000,2,fr7 ; 16 bit result 1414 set_fr_iimmed 2,0x4000,fr8 1415 cmmachs fr7,fr8,acc0,cc3,1 1416 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1417 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1418 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1419 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1420 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1421 test_accg_immed 0,accg0 1422 test_acc_immed 0,acc0 1423 test_accg_immed 0,accg1 1424 test_acc_immed 0,acc1 1425 1426 set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result 1427 set_fr_iimmed 0x7fff,0x7fff,fr8 1428 cmmachs fr7,fr8,acc0,cc3,0 1429 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1430 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1431 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1432 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1433 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1434 test_accg_immed 0,accg0 1435 test_acc_immed 0,acc0 1436 test_accg_immed 0,accg1 1437 test_acc_immed 0,acc1 1438 1439 ; Mixed operands 1440 set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers 1441 set_fr_iimmed 0xfffd,2,fr8 1442 cmmachs fr7,fr8,acc0,cc3,1 1443 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1444 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1445 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1446 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1447 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1448 test_accg_immed 0,accg0 1449 test_acc_immed 0,acc0 1450 test_accg_immed 0,accg1 1451 test_acc_immed 0,acc1 1452 1453 set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 1454 set_fr_iimmed 1,0xfffe,fr8 1455 cmmachs fr7,fr8,acc0,cc3,0 1456 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1457 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1458 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1459 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1460 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1461 test_accg_immed 0,accg0 1462 test_acc_immed 0,acc0 1463 test_accg_immed 0,accg1 1464 test_acc_immed 0,acc1 1465 1466 set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 1467 set_fr_iimmed 0,0xfffe,fr8 1468 cmmachs fr7,fr8,acc0,cc3,1 1469 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1470 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1471 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1472 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1473 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1474 test_accg_immed 0,accg0 1475 test_acc_immed 0,acc0 1476 test_accg_immed 0,accg1 1477 test_acc_immed 0,acc1 1478 1479 set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result 1480 set_fr_iimmed 0xfffe,0x2001,fr8 1481 cmmachs fr7,fr8,acc0,cc3,0 1482 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1483 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1484 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1485 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1486 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1487 test_accg_immed 0,accg0 1488 test_acc_immed 0,acc0 1489 test_accg_immed 0,accg1 1490 test_acc_immed 0,acc1 1491 1492 set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result 1493 set_fr_iimmed 0xfffe,0x4000,fr8 1494 cmmachs fr7,fr8,acc0,cc7,1 1495 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1496 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1497 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1498 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1499 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1500 test_accg_immed 0,accg0 1501 test_acc_immed 0,acc0 1502 test_accg_immed 0,accg1 1503 test_acc_immed 0,acc1 1504 1505 set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result 1506 set_fr_iimmed 0x8000,0x7fff,fr8 1507 cmmachs fr7,fr8,acc0,cc7,0 1508 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1509 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1510 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1511 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1512 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1513 test_accg_immed 0,accg0 1514 test_acc_immed 0,acc0 1515 test_accg_immed 0,accg1 1516 test_acc_immed 0,acc1 1517 1518 ; Negative operands 1519 set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers 1520 set_fr_iimmed 0xfffd,0xfffe,fr8 1521 cmmachs fr7,fr8,acc0,cc7,1 1522 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1523 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1524 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1525 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1526 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1527 test_accg_immed 0,accg0 1528 test_acc_immed 0,acc0 1529 test_accg_immed 0,accg1 1530 test_acc_immed 0,acc1 1531 1532 set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 1533 set_fr_iimmed 0xfffe,0xffff,fr8 1534 cmmachs fr7,fr8,acc0,cc7,0 1535 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1536 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1537 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1538 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1539 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1540 test_accg_immed 0,accg0 1541 test_acc_immed 0,acc0 1542 test_accg_immed 0,accg1 1543 test_acc_immed 0,acc1 1544 1545 set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result 1546 set_fr_iimmed 0x8001,0x8001,fr8 1547 cmmachs fr7,fr8,acc0,cc7,1 1548 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1549 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1550 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1551 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1552 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1553 test_accg_immed 0,accg0 1554 test_acc_immed 0,acc0 1555 test_accg_immed 0,accg1 1556 test_acc_immed 0,acc1 1557 1558 set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result 1559 set_fr_iimmed 0x8000,0x8000,fr8 1560 cmmachs fr7,fr8,acc0,cc7,0 1561 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1562 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1563 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1564 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1565 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1566 test_accg_immed 0,accg0 1567 test_acc_immed 0,acc0 1568 test_accg_immed 0,accg1 1569 test_acc_immed 0,acc1 1570 1571 set_accg_immed 0x7f,accg0 ; saturation 1572 set_acc_immed 0xffffffff,acc0 1573 set_accg_immed 0x7f,accg1 1574 set_acc_immed 0xffffffff,acc1 1575 set_fr_iimmed 1,1,fr7 1576 set_fr_iimmed 1,1,fr8 1577 cmmachs fr7,fr8,acc0,cc7,1 1578 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1579 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1580 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1581 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1582 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1583 test_accg_immed 0x7f,accg0 ; saturation 1584 test_acc_immed 0xffffffff,acc0 1585 test_accg_immed 0x7f,accg1 1586 test_acc_immed 0xffffffff,acc1 1587 1588 set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation 1589 set_fr_iimmed 0x7fff,0x7fff,fr8 1590 cmmachs fr7,fr8,acc0,cc7,0 1591 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1592 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1593 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1594 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1595 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1596 test_accg_immed 0x7f,accg0 ; saturation 1597 test_acc_immed 0xffffffff,acc0 1598 test_accg_immed 0x7f,accg1 1599 test_acc_immed 0xffffffff,acc1 1600 1601 set_accg_immed 0x80,accg0 ; saturation 1602 set_acc_immed 0,acc0 1603 set_accg_immed 0x80,accg1 1604 set_acc_immed 0,acc1 1605 set_fr_iimmed 0xffff,0,fr7 1606 set_fr_iimmed 1,0xffff,fr8 1607 cmmachs fr7,fr8,acc0,cc7,1 1608 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1609 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1610 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1611 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1612 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1613 test_accg_immed 0x80,accg0 ; saturation 1614 test_acc_immed 0,acc0 1615 test_accg_immed 0x80,accg1 1616 test_acc_immed 0,acc1 1617 1618 set_fr_iimmed 0x0000,0x8000,fr7 ; saturation 1619 set_fr_iimmed 0x7fff,0x7fff,fr8 1620 cmmachs fr7,fr8,acc0,cc7,0 1621 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 1622 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 1623 test_spr_bits 2,1,0,msr1 ; msr1.ovf not set 1624 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 1625 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 1626 test_accg_immed 0x80,accg0 ; saturation 1627 test_acc_immed 0,acc0 1628 test_accg_immed 0x80,accg1 1629 test_acc_immed 0,acc1 1630 1631 pass 1632