1//Original:/testcases/core/c_ldimmhalf_drlo/c_ldimmhalf_drlo.dsp 2// Spec Reference: ldimmhalf dreg lo 3# mach: bfin 4 5.include "testutils.inc" 6 start 7 8 9 10INIT_R_REGS -1; 11 12// test Dreg 13R0.L = 0x0001; 14R1.L = 0x0003; 15R2.L = 0x0005; 16R3.L = 0x0007; 17R4.L = 0x0009; 18R5.L = 0x000b; 19R6.L = 0x000d; 20R7.L = 0x000f; 21CHECKREG r0, 0xFFFF0001; 22CHECKREG r1, 0xFFFF0003; 23CHECKREG r2, 0xFFFF0005; 24CHECKREG r3, 0xFFFF0007; 25CHECKREG r4, 0xFFFF0009; 26CHECKREG r5, 0xFFFF000b; 27CHECKREG r6, 0xFFFF000D; 28CHECKREG r7, 0xFFFF000F; 29 30R0.L = 0x0020; 31R1.L = 0x0040; 32R2.L = 0x0060; 33R3.L = 0x0080; 34R4.L = 0x00a0; 35R5.L = 0x00b0; 36R6.L = 0x00c0; 37R7.L = 0x00d0; 38CHECKREG r0, 0xFFFF0020; 39CHECKREG r1, 0xFFFF0040; 40CHECKREG r2, 0xFFFF0060; 41CHECKREG r3, 0xFFFF0080; 42CHECKREG r4, 0xFFFF00a0; 43CHECKREG r5, 0xFFFF00b0; 44CHECKREG r6, 0xFFFF00c0; 45CHECKREG r7, 0xFFFF00d0; 46 47R0.L = 0x0100; 48R1.L = 0x0200; 49R2.L = 0x0300; 50R3.L = 0x0400; 51R4.L = 0x0500; 52R5.L = 0x0600; 53R6.L = 0x0700; 54R7.L = 0x0800; 55CHECKREG r0, 0xFFFF0100; 56CHECKREG r1, 0xFFFF0200; 57CHECKREG r2, 0xFFFF0300; 58CHECKREG r3, 0xFFFF0400; 59CHECKREG r4, 0xFFFF0500; 60CHECKREG r5, 0xFFFF0600; 61CHECKREG r6, 0xFFFF0700; 62CHECKREG r7, 0xFFFF0800; 63 64R0 = 0; 65R1 = 0; 66R2 = 0; 67R3 = 0; 68R4 = 0; 69R5 = 0; 70R6 = 0; 71R7 = 0; 72R0.L = 0x7fff; 73R1.L = 0x7ffe; 74R2.L = -32768; 75R3.L = -32767; 76R4.L = 32767; 77R5.L = 32766; 78R6.L = 32765; 79R7.L = 32764; 80CHECKREG r0, 0x00007fff; 81CHECKREG r1, 0x00007ffe; 82CHECKREG r2, 0x00008000; 83CHECKREG r3, 0x00008001; 84CHECKREG r4, 0x00007FFF; 85CHECKREG r5, 0x00007FFE; 86CHECKREG r6, 0x00007FFD; 87CHECKREG r7, 0x00007FFC; 88 89pass 90