1 /* RISC-V simulator. 2 3 Copyright (C) 2005-2024 Free Software Foundation, Inc. 4 Contributed by Mike Frysinger. 5 6 This file is part of the GNU simulators. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21 #ifndef RISCV_MAIN_H 22 #define RISCV_MAIN_H 23 24 struct riscv_sim_cpu { 25 union { 26 unsigned_word regs[32]; 27 struct { 28 /* These are the ABI names. */ 29 unsigned_word zero, ra, sp, gp, tp; 30 unsigned_word t0, t1, t2; 31 unsigned_word s0, s1; 32 unsigned_word a0, a1, a2, a3, a4, a5, a6, a7; 33 unsigned_word s2, s3, s4, s5, s6, s7, s8, s9, s10, s11; 34 unsigned_word t3, t4, t5, t6; 35 }; 36 }; 37 union { 38 unsigned_word fpregs[32]; 39 struct { 40 /* These are the ABI names. */ 41 unsigned_word ft0, ft1, ft2, ft3, ft4, ft5, ft6, ft7; 42 unsigned_word fs0, fs1; 43 unsigned_word fa0, fa1, fa2, fa3, fa4, fa5, fa6, fa7; 44 unsigned_word fs2, fs3, fs4, fs5, fs6, fs7, fs8, fs9, fs10, fs11; 45 unsigned_word ft8, ft9, ft10, ft11; 46 }; 47 }; 48 sim_cia pc; 49 50 struct { 51 #define DECLARE_CSR(name, ...) unsigned_word name; 52 #include "opcode/riscv-opc.h" 53 #undef DECLARE_CSR 54 } csr; 55 }; 56 #define RISCV_SIM_CPU(cpu) ((struct riscv_sim_cpu *) CPU_ARCH_DATA (cpu)) 57 58 struct atomic_mem_reserved_list; 59 struct atomic_mem_reserved_list { 60 struct atomic_mem_reserved_list *next; 61 address_word addr; 62 }; 63 64 struct riscv_sim_state { 65 struct atomic_mem_reserved_list *amo_reserved_list; 66 }; 67 #define RISCV_SIM_STATE(sd) ((struct riscv_sim_state *) STATE_ARCH_DATA (sd)) 68 69 extern void step_once (SIM_CPU *); 70 extern void initialize_cpu (SIM_DESC, SIM_CPU *, int); 71 extern void initialize_env (SIM_DESC, const char * const *argv, 72 const char * const *env); 73 74 #define DEFAULT_MEM_SIZE (64 * 1024 * 1024) 75 76 #define RISCV_XLEN(cpu) MACH_WORD_BITSIZE (CPU_MACH (cpu)) 77 78 #endif 79