1// -*- C -*- 2 3// Simulator definition for the MIPS 32/64 revision 2 instructions. 4// Copyright (C) 2004-2014 Free Software Foundation, Inc. 5// Contributed by David Ung, of MIPS Technologies. 6// 7// This file is part of GDB, the GNU debugger. 8// 9// This program is free software; you can redistribute it and/or modify 10// it under the terms of the GNU General Public License as published by 11// the Free Software Foundation; either version 3 of the License, or 12// (at your option) any later version. 13// 14// This program is distributed in the hope that it will be useful, 15// but WITHOUT ANY WARRANTY; without even the implied warranty of 16// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17// GNU General Public License for more details. 18// 19// You should have received a copy of the GNU General Public License 20// along with this program. If not, see <http://www.gnu.org/licenses/>. 21 22 23011111,5.RS,5.RT,5.SIZE,5.LSB,000011::64::DEXT 24"dext r<RT>, r<RS>, <LSB>, <SIZE+1>" 25*mips64r2: 26{ 27 check_u64 (SD_, instruction_0); 28 TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE); 29 GPR[RT] = EXTRACTED64 (GPR[RS], LSB + SIZE, LSB); 30 TRACE_ALU_RESULT1 (GPR[RT]); 31} 32 33011111,5.RS,5.RT,5.SIZE,5.LSB,000001::64::DEXTM 34"dextm r<RT>, r<RS>, <LSB>, <SIZE+33>" 35*mips64r2: 36{ 37 check_u64 (SD_, instruction_0); 38 TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE); 39 GPR[RT] = EXTRACTED64 (GPR[RS], LSB + SIZE + 32, LSB); 40 TRACE_ALU_RESULT1 (GPR[RT]); 41} 42 43011111,5.RS,5.RT,5.SIZE,5.LSB,000010::64::DEXTU 44"dextu r<RT>, r<RS>, <LSB+32>, <SIZE+1>" 45*mips64r2: 46{ 47 check_u64 (SD_, instruction_0); 48 TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE); 49 GPR[RT] = EXTRACTED64 (GPR[RS], LSB + 32 + SIZE, LSB + 32); 50 TRACE_ALU_RESULT1 (GPR[RT]); 51} 52 53 54010000,01011,5.RT,01100,00000,0,00,000::32::DI 55"di":RT == 0 56"di r<RT>" 57*mips32r2: 58*mips64r2: 59{ 60 TRACE_ALU_INPUT0 (); 61 GPR[RT] = EXTEND32 (SR); 62 SR &= ~status_IE; 63 TRACE_ALU_RESULT1 (GPR[RT]); 64} 65 66 67011111,5.RS,5.RT,5.MSB,5.LSB,000111::64::DINS 68"dins r<RT>, r<RS>, <LSB>, <MSB-LSB+1>" 69*mips64r2: 70{ 71 check_u64 (SD_, instruction_0); 72 TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB); 73 if (LSB <= MSB) 74 GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << LSB)) & MASK64 (MSB, LSB); 75 TRACE_ALU_RESULT1 (GPR[RT]); 76} 77 78011111,5.RS,5.RT,5.MSB,5.LSB,000101::64::DINSM 79"dinsm r<RT>, r<RS>, <LSB>, <MSB+32-LSB+1>" 80*mips64r2: 81{ 82 check_u64 (SD_, instruction_0); 83 TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB); 84 if (LSB <= MSB + 32) 85 GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << LSB)) & MASK64 (MSB + 32, LSB); 86 TRACE_ALU_RESULT1 (GPR[RT]); 87} 88 89011111,5.RS,5.RT,5.MSB,5.LSB,000110::64::DINSU 90"dinsu r<RT>, r<RS>, <LSB+32>, <MSB-LSB+1>" 91*mips64r2: 92{ 93 check_u64 (SD_, instruction_0); 94 TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB); 95 if (LSB <= MSB) 96 GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << (LSB + 32))) 97 & MASK64 (MSB + 32, LSB + 32); 98 TRACE_ALU_RESULT1 (GPR[RT]); 99} 100 101 102011111,00000,5.RT,5.RD,00010,100100::64::DSBH 103"dsbh r<RD>, r<RT>" 104*mips64r2: 105{ 106 union { unsigned64 d; unsigned16 h[4]; } u; 107 check_u64 (SD_, instruction_0); 108 TRACE_ALU_INPUT1 (GPR[RT]); 109 u.d = GPR[RT]; 110 u.h[0] = SWAP_2 (u.h[0]); 111 u.h[1] = SWAP_2 (u.h[1]); 112 u.h[2] = SWAP_2 (u.h[2]); 113 u.h[3] = SWAP_2 (u.h[3]); 114 GPR[RD] = u.d; 115 TRACE_ALU_RESULT1 (GPR[RD]); 116} 117 118011111,00000,5.RT,5.RD,00101,100100::64::DSHD 119"dshd r<RD>, r<RT>" 120*mips64r2: 121{ 122 unsigned64 d; 123 check_u64 (SD_, instruction_0); 124 TRACE_ALU_INPUT1 (GPR[RT]); 125 d = GPR[RT]; 126 GPR[RD] = ((d >> 48) 127 | (d << 48) 128 | ((d & 0x0000ffff00000000ULL) >> 16) 129 | ((d & 0x00000000ffff0000ULL) << 16)); 130 TRACE_ALU_RESULT1 (GPR[RD]); 131} 132 133 134010000,01011,5.RT,01100,00000,1,00,000::32::EI 135"ei":RT == 0 136"ei r<RT>" 137*mips32r2: 138*mips64r2: 139{ 140 TRACE_ALU_INPUT0 (); 141 GPR[RT] = EXTEND32 (SR); 142 SR |= status_IE; 143 TRACE_ALU_RESULT1 (GPR[RT]); 144} 145 146 147011111,5.RS,5.RT,5.SIZE,5.LSB,000000::32::EXT 148"ext r<RT>, r<RS>, <LSB>, <SIZE+1>" 149*mips32r2: 150*mips64r2: 151{ 152 TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE); 153 GPR[RT] = EXTEND32 (EXTRACTED32 (GPR[RS], LSB + SIZE, LSB)); 154 TRACE_ALU_RESULT1 (GPR[RT]); 155} 156 157 158010001,00011,5.RT,5.FS,00000000000:COP1Sa:32,f::MFHC1 159"mfhc1 r<RT>, f<FS>" 160*mips32r2: 161*mips64r2: 162{ 163 check_fpu (SD_); 164 if (SizeFGR() == 64) 165 GPR[RT] = EXTEND32 (WORD64HI (FGR[FS])); 166 else if ((FS & 0x1) == 0) 167 GPR[RT] = EXTEND32 (FGR[FS + 1]); 168 else 169 { 170 if (STATE_VERBOSE_P(SD)) 171 sim_io_eprintf (SD, 172 "Warning: PC 0x%lx: MFHC1 32-bit use of odd FPR number\n", 173 (long) CIA); 174 GPR[RT] = EXTEND32 (0xBADF00D); 175 } 176 TRACE_ALU_RESULT (GPR[RT]); 177} 178 179010001,00111,5.RT,5.FS,00000000000:COP1Sa:32,f::MTHC1 180"mthc1 r<RT>, f<FS>" 181*mips32r2: 182*mips64r2: 183{ 184 check_fpu (SD_); 185 if (SizeFGR() == 64) 186 StoreFPR (FS, fmt_uninterpreted_64, SET64HI (GPR[RT]) | VL4_8 (FGR[FS])); 187 else if ((FS & 0x1) == 0) 188 StoreFPR (FS + 1, fmt_uninterpreted_32, VL4_8 (GPR[RT])); 189 else 190 { 191 if (STATE_VERBOSE_P(SD)) 192 sim_io_eprintf (SD, 193 "Warning: PC 0x%lx: MTHC1 32-bit use of odd FPR number\n", 194 (long) CIA); 195 StoreFPR (FS, fmt_uninterpreted_32, 0xDEADC0DE); 196 } 197 TRACE_FP_RESULT (GPR[RT]); 198} 199 200 201011111,5.RS,5.RT,5.MSB,5.LSB,000100::32::INS 202"ins r<RT>, r<RS>, <LSB>, <MSB-LSB+1>" 203*mips32r2: 204*mips64r2: 205{ 206 TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB); 207 if (LSB <= MSB) 208 GPR[RT] = EXTEND32 (GPR[RT] ^ 209 ((GPR[RT] ^ (GPR[RS] << LSB)) & MASK32 (MSB, LSB))); 210 TRACE_ALU_RESULT1 (GPR[RT]); 211} 212 213 214011111,00000,5.RT,5.RD,10000,100000::32::SEB 215"seb r<RD>, r<RT>" 216*mips32r2: 217*mips64r2: 218{ 219 TRACE_ALU_INPUT1 (GPR[RT]); 220 GPR[RD] = EXTEND8 (GPR[RT]); 221 TRACE_ALU_RESULT1 (GPR[RD]); 222} 223 224011111,00000,5.RT,5.RD,11000,100000::32::SEH 225"seh r<RD>, r<RT>" 226*mips32r2: 227*mips64r2: 228{ 229 TRACE_ALU_INPUT1 (GPR[RT]); 230 GPR[RD] = EXTEND16 (GPR[RT]); 231 TRACE_ALU_RESULT1 (GPR[RD]); 232} 233 234 235000001,5.BASE,11111,16.OFFSET::32::SYNCI 236"synci <OFFSET>(r<BASE>)" 237*mips32r2: 238*mips64r2: 239{ 240 // sync i-cache - nothing to do currently 241} 242 243 244011111,00000,5.RT,5.RD,00000,111011::32::RDHWR 245"rdhwr r<RT>, r<RD>" 246*mips32r2: 247*mips64r2: 248{ 249 // Return 0 for all hardware registers currently 250 GPR[RT] = EXTEND32 (0); 251 TRACE_ALU_RESULT1 (GPR[RT]); 252} 253 254 255011111,00000,5.RT,5.RD,00010,100000::32::WSBH 256"wsbh r<RD>, r<RT>" 257*mips32r2: 258*mips64r2: 259{ 260 union { unsigned32 w; unsigned16 h[2]; } u; 261 TRACE_ALU_INPUT1 (GPR[RT]); 262 u.w = GPR[RT]; 263 u.h[0] = SWAP_2 (u.h[0]); 264 u.h[1] = SWAP_2 (u.h[1]); 265 GPR[RD] = EXTEND32 (u.w); 266 TRACE_ALU_RESULT1 (GPR[RD]); 267} 268 269 270 271