1 /* Simulator for Motorola's MCore processor 2 Copyright (C) 2009-2017 Free Software Foundation, Inc. 3 4 This file is part of GDB, the GNU debugger. 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 18 19 #ifndef SIM_MAIN_H 20 #define SIM_MAIN_H 21 22 #include "sim-basics.h" 23 24 typedef long int word; 25 typedef unsigned long int uword; 26 27 #include "sim-base.h" 28 #include "bfd.h" 29 30 /* The machine state. 31 This state is maintained in host byte order. The 32 fetch/store register functions must translate between host 33 byte order and the target processor byte order. 34 Keeping this data in target byte order simplifies the register 35 read/write functions. Keeping this data in native order improves 36 the performance of the simulator. Simulation speed is deemed more 37 important. */ 38 39 /* The ordering of the mcore_regset structure is matched in the 40 gdb/config/mcore/tm-mcore.h file in the REGISTER_NAMES macro. */ 41 struct mcore_regset 42 { 43 word gregs[16]; /* primary registers */ 44 word alt_gregs[16]; /* alt register file */ 45 word cregs[32]; /* control registers */ 46 word pc; 47 }; 48 #define LAST_VALID_CREG 32 /* only 0..12 implemented */ 49 #define NUM_MCORE_REGS (16 + 16 + LAST_VALID_CREG + 1) 50 51 struct _sim_cpu { 52 53 union 54 { 55 struct mcore_regset regs; 56 /* Used by the fetch/store reg helpers to access registers linearly. */ 57 word asints[NUM_MCORE_REGS]; 58 }; 59 60 /* Used to switch between gregs/alt_gregs based on the control state. */ 61 word *active_gregs; 62 63 int ticks; 64 int stalls; 65 int cycles; 66 int insts; 67 68 sim_cpu_base base; 69 }; 70 71 struct sim_state { 72 73 sim_cpu *cpu[MAX_NR_PROCESSORS]; 74 75 sim_state_base base; 76 }; 77 78 #endif 79 80