1 /* Simulator for Motorola's MCore processor 2 Copyright (C) 1999-2017 Free Software Foundation, Inc. 3 Contributed by Cygnus Solutions. 4 5 This file is part of GDB, the GNU debugger. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #include "config.h" 21 #include <signal.h> 22 #include <stdlib.h> 23 #include <string.h> 24 #include <sys/times.h> 25 #include <sys/param.h> 26 #include <unistd.h> 27 #include "bfd.h" 28 #include "gdb/callback.h" 29 #include "libiberty.h" 30 #include "gdb/remote-sim.h" 31 32 #include "sim-main.h" 33 #include "sim-base.h" 34 #include "sim-syscall.h" 35 #include "sim-options.h" 36 37 #define target_big_endian (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) 38 39 40 static unsigned long 41 mcore_extract_unsigned_integer (unsigned char *addr, int len) 42 { 43 unsigned long retval; 44 unsigned char * p; 45 unsigned char * startaddr = (unsigned char *)addr; 46 unsigned char * endaddr = startaddr + len; 47 48 if (len > (int) sizeof (unsigned long)) 49 printf ("That operation is not available on integers of more than %zu bytes.", 50 sizeof (unsigned long)); 51 52 /* Start at the most significant end of the integer, and work towards 53 the least significant. */ 54 retval = 0; 55 56 if (! target_big_endian) 57 { 58 for (p = endaddr; p > startaddr;) 59 retval = (retval << 8) | * -- p; 60 } 61 else 62 { 63 for (p = startaddr; p < endaddr;) 64 retval = (retval << 8) | * p ++; 65 } 66 67 return retval; 68 } 69 70 static void 71 mcore_store_unsigned_integer (unsigned char *addr, int len, unsigned long val) 72 { 73 unsigned char * p; 74 unsigned char * startaddr = (unsigned char *)addr; 75 unsigned char * endaddr = startaddr + len; 76 77 if (! target_big_endian) 78 { 79 for (p = startaddr; p < endaddr;) 80 { 81 * p ++ = val & 0xff; 82 val >>= 8; 83 } 84 } 85 else 86 { 87 for (p = endaddr; p > startaddr;) 88 { 89 * -- p = val & 0xff; 90 val >>= 8; 91 } 92 } 93 } 94 95 static int memcycles = 1; 96 97 #define gr cpu->active_gregs 98 #define cr cpu->regs.cregs 99 #define sr cr[0] 100 #define vbr cr[1] 101 #define esr cr[2] 102 #define fsr cr[3] 103 #define epc cr[4] 104 #define fpc cr[5] 105 #define ss0 cr[6] 106 #define ss1 cr[7] 107 #define ss2 cr[8] 108 #define ss3 cr[9] 109 #define ss4 cr[10] 110 #define gcr cr[11] 111 #define gsr cr[12] 112 113 /* maniuplate the carry bit */ 114 #define C_ON() (sr & 1) 115 #define C_VALUE() (sr & 1) 116 #define C_OFF() ((sr & 1) == 0) 117 #define SET_C() {sr |= 1;} 118 #define CLR_C() {sr &= 0xfffffffe;} 119 #define NEW_C(v) {CLR_C(); sr |= ((v) & 1);} 120 121 #define SR_AF() ((sr >> 1) & 1) 122 static void set_active_regs (SIM_CPU *cpu) 123 { 124 if (SR_AF()) 125 cpu->active_gregs = cpu->regs.alt_gregs; 126 else 127 cpu->active_gregs = cpu->regs.gregs; 128 } 129 130 #define TRAPCODE 1 /* r1 holds which function we want */ 131 #define PARM1 2 /* first parameter */ 132 #define PARM2 3 133 #define PARM3 4 134 #define PARM4 5 135 #define RET1 2 /* register for return values. */ 136 137 /* Default to a 8 Mbyte (== 2^23) memory space. */ 138 #define DEFAULT_MEMORY_SIZE 0x800000 139 140 static void 141 set_initial_gprs (SIM_CPU *cpu) 142 { 143 /* Set up machine just out of reset. */ 144 CPU_PC_SET (cpu, 0); 145 sr = 0; 146 147 /* Clean out the GPRs and alternate GPRs. */ 148 memset (&cpu->regs.gregs, 0, sizeof(cpu->regs.gregs)); 149 memset (&cpu->regs.alt_gregs, 0, sizeof(cpu->regs.alt_gregs)); 150 151 /* Make our register set point to the right place. */ 152 set_active_regs (cpu); 153 154 /* ABI specifies initial values for these registers. */ 155 gr[0] = DEFAULT_MEMORY_SIZE - 4; 156 157 /* dac fix, the stack address must be 8-byte aligned! */ 158 gr[0] = gr[0] - gr[0] % 8; 159 gr[PARM1] = 0; 160 gr[PARM2] = 0; 161 gr[PARM3] = 0; 162 gr[PARM4] = gr[0]; 163 } 164 165 /* Simulate a monitor trap. */ 166 167 static void 168 handle_trap1 (SIM_DESC sd, SIM_CPU *cpu) 169 { 170 /* XXX: We don't pass back the actual errno value. */ 171 gr[RET1] = sim_syscall (cpu, gr[TRAPCODE], gr[PARM1], gr[PARM2], gr[PARM3], 172 gr[PARM4]); 173 } 174 175 static void 176 process_stub (SIM_DESC sd, SIM_CPU *cpu, int what) 177 { 178 /* These values should match those in libgloss/mcore/syscalls.s. */ 179 switch (what) 180 { 181 case 3: /* _read */ 182 case 4: /* _write */ 183 case 5: /* _open */ 184 case 6: /* _close */ 185 case 10: /* _unlink */ 186 case 19: /* _lseek */ 187 case 43: /* _times */ 188 gr[TRAPCODE] = what; 189 handle_trap1 (sd, cpu); 190 break; 191 192 default: 193 if (STATE_VERBOSE_P (sd)) 194 fprintf (stderr, "Unhandled stub opcode: %d\n", what); 195 break; 196 } 197 } 198 199 static void 200 util (SIM_DESC sd, SIM_CPU *cpu, unsigned what) 201 { 202 switch (what) 203 { 204 case 0: /* exit */ 205 sim_engine_halt (sd, cpu, NULL, cpu->regs.pc, sim_exited, gr[PARM1]); 206 break; 207 208 case 1: /* printf */ 209 if (STATE_VERBOSE_P (sd)) 210 fprintf (stderr, "WARNING: printf unimplemented\n"); 211 break; 212 213 case 2: /* scanf */ 214 if (STATE_VERBOSE_P (sd)) 215 fprintf (stderr, "WARNING: scanf unimplemented\n"); 216 break; 217 218 case 3: /* utime */ 219 gr[RET1] = cpu->insts; 220 break; 221 222 case 0xFF: 223 process_stub (sd, cpu, gr[1]); 224 break; 225 226 default: 227 if (STATE_VERBOSE_P (sd)) 228 fprintf (stderr, "Unhandled util code: %x\n", what); 229 break; 230 } 231 } 232 233 /* For figuring out whether we carried; addc/subc use this. */ 234 static int 235 iu_carry (unsigned long a, unsigned long b, int cin) 236 { 237 unsigned long x; 238 239 x = (a & 0xffff) + (b & 0xffff) + cin; 240 x = (x >> 16) + (a >> 16) + (b >> 16); 241 x >>= 16; 242 243 return (x != 0); 244 } 245 246 /* TODO: Convert to common watchpoints. */ 247 #undef WATCHFUNCTIONS 248 #ifdef WATCHFUNCTIONS 249 250 #define MAXWL 80 251 word WL[MAXWL]; 252 char * WLstr[MAXWL]; 253 254 int ENDWL=0; 255 int WLincyc; 256 int WLcyc[MAXWL]; 257 int WLcnts[MAXWL]; 258 int WLmax[MAXWL]; 259 int WLmin[MAXWL]; 260 word WLendpc; 261 int WLbcyc; 262 int WLW; 263 #endif 264 265 #define RD (inst & 0xF) 266 #define RS ((inst >> 4) & 0xF) 267 #define RX ((inst >> 8) & 0xF) 268 #define IMM5 ((inst >> 4) & 0x1F) 269 #define IMM4 ((inst) & 0xF) 270 271 #define rbat(X) sim_core_read_1 (cpu, 0, read_map, X) 272 #define rhat(X) sim_core_read_2 (cpu, 0, read_map, X) 273 #define rlat(X) sim_core_read_4 (cpu, 0, read_map, X) 274 #define wbat(X, D) sim_core_write_1 (cpu, 0, write_map, X, D) 275 #define what(X, D) sim_core_write_2 (cpu, 0, write_map, X, D) 276 #define wlat(X, D) sim_core_write_4 (cpu, 0, write_map, X, D) 277 278 static int tracing = 0; 279 280 #define ILLEGAL() \ 281 sim_engine_halt (sd, cpu, NULL, pc, sim_stopped, SIM_SIGILL) 282 283 static void 284 step_once (SIM_DESC sd, SIM_CPU *cpu) 285 { 286 int needfetch; 287 word ibuf; 288 word pc; 289 unsigned short inst; 290 int memops; 291 int bonus_cycles; 292 int insts; 293 int w; 294 int cycs; 295 #ifdef WATCHFUNCTIONS 296 word WLhash; 297 #endif 298 299 pc = CPU_PC_GET (cpu); 300 301 /* Fetch the initial instructions that we'll decode. */ 302 ibuf = rlat (pc & 0xFFFFFFFC); 303 needfetch = 0; 304 305 memops = 0; 306 bonus_cycles = 0; 307 insts = 0; 308 309 /* make our register set point to the right place */ 310 set_active_regs (cpu); 311 312 #ifdef WATCHFUNCTIONS 313 /* make a hash to speed exec loop, hope it's nonzero */ 314 WLhash = 0xFFFFFFFF; 315 316 for (w = 1; w <= ENDWL; w++) 317 WLhash = WLhash & WL[w]; 318 #endif 319 320 /* TODO: Unindent this block. */ 321 { 322 word oldpc; 323 324 insts ++; 325 326 if (pc & 02) 327 { 328 if (! target_big_endian) 329 inst = ibuf >> 16; 330 else 331 inst = ibuf & 0xFFFF; 332 needfetch = 1; 333 } 334 else 335 { 336 if (! target_big_endian) 337 inst = ibuf & 0xFFFF; 338 else 339 inst = ibuf >> 16; 340 } 341 342 #ifdef WATCHFUNCTIONS 343 /* now scan list of watch addresses, if match, count it and 344 note return address and count cycles until pc=return address */ 345 346 if ((WLincyc == 1) && (pc == WLendpc)) 347 { 348 cycs = (cpu->cycles + (insts + bonus_cycles + 349 (memops * memcycles)) - WLbcyc); 350 351 if (WLcnts[WLW] == 1) 352 { 353 WLmax[WLW] = cycs; 354 WLmin[WLW] = cycs; 355 WLcyc[WLW] = 0; 356 } 357 358 if (cycs > WLmax[WLW]) 359 { 360 WLmax[WLW] = cycs; 361 } 362 363 if (cycs < WLmin[WLW]) 364 { 365 WLmin[WLW] = cycs; 366 } 367 368 WLcyc[WLW] += cycs; 369 WLincyc = 0; 370 WLendpc = 0; 371 } 372 373 /* Optimize with a hash to speed loop. */ 374 if (WLincyc == 0) 375 { 376 if ((WLhash == 0) || ((WLhash & pc) != 0)) 377 { 378 for (w=1; w <= ENDWL; w++) 379 { 380 if (pc == WL[w]) 381 { 382 WLcnts[w]++; 383 WLbcyc = cpu->cycles + insts 384 + bonus_cycles + (memops * memcycles); 385 WLendpc = gr[15]; 386 WLincyc = 1; 387 WLW = w; 388 break; 389 } 390 } 391 } 392 } 393 #endif 394 395 if (tracing) 396 fprintf (stderr, "%.4lx: inst = %.4x ", pc, inst); 397 398 oldpc = pc; 399 400 pc += 2; 401 402 switch (inst >> 8) 403 { 404 case 0x00: 405 switch RS 406 { 407 case 0x0: 408 switch RD 409 { 410 case 0x0: /* bkpt */ 411 pc -= 2; 412 sim_engine_halt (sd, cpu, NULL, pc - 2, 413 sim_stopped, SIM_SIGTRAP); 414 break; 415 416 case 0x1: /* sync */ 417 break; 418 419 case 0x2: /* rte */ 420 pc = epc; 421 sr = esr; 422 needfetch = 1; 423 424 set_active_regs (cpu); 425 break; 426 427 case 0x3: /* rfi */ 428 pc = fpc; 429 sr = fsr; 430 needfetch = 1; 431 432 set_active_regs (cpu); 433 break; 434 435 case 0x4: /* stop */ 436 if (STATE_VERBOSE_P (sd)) 437 fprintf (stderr, "WARNING: stop unimplemented\n"); 438 break; 439 440 case 0x5: /* wait */ 441 if (STATE_VERBOSE_P (sd)) 442 fprintf (stderr, "WARNING: wait unimplemented\n"); 443 break; 444 445 case 0x6: /* doze */ 446 if (STATE_VERBOSE_P (sd)) 447 fprintf (stderr, "WARNING: doze unimplemented\n"); 448 break; 449 450 case 0x7: 451 ILLEGAL (); /* illegal */ 452 break; 453 454 case 0x8: /* trap 0 */ 455 case 0xA: /* trap 2 */ 456 case 0xB: /* trap 3 */ 457 sim_engine_halt (sd, cpu, NULL, pc, 458 sim_stopped, SIM_SIGTRAP); 459 break; 460 461 case 0xC: /* trap 4 */ 462 case 0xD: /* trap 5 */ 463 case 0xE: /* trap 6 */ 464 ILLEGAL (); /* illegal */ 465 break; 466 467 case 0xF: /* trap 7 */ 468 sim_engine_halt (sd, cpu, NULL, pc, /* integer div-by-0 */ 469 sim_stopped, SIM_SIGTRAP); 470 break; 471 472 case 0x9: /* trap 1 */ 473 handle_trap1 (sd, cpu); 474 break; 475 } 476 break; 477 478 case 0x1: 479 ILLEGAL (); /* illegal */ 480 break; 481 482 case 0x2: /* mvc */ 483 gr[RD] = C_VALUE(); 484 break; 485 case 0x3: /* mvcv */ 486 gr[RD] = C_OFF(); 487 break; 488 case 0x4: /* ldq */ 489 { 490 word addr = gr[RD]; 491 int regno = 4; /* always r4-r7 */ 492 493 bonus_cycles++; 494 memops += 4; 495 do 496 { 497 gr[regno] = rlat (addr); 498 addr += 4; 499 regno++; 500 } 501 while ((regno&0x3) != 0); 502 } 503 break; 504 case 0x5: /* stq */ 505 { 506 word addr = gr[RD]; 507 int regno = 4; /* always r4-r7 */ 508 509 memops += 4; 510 bonus_cycles++; 511 do 512 { 513 wlat (addr, gr[regno]); 514 addr += 4; 515 regno++; 516 } 517 while ((regno & 0x3) != 0); 518 } 519 break; 520 case 0x6: /* ldm */ 521 { 522 word addr = gr[0]; 523 int regno = RD; 524 525 /* bonus cycle is really only needed if 526 the next insn shifts the last reg loaded. 527 528 bonus_cycles++; 529 */ 530 memops += 16-regno; 531 while (regno <= 0xF) 532 { 533 gr[regno] = rlat (addr); 534 addr += 4; 535 regno++; 536 } 537 } 538 break; 539 case 0x7: /* stm */ 540 { 541 word addr = gr[0]; 542 int regno = RD; 543 544 /* this should be removed! */ 545 /* bonus_cycles ++; */ 546 547 memops += 16 - regno; 548 while (regno <= 0xF) 549 { 550 wlat (addr, gr[regno]); 551 addr += 4; 552 regno++; 553 } 554 } 555 break; 556 557 case 0x8: /* dect */ 558 gr[RD] -= C_VALUE(); 559 break; 560 case 0x9: /* decf */ 561 gr[RD] -= C_OFF(); 562 break; 563 case 0xA: /* inct */ 564 gr[RD] += C_VALUE(); 565 break; 566 case 0xB: /* incf */ 567 gr[RD] += C_OFF(); 568 break; 569 case 0xC: /* jmp */ 570 pc = gr[RD]; 571 if (tracing && RD == 15) 572 fprintf (stderr, "Func return, r2 = %lxx, r3 = %lx\n", 573 gr[2], gr[3]); 574 bonus_cycles++; 575 needfetch = 1; 576 break; 577 case 0xD: /* jsr */ 578 gr[15] = pc; 579 pc = gr[RD]; 580 bonus_cycles++; 581 needfetch = 1; 582 break; 583 case 0xE: /* ff1 */ 584 { 585 word tmp, i; 586 tmp = gr[RD]; 587 for (i = 0; !(tmp & 0x80000000) && i < 32; i++) 588 tmp <<= 1; 589 gr[RD] = i; 590 } 591 break; 592 case 0xF: /* brev */ 593 { 594 word tmp; 595 tmp = gr[RD]; 596 tmp = ((tmp & 0xaaaaaaaa) >> 1) | ((tmp & 0x55555555) << 1); 597 tmp = ((tmp & 0xcccccccc) >> 2) | ((tmp & 0x33333333) << 2); 598 tmp = ((tmp & 0xf0f0f0f0) >> 4) | ((tmp & 0x0f0f0f0f) << 4); 599 tmp = ((tmp & 0xff00ff00) >> 8) | ((tmp & 0x00ff00ff) << 8); 600 gr[RD] = ((tmp & 0xffff0000) >> 16) | ((tmp & 0x0000ffff) << 16); 601 } 602 break; 603 } 604 break; 605 case 0x01: 606 switch RS 607 { 608 case 0x0: /* xtrb3 */ 609 gr[1] = (gr[RD]) & 0xFF; 610 NEW_C (gr[RD] != 0); 611 break; 612 case 0x1: /* xtrb2 */ 613 gr[1] = (gr[RD]>>8) & 0xFF; 614 NEW_C (gr[RD] != 0); 615 break; 616 case 0x2: /* xtrb1 */ 617 gr[1] = (gr[RD]>>16) & 0xFF; 618 NEW_C (gr[RD] != 0); 619 break; 620 case 0x3: /* xtrb0 */ 621 gr[1] = (gr[RD]>>24) & 0xFF; 622 NEW_C (gr[RD] != 0); 623 break; 624 case 0x4: /* zextb */ 625 gr[RD] &= 0x000000FF; 626 break; 627 case 0x5: /* sextb */ 628 { 629 long tmp; 630 tmp = gr[RD]; 631 tmp <<= 24; 632 tmp >>= 24; 633 gr[RD] = tmp; 634 } 635 break; 636 case 0x6: /* zexth */ 637 gr[RD] &= 0x0000FFFF; 638 break; 639 case 0x7: /* sexth */ 640 { 641 long tmp; 642 tmp = gr[RD]; 643 tmp <<= 16; 644 tmp >>= 16; 645 gr[RD] = tmp; 646 } 647 break; 648 case 0x8: /* declt */ 649 --gr[RD]; 650 NEW_C ((long)gr[RD] < 0); 651 break; 652 case 0x9: /* tstnbz */ 653 { 654 word tmp = gr[RD]; 655 NEW_C ((tmp & 0xFF000000) != 0 && 656 (tmp & 0x00FF0000) != 0 && (tmp & 0x0000FF00) != 0 && 657 (tmp & 0x000000FF) != 0); 658 } 659 break; 660 case 0xA: /* decgt */ 661 --gr[RD]; 662 NEW_C ((long)gr[RD] > 0); 663 break; 664 case 0xB: /* decne */ 665 --gr[RD]; 666 NEW_C ((long)gr[RD] != 0); 667 break; 668 case 0xC: /* clrt */ 669 if (C_ON()) 670 gr[RD] = 0; 671 break; 672 case 0xD: /* clrf */ 673 if (C_OFF()) 674 gr[RD] = 0; 675 break; 676 case 0xE: /* abs */ 677 if (gr[RD] & 0x80000000) 678 gr[RD] = ~gr[RD] + 1; 679 break; 680 case 0xF: /* not */ 681 gr[RD] = ~gr[RD]; 682 break; 683 } 684 break; 685 case 0x02: /* movt */ 686 if (C_ON()) 687 gr[RD] = gr[RS]; 688 break; 689 case 0x03: /* mult */ 690 /* consume 2 bits per cycle from rs, until rs is 0 */ 691 { 692 unsigned int t = gr[RS]; 693 int ticks; 694 for (ticks = 0; t != 0 ; t >>= 2) 695 ticks++; 696 bonus_cycles += ticks; 697 } 698 bonus_cycles += 2; /* min. is 3, so add 2, plus ticks above */ 699 if (tracing) 700 fprintf (stderr, " mult %lx by %lx to give %lx", 701 gr[RD], gr[RS], gr[RD] * gr[RS]); 702 gr[RD] = gr[RD] * gr[RS]; 703 break; 704 case 0x04: /* loopt */ 705 if (C_ON()) 706 { 707 pc += (IMM4 << 1) - 32; 708 bonus_cycles ++; 709 needfetch = 1; 710 } 711 --gr[RS]; /* not RD! */ 712 NEW_C (((long)gr[RS]) > 0); 713 break; 714 case 0x05: /* subu */ 715 gr[RD] -= gr[RS]; 716 break; 717 case 0x06: /* addc */ 718 { 719 unsigned long tmp, a, b; 720 a = gr[RD]; 721 b = gr[RS]; 722 gr[RD] = a + b + C_VALUE (); 723 tmp = iu_carry (a, b, C_VALUE ()); 724 NEW_C (tmp); 725 } 726 break; 727 case 0x07: /* subc */ 728 { 729 unsigned long tmp, a, b; 730 a = gr[RD]; 731 b = gr[RS]; 732 gr[RD] = a - b + C_VALUE () - 1; 733 tmp = iu_carry (a,~b, C_VALUE ()); 734 NEW_C (tmp); 735 } 736 break; 737 case 0x08: /* illegal */ 738 case 0x09: /* illegal*/ 739 ILLEGAL (); 740 break; 741 case 0x0A: /* movf */ 742 if (C_OFF()) 743 gr[RD] = gr[RS]; 744 break; 745 case 0x0B: /* lsr */ 746 { 747 unsigned long dst, src; 748 dst = gr[RD]; 749 src = gr[RS]; 750 /* We must not rely solely upon the native shift operations, since they 751 may not match the M*Core's behaviour on boundary conditions. */ 752 dst = src > 31 ? 0 : dst >> src; 753 gr[RD] = dst; 754 } 755 break; 756 case 0x0C: /* cmphs */ 757 NEW_C ((unsigned long )gr[RD] >= 758 (unsigned long)gr[RS]); 759 break; 760 case 0x0D: /* cmplt */ 761 NEW_C ((long)gr[RD] < (long)gr[RS]); 762 break; 763 case 0x0E: /* tst */ 764 NEW_C ((gr[RD] & gr[RS]) != 0); 765 break; 766 case 0x0F: /* cmpne */ 767 NEW_C (gr[RD] != gr[RS]); 768 break; 769 case 0x10: case 0x11: /* mfcr */ 770 { 771 unsigned r; 772 r = IMM5; 773 if (r <= LAST_VALID_CREG) 774 gr[RD] = cr[r]; 775 else 776 ILLEGAL (); 777 } 778 break; 779 780 case 0x12: /* mov */ 781 gr[RD] = gr[RS]; 782 if (tracing) 783 fprintf (stderr, "MOV %lx into reg %d", gr[RD], RD); 784 break; 785 786 case 0x13: /* bgenr */ 787 if (gr[RS] & 0x20) 788 gr[RD] = 0; 789 else 790 gr[RD] = 1 << (gr[RS] & 0x1F); 791 break; 792 793 case 0x14: /* rsub */ 794 gr[RD] = gr[RS] - gr[RD]; 795 break; 796 797 case 0x15: /* ixw */ 798 gr[RD] += gr[RS]<<2; 799 break; 800 801 case 0x16: /* and */ 802 gr[RD] &= gr[RS]; 803 break; 804 805 case 0x17: /* xor */ 806 gr[RD] ^= gr[RS]; 807 break; 808 809 case 0x18: case 0x19: /* mtcr */ 810 { 811 unsigned r; 812 r = IMM5; 813 if (r <= LAST_VALID_CREG) 814 cr[r] = gr[RD]; 815 else 816 ILLEGAL (); 817 818 /* we might have changed register sets... */ 819 set_active_regs (cpu); 820 } 821 break; 822 823 case 0x1A: /* asr */ 824 /* We must not rely solely upon the native shift operations, since they 825 may not match the M*Core's behaviour on boundary conditions. */ 826 if (gr[RS] > 30) 827 gr[RD] = ((long) gr[RD]) < 0 ? -1 : 0; 828 else 829 gr[RD] = (long) gr[RD] >> gr[RS]; 830 break; 831 832 case 0x1B: /* lsl */ 833 /* We must not rely solely upon the native shift operations, since they 834 may not match the M*Core's behaviour on boundary conditions. */ 835 gr[RD] = gr[RS] > 31 ? 0 : gr[RD] << gr[RS]; 836 break; 837 838 case 0x1C: /* addu */ 839 gr[RD] += gr[RS]; 840 break; 841 842 case 0x1D: /* ixh */ 843 gr[RD] += gr[RS] << 1; 844 break; 845 846 case 0x1E: /* or */ 847 gr[RD] |= gr[RS]; 848 break; 849 850 case 0x1F: /* andn */ 851 gr[RD] &= ~gr[RS]; 852 break; 853 case 0x20: case 0x21: /* addi */ 854 gr[RD] = 855 gr[RD] + (IMM5 + 1); 856 break; 857 case 0x22: case 0x23: /* cmplti */ 858 { 859 int tmp = (IMM5 + 1); 860 if (gr[RD] < tmp) 861 { 862 SET_C(); 863 } 864 else 865 { 866 CLR_C(); 867 } 868 } 869 break; 870 case 0x24: case 0x25: /* subi */ 871 gr[RD] = 872 gr[RD] - (IMM5 + 1); 873 break; 874 case 0x26: case 0x27: /* illegal */ 875 ILLEGAL (); 876 break; 877 case 0x28: case 0x29: /* rsubi */ 878 gr[RD] = 879 IMM5 - gr[RD]; 880 break; 881 case 0x2A: case 0x2B: /* cmpnei */ 882 if (gr[RD] != IMM5) 883 { 884 SET_C(); 885 } 886 else 887 { 888 CLR_C(); 889 } 890 break; 891 892 case 0x2C: case 0x2D: /* bmaski, divu */ 893 { 894 unsigned imm = IMM5; 895 896 if (imm == 1) 897 { 898 int exe; 899 int rxnlz, r1nlz; 900 unsigned int rx, r1; 901 902 rx = gr[RD]; 903 r1 = gr[1]; 904 exe = 0; 905 906 /* unsigned divide */ 907 gr[RD] = (word) ((unsigned int) gr[RD] / (unsigned int)gr[1] ); 908 909 /* compute bonus_cycles for divu */ 910 for (r1nlz = 0; ((r1 & 0x80000000) == 0) && (r1nlz < 32); r1nlz ++) 911 r1 = r1 << 1; 912 913 for (rxnlz = 0; ((rx & 0x80000000) == 0) && (rxnlz < 32); rxnlz ++) 914 rx = rx << 1; 915 916 if (r1nlz < rxnlz) 917 exe += 4; 918 else 919 exe += 5 + r1nlz - rxnlz; 920 921 if (exe >= (2 * memcycles - 1)) 922 { 923 bonus_cycles += exe - (2 * memcycles) + 1; 924 } 925 } 926 else if (imm == 0 || imm >= 8) 927 { 928 /* bmaski */ 929 if (imm == 0) 930 gr[RD] = -1; 931 else 932 gr[RD] = (1 << imm) - 1; 933 } 934 else 935 { 936 /* illegal */ 937 ILLEGAL (); 938 } 939 } 940 break; 941 case 0x2E: case 0x2F: /* andi */ 942 gr[RD] = gr[RD] & IMM5; 943 break; 944 case 0x30: case 0x31: /* bclri */ 945 gr[RD] = gr[RD] & ~(1<<IMM5); 946 break; 947 case 0x32: case 0x33: /* bgeni, divs */ 948 { 949 unsigned imm = IMM5; 950 if (imm == 1) 951 { 952 int exe,sc; 953 int rxnlz, r1nlz; 954 signed int rx, r1; 955 956 /* compute bonus_cycles for divu */ 957 rx = gr[RD]; 958 r1 = gr[1]; 959 exe = 0; 960 961 if (((rx < 0) && (r1 > 0)) || ((rx >= 0) && (r1 < 0))) 962 sc = 1; 963 else 964 sc = 0; 965 966 rx = abs (rx); 967 r1 = abs (r1); 968 969 /* signed divide, general registers are of type int, so / op is OK */ 970 gr[RD] = gr[RD] / gr[1]; 971 972 for (r1nlz = 0; ((r1 & 0x80000000) == 0) && (r1nlz < 32) ; r1nlz ++ ) 973 r1 = r1 << 1; 974 975 for (rxnlz = 0; ((rx & 0x80000000) == 0) && (rxnlz < 32) ; rxnlz ++ ) 976 rx = rx << 1; 977 978 if (r1nlz < rxnlz) 979 exe += 5; 980 else 981 exe += 6 + r1nlz - rxnlz + sc; 982 983 if (exe >= (2 * memcycles - 1)) 984 { 985 bonus_cycles += exe - (2 * memcycles) + 1; 986 } 987 } 988 else if (imm >= 7) 989 { 990 /* bgeni */ 991 gr[RD] = (1 << IMM5); 992 } 993 else 994 { 995 /* illegal */ 996 ILLEGAL (); 997 } 998 break; 999 } 1000 case 0x34: case 0x35: /* bseti */ 1001 gr[RD] = gr[RD] | (1 << IMM5); 1002 break; 1003 case 0x36: case 0x37: /* btsti */ 1004 NEW_C (gr[RD] >> IMM5); 1005 break; 1006 case 0x38: case 0x39: /* xsr, rotli */ 1007 { 1008 unsigned imm = IMM5; 1009 unsigned long tmp = gr[RD]; 1010 if (imm == 0) 1011 { 1012 word cbit; 1013 cbit = C_VALUE(); 1014 NEW_C (tmp); 1015 gr[RD] = (cbit << 31) | (tmp >> 1); 1016 } 1017 else 1018 gr[RD] = (tmp << imm) | (tmp >> (32 - imm)); 1019 } 1020 break; 1021 case 0x3A: case 0x3B: /* asrc, asri */ 1022 { 1023 unsigned imm = IMM5; 1024 long tmp = gr[RD]; 1025 if (imm == 0) 1026 { 1027 NEW_C (tmp); 1028 gr[RD] = tmp >> 1; 1029 } 1030 else 1031 gr[RD] = tmp >> imm; 1032 } 1033 break; 1034 case 0x3C: case 0x3D: /* lslc, lsli */ 1035 { 1036 unsigned imm = IMM5; 1037 unsigned long tmp = gr[RD]; 1038 if (imm == 0) 1039 { 1040 NEW_C (tmp >> 31); 1041 gr[RD] = tmp << 1; 1042 } 1043 else 1044 gr[RD] = tmp << imm; 1045 } 1046 break; 1047 case 0x3E: case 0x3F: /* lsrc, lsri */ 1048 { 1049 unsigned imm = IMM5; 1050 unsigned long tmp = gr[RD]; 1051 if (imm == 0) 1052 { 1053 NEW_C (tmp); 1054 gr[RD] = tmp >> 1; 1055 } 1056 else 1057 gr[RD] = tmp >> imm; 1058 } 1059 break; 1060 case 0x40: case 0x41: case 0x42: case 0x43: 1061 case 0x44: case 0x45: case 0x46: case 0x47: 1062 case 0x48: case 0x49: case 0x4A: case 0x4B: 1063 case 0x4C: case 0x4D: case 0x4E: case 0x4F: 1064 ILLEGAL (); 1065 break; 1066 case 0x50: 1067 util (sd, cpu, inst & 0xFF); 1068 break; 1069 case 0x51: case 0x52: case 0x53: 1070 case 0x54: case 0x55: case 0x56: case 0x57: 1071 case 0x58: case 0x59: case 0x5A: case 0x5B: 1072 case 0x5C: case 0x5D: case 0x5E: case 0x5F: 1073 ILLEGAL (); 1074 break; 1075 case 0x60: case 0x61: case 0x62: case 0x63: /* movi */ 1076 case 0x64: case 0x65: case 0x66: case 0x67: 1077 gr[RD] = (inst >> 4) & 0x7F; 1078 break; 1079 case 0x68: case 0x69: case 0x6A: case 0x6B: 1080 case 0x6C: case 0x6D: case 0x6E: case 0x6F: /* illegal */ 1081 ILLEGAL (); 1082 break; 1083 case 0x71: case 0x72: case 0x73: 1084 case 0x74: case 0x75: case 0x76: case 0x77: 1085 case 0x78: case 0x79: case 0x7A: case 0x7B: 1086 case 0x7C: case 0x7D: case 0x7E: /* lrw */ 1087 gr[RX] = rlat ((pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC); 1088 if (tracing) 1089 fprintf (stderr, "LRW of 0x%x from 0x%lx to reg %d", 1090 rlat ((pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC), 1091 (pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC, RX); 1092 memops++; 1093 break; 1094 case 0x7F: /* jsri */ 1095 gr[15] = pc; 1096 if (tracing) 1097 fprintf (stderr, 1098 "func call: r2 = %lx r3 = %lx r4 = %lx r5 = %lx r6 = %lx r7 = %lx\n", 1099 gr[2], gr[3], gr[4], gr[5], gr[6], gr[7]); 1100 case 0x70: /* jmpi */ 1101 pc = rlat ((pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC); 1102 memops++; 1103 bonus_cycles++; 1104 needfetch = 1; 1105 break; 1106 1107 case 0x80: case 0x81: case 0x82: case 0x83: 1108 case 0x84: case 0x85: case 0x86: case 0x87: 1109 case 0x88: case 0x89: case 0x8A: case 0x8B: 1110 case 0x8C: case 0x8D: case 0x8E: case 0x8F: /* ld */ 1111 gr[RX] = rlat (gr[RD] + ((inst >> 2) & 0x003C)); 1112 if (tracing) 1113 fprintf (stderr, "load reg %d from 0x%lx with 0x%lx", 1114 RX, 1115 gr[RD] + ((inst >> 2) & 0x003C), gr[RX]); 1116 memops++; 1117 break; 1118 case 0x90: case 0x91: case 0x92: case 0x93: 1119 case 0x94: case 0x95: case 0x96: case 0x97: 1120 case 0x98: case 0x99: case 0x9A: case 0x9B: 1121 case 0x9C: case 0x9D: case 0x9E: case 0x9F: /* st */ 1122 wlat (gr[RD] + ((inst >> 2) & 0x003C), gr[RX]); 1123 if (tracing) 1124 fprintf (stderr, "store reg %d (containing 0x%lx) to 0x%lx", 1125 RX, gr[RX], 1126 gr[RD] + ((inst >> 2) & 0x003C)); 1127 memops++; 1128 break; 1129 case 0xA0: case 0xA1: case 0xA2: case 0xA3: 1130 case 0xA4: case 0xA5: case 0xA6: case 0xA7: 1131 case 0xA8: case 0xA9: case 0xAA: case 0xAB: 1132 case 0xAC: case 0xAD: case 0xAE: case 0xAF: /* ld.b */ 1133 gr[RX] = rbat (gr[RD] + RS); 1134 memops++; 1135 break; 1136 case 0xB0: case 0xB1: case 0xB2: case 0xB3: 1137 case 0xB4: case 0xB5: case 0xB6: case 0xB7: 1138 case 0xB8: case 0xB9: case 0xBA: case 0xBB: 1139 case 0xBC: case 0xBD: case 0xBE: case 0xBF: /* st.b */ 1140 wbat (gr[RD] + RS, gr[RX]); 1141 memops++; 1142 break; 1143 case 0xC0: case 0xC1: case 0xC2: case 0xC3: 1144 case 0xC4: case 0xC5: case 0xC6: case 0xC7: 1145 case 0xC8: case 0xC9: case 0xCA: case 0xCB: 1146 case 0xCC: case 0xCD: case 0xCE: case 0xCF: /* ld.h */ 1147 gr[RX] = rhat (gr[RD] + ((inst >> 3) & 0x001E)); 1148 memops++; 1149 break; 1150 case 0xD0: case 0xD1: case 0xD2: case 0xD3: 1151 case 0xD4: case 0xD5: case 0xD6: case 0xD7: 1152 case 0xD8: case 0xD9: case 0xDA: case 0xDB: 1153 case 0xDC: case 0xDD: case 0xDE: case 0xDF: /* st.h */ 1154 what (gr[RD] + ((inst >> 3) & 0x001E), gr[RX]); 1155 memops++; 1156 break; 1157 case 0xE8: case 0xE9: case 0xEA: case 0xEB: 1158 case 0xEC: case 0xED: case 0xEE: case 0xEF: /* bf */ 1159 if (C_OFF()) 1160 { 1161 int disp; 1162 disp = inst & 0x03FF; 1163 if (inst & 0x0400) 1164 disp |= 0xFFFFFC00; 1165 pc += disp<<1; 1166 bonus_cycles++; 1167 needfetch = 1; 1168 } 1169 break; 1170 case 0xE0: case 0xE1: case 0xE2: case 0xE3: 1171 case 0xE4: case 0xE5: case 0xE6: case 0xE7: /* bt */ 1172 if (C_ON()) 1173 { 1174 int disp; 1175 disp = inst & 0x03FF; 1176 if (inst & 0x0400) 1177 disp |= 0xFFFFFC00; 1178 pc += disp<<1; 1179 bonus_cycles++; 1180 needfetch = 1; 1181 } 1182 break; 1183 1184 case 0xF8: case 0xF9: case 0xFA: case 0xFB: 1185 case 0xFC: case 0xFD: case 0xFE: case 0xFF: /* bsr */ 1186 gr[15] = pc; 1187 case 0xF0: case 0xF1: case 0xF2: case 0xF3: 1188 case 0xF4: case 0xF5: case 0xF6: case 0xF7: /* br */ 1189 { 1190 int disp; 1191 disp = inst & 0x03FF; 1192 if (inst & 0x0400) 1193 disp |= 0xFFFFFC00; 1194 pc += disp<<1; 1195 bonus_cycles++; 1196 needfetch = 1; 1197 } 1198 break; 1199 1200 } 1201 1202 if (tracing) 1203 fprintf (stderr, "\n"); 1204 1205 if (needfetch) 1206 { 1207 ibuf = rlat (pc & 0xFFFFFFFC); 1208 needfetch = 0; 1209 } 1210 } 1211 1212 /* Hide away the things we've cached while executing. */ 1213 CPU_PC_SET (cpu, pc); 1214 cpu->insts += insts; /* instructions done ... */ 1215 cpu->cycles += insts; /* and each takes a cycle */ 1216 cpu->cycles += bonus_cycles; /* and extra cycles for branches */ 1217 cpu->cycles += memops * memcycles; /* and memop cycle delays */ 1218 } 1219 1220 void 1221 sim_engine_run (SIM_DESC sd, 1222 int next_cpu_nr, /* ignore */ 1223 int nr_cpus, /* ignore */ 1224 int siggnal) /* ignore */ 1225 { 1226 sim_cpu *cpu; 1227 1228 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); 1229 1230 cpu = STATE_CPU (sd, 0); 1231 1232 while (1) 1233 { 1234 step_once (sd, cpu); 1235 if (sim_events_tick (sd)) 1236 sim_events_process (sd); 1237 } 1238 } 1239 1240 static int 1241 mcore_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length) 1242 { 1243 if (rn < NUM_MCORE_REGS && rn >= 0) 1244 { 1245 if (length == 4) 1246 { 1247 long ival; 1248 1249 /* misalignment safe */ 1250 ival = mcore_extract_unsigned_integer (memory, 4); 1251 cpu->asints[rn] = ival; 1252 } 1253 1254 return 4; 1255 } 1256 else 1257 return 0; 1258 } 1259 1260 static int 1261 mcore_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) 1262 { 1263 if (rn < NUM_MCORE_REGS && rn >= 0) 1264 { 1265 if (length == 4) 1266 { 1267 long ival = cpu->asints[rn]; 1268 1269 /* misalignment-safe */ 1270 mcore_store_unsigned_integer (memory, 4, ival); 1271 } 1272 1273 return 4; 1274 } 1275 else 1276 return 0; 1277 } 1278 1279 void 1280 sim_info (SIM_DESC sd, int verbose) 1281 { 1282 SIM_CPU *cpu = STATE_CPU (sd, 0); 1283 #ifdef WATCHFUNCTIONS 1284 int w, wcyc; 1285 #endif 1286 double virttime = cpu->cycles / 36.0e6; 1287 host_callback *callback = STATE_CALLBACK (sd); 1288 1289 callback->printf_filtered (callback, "\n\n# instructions executed %10d\n", 1290 cpu->insts); 1291 callback->printf_filtered (callback, "# cycles %10d\n", 1292 cpu->cycles); 1293 callback->printf_filtered (callback, "# pipeline stalls %10d\n", 1294 cpu->stalls); 1295 callback->printf_filtered (callback, "# virtual time taken %10.4f\n", 1296 virttime); 1297 1298 #ifdef WATCHFUNCTIONS 1299 callback->printf_filtered (callback, "\nNumber of watched functions: %d\n", 1300 ENDWL); 1301 1302 wcyc = 0; 1303 1304 for (w = 1; w <= ENDWL; w++) 1305 { 1306 callback->printf_filtered (callback, "WL = %s %8x\n",WLstr[w],WL[w]); 1307 callback->printf_filtered (callback, " calls = %d, cycles = %d\n", 1308 WLcnts[w],WLcyc[w]); 1309 1310 if (WLcnts[w] != 0) 1311 callback->printf_filtered (callback, 1312 " maxcpc = %d, mincpc = %d, avecpc = %d\n", 1313 WLmax[w],WLmin[w],WLcyc[w]/WLcnts[w]); 1314 wcyc += WLcyc[w]; 1315 } 1316 1317 callback->printf_filtered (callback, 1318 "Total cycles for watched functions: %d\n",wcyc); 1319 #endif 1320 } 1321 1322 static sim_cia 1323 mcore_pc_get (sim_cpu *cpu) 1324 { 1325 return cpu->regs.pc; 1326 } 1327 1328 static void 1329 mcore_pc_set (sim_cpu *cpu, sim_cia pc) 1330 { 1331 cpu->regs.pc = pc; 1332 } 1333 1334 static void 1335 free_state (SIM_DESC sd) 1336 { 1337 if (STATE_MODULES (sd) != NULL) 1338 sim_module_uninstall (sd); 1339 sim_cpu_free_all (sd); 1340 sim_state_free (sd); 1341 } 1342 1343 SIM_DESC 1344 sim_open (SIM_OPEN_KIND kind, host_callback *cb, 1345 struct bfd *abfd, char * const *argv) 1346 { 1347 int i; 1348 SIM_DESC sd = sim_state_alloc (kind, cb); 1349 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); 1350 1351 /* The cpu data is kept in a separately allocated chunk of memory. */ 1352 if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK) 1353 { 1354 free_state (sd); 1355 return 0; 1356 } 1357 1358 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) 1359 { 1360 free_state (sd); 1361 return 0; 1362 } 1363 1364 /* The parser will print an error message for us, so we silently return. */ 1365 if (sim_parse_args (sd, argv) != SIM_RC_OK) 1366 { 1367 free_state (sd); 1368 return 0; 1369 } 1370 1371 /* Check for/establish the a reference program image. */ 1372 if (sim_analyze_program (sd, 1373 (STATE_PROG_ARGV (sd) != NULL 1374 ? *STATE_PROG_ARGV (sd) 1375 : NULL), abfd) != SIM_RC_OK) 1376 { 1377 free_state (sd); 1378 return 0; 1379 } 1380 1381 /* Configure/verify the target byte order and other runtime 1382 configuration options. */ 1383 if (sim_config (sd) != SIM_RC_OK) 1384 { 1385 sim_module_uninstall (sd); 1386 return 0; 1387 } 1388 1389 if (sim_post_argv_init (sd) != SIM_RC_OK) 1390 { 1391 /* Uninstall the modules to avoid memory leaks, 1392 file descriptor leaks, etc. */ 1393 sim_module_uninstall (sd); 1394 return 0; 1395 } 1396 1397 /* CPU specific initialization. */ 1398 for (i = 0; i < MAX_NR_PROCESSORS; ++i) 1399 { 1400 SIM_CPU *cpu = STATE_CPU (sd, i); 1401 1402 CPU_REG_FETCH (cpu) = mcore_reg_fetch; 1403 CPU_REG_STORE (cpu) = mcore_reg_store; 1404 CPU_PC_FETCH (cpu) = mcore_pc_get; 1405 CPU_PC_STORE (cpu) = mcore_pc_set; 1406 1407 set_initial_gprs (cpu); /* Reset the GPR registers. */ 1408 } 1409 1410 /* Default to a 8 Mbyte (== 2^23) memory space. */ 1411 sim_do_commandf (sd, "memory-size %#x", DEFAULT_MEMORY_SIZE); 1412 1413 return sd; 1414 } 1415 1416 SIM_RC 1417 sim_create_inferior (SIM_DESC sd, struct bfd *prog_bfd, 1418 char * const *argv, char * const *env) 1419 { 1420 SIM_CPU *cpu = STATE_CPU (sd, 0); 1421 char ** avp; 1422 int nargs = 0; 1423 int nenv = 0; 1424 int s_length; 1425 int l; 1426 unsigned long strings; 1427 unsigned long pointers; 1428 unsigned long hi_stack; 1429 1430 1431 /* Set the initial register set. */ 1432 set_initial_gprs (cpu); 1433 1434 hi_stack = DEFAULT_MEMORY_SIZE - 4; 1435 CPU_PC_SET (cpu, bfd_get_start_address (prog_bfd)); 1436 1437 /* Calculate the argument and environment strings. */ 1438 s_length = 0; 1439 nargs = 0; 1440 avp = argv; 1441 while (avp && *avp) 1442 { 1443 l = strlen (*avp) + 1; /* include the null */ 1444 s_length += (l + 3) & ~3; /* make it a 4 byte boundary */ 1445 nargs++; avp++; 1446 } 1447 1448 nenv = 0; 1449 avp = env; 1450 while (avp && *avp) 1451 { 1452 l = strlen (*avp) + 1; /* include the null */ 1453 s_length += (l + 3) & ~ 3;/* make it a 4 byte boundary */ 1454 nenv++; avp++; 1455 } 1456 1457 /* Claim some memory for the pointers and strings. */ 1458 pointers = hi_stack - sizeof(word) * (nenv+1+nargs+1); 1459 pointers &= ~3; /* must be 4-byte aligned */ 1460 gr[0] = pointers; 1461 1462 strings = gr[0] - s_length; 1463 strings &= ~3; /* want to make it 4-byte aligned */ 1464 gr[0] = strings; 1465 /* dac fix, the stack address must be 8-byte aligned! */ 1466 gr[0] = gr[0] - gr[0] % 8; 1467 1468 /* Loop through the arguments and fill them in. */ 1469 gr[PARM1] = nargs; 1470 if (nargs == 0) 1471 { 1472 /* No strings to fill in. */ 1473 gr[PARM2] = 0; 1474 } 1475 else 1476 { 1477 gr[PARM2] = pointers; 1478 avp = argv; 1479 while (avp && *avp) 1480 { 1481 /* Save where we're putting it. */ 1482 wlat (pointers, strings); 1483 1484 /* Copy the string. */ 1485 l = strlen (* avp) + 1; 1486 sim_core_write_buffer (sd, cpu, write_map, *avp, strings, l); 1487 1488 /* Bump the pointers. */ 1489 avp++; 1490 pointers += 4; 1491 strings += l+1; 1492 } 1493 1494 /* A null to finish the list. */ 1495 wlat (pointers, 0); 1496 pointers += 4; 1497 } 1498 1499 /* Now do the environment pointers. */ 1500 if (nenv == 0) 1501 { 1502 /* No strings to fill in. */ 1503 gr[PARM3] = 0; 1504 } 1505 else 1506 { 1507 gr[PARM3] = pointers; 1508 avp = env; 1509 1510 while (avp && *avp) 1511 { 1512 /* Save where we're putting it. */ 1513 wlat (pointers, strings); 1514 1515 /* Copy the string. */ 1516 l = strlen (* avp) + 1; 1517 sim_core_write_buffer (sd, cpu, write_map, *avp, strings, l); 1518 1519 /* Bump the pointers. */ 1520 avp++; 1521 pointers += 4; 1522 strings += l+1; 1523 } 1524 1525 /* A null to finish the list. */ 1526 wlat (pointers, 0); 1527 pointers += 4; 1528 } 1529 1530 return SIM_RC_OK; 1531 } 1532