1 /* m32r exception, interrupt, and trap (EIT) support 2 Copyright (C) 1998-2015 Free Software Foundation, Inc. 3 Contributed by Cygnus Solutions. 4 5 This file is part of GDB, the GNU debugger. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #include "sim-main.h" 21 #include "sim-syscall.h" 22 #include "targ-vals.h" 23 24 #define TRAP_FLUSH_CACHE 12 25 /* The semantic code invokes this for invalid (unrecognized) instructions. */ 26 27 SEM_PC 28 sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC pc) 29 { 30 SIM_DESC sd = CPU_STATE (current_cpu); 31 32 #if 0 33 if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) 34 { 35 h_bsm_set (current_cpu, h_sm_get (current_cpu)); 36 h_bie_set (current_cpu, h_ie_get (current_cpu)); 37 h_bcond_set (current_cpu, h_cond_get (current_cpu)); 38 /* sm not changed */ 39 h_ie_set (current_cpu, 0); 40 h_cond_set (current_cpu, 0); 41 42 h_bpc_set (current_cpu, cia); 43 44 sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL, 45 EIT_RSVD_INSN_ADDR); 46 } 47 else 48 #endif 49 sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL); 50 51 return pc; 52 } 53 54 /* Process an address exception. */ 55 56 void 57 m32r_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia, 58 unsigned int map, int nr_bytes, address_word addr, 59 transfer_type transfer, sim_core_signals sig) 60 { 61 if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) 62 { 63 m32rbf_h_cr_set (current_cpu, H_CR_BBPC, 64 m32rbf_h_cr_get (current_cpu, H_CR_BPC)); 65 switch (MACH_NUM (CPU_MACH (current_cpu))) 66 { 67 case MACH_M32R: 68 m32rbf_h_bpsw_set (current_cpu, m32rbf_h_psw_get (current_cpu)); 69 /* sm not changed. */ 70 m32rbf_h_psw_set (current_cpu, m32rbf_h_psw_get (current_cpu) & 0x80); 71 break; 72 case MACH_M32RX: 73 m32rxf_h_bpsw_set (current_cpu, m32rxf_h_psw_get (current_cpu)); 74 /* sm not changed. */ 75 m32rxf_h_psw_set (current_cpu, m32rxf_h_psw_get (current_cpu) & 0x80); 76 break; 77 case MACH_M32R2: 78 m32r2f_h_bpsw_set (current_cpu, m32r2f_h_psw_get (current_cpu)); 79 /* sm not changed. */ 80 m32r2f_h_psw_set (current_cpu, m32r2f_h_psw_get (current_cpu) & 0x80); 81 break; 82 default: 83 abort (); 84 } 85 86 m32rbf_h_cr_set (current_cpu, H_CR_BPC, cia); 87 88 sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL, 89 EIT_ADDR_EXCP_ADDR); 90 } 91 else 92 sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr, 93 transfer, sig); 94 } 95 96 /* Trap support. 97 The result is the pc address to continue at. 98 Preprocessing like saving the various registers has already been done. */ 99 100 USI 101 m32r_trap (SIM_CPU *current_cpu, PCADDR pc, int num) 102 { 103 SIM_DESC sd = CPU_STATE (current_cpu); 104 host_callback *cb = STATE_CALLBACK (sd); 105 106 #ifdef SIM_HAVE_BREAKPOINTS 107 /* Check for breakpoints "owned" by the simulator first, regardless 108 of --environment. */ 109 if (num == TRAP_BREAKPOINT) 110 { 111 /* First try sim-break.c. If it's a breakpoint the simulator "owns" 112 it doesn't return. Otherwise it returns and let's us try. */ 113 sim_handle_breakpoint (sd, current_cpu, pc); 114 /* Fall through. */ 115 } 116 #endif 117 118 if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) 119 { 120 /* The new pc is the trap vector entry. 121 We assume there's a branch there to some handler. 122 Use cr5 as EVB (EIT Vector Base) register. */ 123 /* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */ 124 USI new_pc = m32rbf_h_cr_get (current_cpu, 5) + 0x40 + num * 4; 125 return new_pc; 126 } 127 128 switch (num) 129 { 130 case TRAP_SYSCALL : 131 { 132 long result, result2; 133 int errcode; 134 135 sim_syscall_multi (current_cpu, 136 m32rbf_h_gr_get (current_cpu, 0), 137 m32rbf_h_gr_get (current_cpu, 1), 138 m32rbf_h_gr_get (current_cpu, 2), 139 m32rbf_h_gr_get (current_cpu, 3), 140 m32rbf_h_gr_get (current_cpu, 4), 141 &result, &result2, &errcode); 142 143 m32rbf_h_gr_set (current_cpu, 2, errcode); 144 m32rbf_h_gr_set (current_cpu, 0, result); 145 m32rbf_h_gr_set (current_cpu, 1, result2); 146 break; 147 } 148 149 case TRAP_BREAKPOINT: 150 sim_engine_halt (sd, current_cpu, NULL, pc, 151 sim_stopped, SIM_SIGTRAP); 152 break; 153 154 case TRAP_FLUSH_CACHE: 155 /* Do nothing. */ 156 break; 157 158 default : 159 { 160 /* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */ 161 /* Use cr5 as EVB (EIT Vector Base) register. */ 162 USI new_pc = m32rbf_h_cr_get (current_cpu, 5) + 0x40 + num * 4; 163 return new_pc; 164 } 165 } 166 167 /* Fake an "rte" insn. */ 168 /* FIXME: Should duplicate all of rte processing. */ 169 return (pc & -4) + 4; 170 } 171