1 /* Simulator instruction decoder for m32rxf. 2 3 THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5 Copyright 1996-2010 Free Software Foundation, Inc. 6 7 This file is part of the GNU simulators. 8 9 This file is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License along 20 with this program; if not, write to the Free Software Foundation, Inc., 21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 22 23 */ 24 25 #define WANT_CPU m32rxf 26 #define WANT_CPU_M32RXF 27 28 #include "sim-main.h" 29 #include "sim-assert.h" 30 31 /* Insn can't be executed in parallel. 32 Or is that "do NOt Pass to Air defense Radar"? :-) */ 33 #define NOPAR (-1) 34 35 /* The instruction descriptor array. 36 This is computed at runtime. Space for it is not malloc'd to save a 37 teensy bit of cpu in the decoder. Moving it to malloc space is trivial 38 but won't be done until necessary (we don't currently support the runtime 39 addition of instructions nor an SMP machine with different cpus). */ 40 static IDESC m32rxf_insn_data[M32RXF_INSN__MAX]; 41 42 /* Commas between elements are contained in the macros. 43 Some of these are conditionally compiled out. */ 44 45 static const struct insn_sem m32rxf_insn_sem[] = 46 { 47 { VIRTUAL_INSN_X_INVALID, M32RXF_INSN_X_INVALID, M32RXF_SFMT_EMPTY, NOPAR, NOPAR }, 48 { VIRTUAL_INSN_X_AFTER, M32RXF_INSN_X_AFTER, M32RXF_SFMT_EMPTY, NOPAR, NOPAR }, 49 { VIRTUAL_INSN_X_BEFORE, M32RXF_INSN_X_BEFORE, M32RXF_SFMT_EMPTY, NOPAR, NOPAR }, 50 { VIRTUAL_INSN_X_CTI_CHAIN, M32RXF_INSN_X_CTI_CHAIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR }, 51 { VIRTUAL_INSN_X_CHAIN, M32RXF_INSN_X_CHAIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR }, 52 { VIRTUAL_INSN_X_BEGIN, M32RXF_INSN_X_BEGIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR }, 53 { M32R_INSN_ADD, M32RXF_INSN_ADD, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_ADD, M32RXF_INSN_WRITE_ADD }, 54 { M32R_INSN_ADD3, M32RXF_INSN_ADD3, M32RXF_SFMT_ADD3, NOPAR, NOPAR }, 55 { M32R_INSN_AND, M32RXF_INSN_AND, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_AND, M32RXF_INSN_WRITE_AND }, 56 { M32R_INSN_AND3, M32RXF_INSN_AND3, M32RXF_SFMT_AND3, NOPAR, NOPAR }, 57 { M32R_INSN_OR, M32RXF_INSN_OR, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_OR, M32RXF_INSN_WRITE_OR }, 58 { M32R_INSN_OR3, M32RXF_INSN_OR3, M32RXF_SFMT_OR3, NOPAR, NOPAR }, 59 { M32R_INSN_XOR, M32RXF_INSN_XOR, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_XOR, M32RXF_INSN_WRITE_XOR }, 60 { M32R_INSN_XOR3, M32RXF_INSN_XOR3, M32RXF_SFMT_AND3, NOPAR, NOPAR }, 61 { M32R_INSN_ADDI, M32RXF_INSN_ADDI, M32RXF_SFMT_ADDI, M32RXF_INSN_PAR_ADDI, M32RXF_INSN_WRITE_ADDI }, 62 { M32R_INSN_ADDV, M32RXF_INSN_ADDV, M32RXF_SFMT_ADDV, M32RXF_INSN_PAR_ADDV, M32RXF_INSN_WRITE_ADDV }, 63 { M32R_INSN_ADDV3, M32RXF_INSN_ADDV3, M32RXF_SFMT_ADDV3, NOPAR, NOPAR }, 64 { M32R_INSN_ADDX, M32RXF_INSN_ADDX, M32RXF_SFMT_ADDX, M32RXF_INSN_PAR_ADDX, M32RXF_INSN_WRITE_ADDX }, 65 { M32R_INSN_BC8, M32RXF_INSN_BC8, M32RXF_SFMT_BC8, M32RXF_INSN_PAR_BC8, M32RXF_INSN_WRITE_BC8 }, 66 { M32R_INSN_BC24, M32RXF_INSN_BC24, M32RXF_SFMT_BC24, NOPAR, NOPAR }, 67 { M32R_INSN_BEQ, M32RXF_INSN_BEQ, M32RXF_SFMT_BEQ, NOPAR, NOPAR }, 68 { M32R_INSN_BEQZ, M32RXF_INSN_BEQZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR }, 69 { M32R_INSN_BGEZ, M32RXF_INSN_BGEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR }, 70 { M32R_INSN_BGTZ, M32RXF_INSN_BGTZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR }, 71 { M32R_INSN_BLEZ, M32RXF_INSN_BLEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR }, 72 { M32R_INSN_BLTZ, M32RXF_INSN_BLTZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR }, 73 { M32R_INSN_BNEZ, M32RXF_INSN_BNEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR }, 74 { M32R_INSN_BL8, M32RXF_INSN_BL8, M32RXF_SFMT_BL8, M32RXF_INSN_PAR_BL8, M32RXF_INSN_WRITE_BL8 }, 75 { M32R_INSN_BL24, M32RXF_INSN_BL24, M32RXF_SFMT_BL24, NOPAR, NOPAR }, 76 { M32R_INSN_BCL8, M32RXF_INSN_BCL8, M32RXF_SFMT_BCL8, M32RXF_INSN_PAR_BCL8, M32RXF_INSN_WRITE_BCL8 }, 77 { M32R_INSN_BCL24, M32RXF_INSN_BCL24, M32RXF_SFMT_BCL24, NOPAR, NOPAR }, 78 { M32R_INSN_BNC8, M32RXF_INSN_BNC8, M32RXF_SFMT_BC8, M32RXF_INSN_PAR_BNC8, M32RXF_INSN_WRITE_BNC8 }, 79 { M32R_INSN_BNC24, M32RXF_INSN_BNC24, M32RXF_SFMT_BC24, NOPAR, NOPAR }, 80 { M32R_INSN_BNE, M32RXF_INSN_BNE, M32RXF_SFMT_BEQ, NOPAR, NOPAR }, 81 { M32R_INSN_BRA8, M32RXF_INSN_BRA8, M32RXF_SFMT_BRA8, M32RXF_INSN_PAR_BRA8, M32RXF_INSN_WRITE_BRA8 }, 82 { M32R_INSN_BRA24, M32RXF_INSN_BRA24, M32RXF_SFMT_BRA24, NOPAR, NOPAR }, 83 { M32R_INSN_BNCL8, M32RXF_INSN_BNCL8, M32RXF_SFMT_BCL8, M32RXF_INSN_PAR_BNCL8, M32RXF_INSN_WRITE_BNCL8 }, 84 { M32R_INSN_BNCL24, M32RXF_INSN_BNCL24, M32RXF_SFMT_BCL24, NOPAR, NOPAR }, 85 { M32R_INSN_CMP, M32RXF_INSN_CMP, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMP, M32RXF_INSN_WRITE_CMP }, 86 { M32R_INSN_CMPI, M32RXF_INSN_CMPI, M32RXF_SFMT_CMPI, NOPAR, NOPAR }, 87 { M32R_INSN_CMPU, M32RXF_INSN_CMPU, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMPU, M32RXF_INSN_WRITE_CMPU }, 88 { M32R_INSN_CMPUI, M32RXF_INSN_CMPUI, M32RXF_SFMT_CMPI, NOPAR, NOPAR }, 89 { M32R_INSN_CMPEQ, M32RXF_INSN_CMPEQ, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMPEQ, M32RXF_INSN_WRITE_CMPEQ }, 90 { M32R_INSN_CMPZ, M32RXF_INSN_CMPZ, M32RXF_SFMT_CMPZ, M32RXF_INSN_PAR_CMPZ, M32RXF_INSN_WRITE_CMPZ }, 91 { M32R_INSN_DIV, M32RXF_INSN_DIV, M32RXF_SFMT_DIV, NOPAR, NOPAR }, 92 { M32R_INSN_DIVU, M32RXF_INSN_DIVU, M32RXF_SFMT_DIV, NOPAR, NOPAR }, 93 { M32R_INSN_REM, M32RXF_INSN_REM, M32RXF_SFMT_DIV, NOPAR, NOPAR }, 94 { M32R_INSN_REMU, M32RXF_INSN_REMU, M32RXF_SFMT_DIV, NOPAR, NOPAR }, 95 { M32R_INSN_DIVH, M32RXF_INSN_DIVH, M32RXF_SFMT_DIV, NOPAR, NOPAR }, 96 { M32R_INSN_JC, M32RXF_INSN_JC, M32RXF_SFMT_JC, M32RXF_INSN_PAR_JC, M32RXF_INSN_WRITE_JC }, 97 { M32R_INSN_JNC, M32RXF_INSN_JNC, M32RXF_SFMT_JC, M32RXF_INSN_PAR_JNC, M32RXF_INSN_WRITE_JNC }, 98 { M32R_INSN_JL, M32RXF_INSN_JL, M32RXF_SFMT_JL, M32RXF_INSN_PAR_JL, M32RXF_INSN_WRITE_JL }, 99 { M32R_INSN_JMP, M32RXF_INSN_JMP, M32RXF_SFMT_JMP, M32RXF_INSN_PAR_JMP, M32RXF_INSN_WRITE_JMP }, 100 { M32R_INSN_LD, M32RXF_INSN_LD, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LD, M32RXF_INSN_WRITE_LD }, 101 { M32R_INSN_LD_D, M32RXF_INSN_LD_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR }, 102 { M32R_INSN_LDB, M32RXF_INSN_LDB, M32RXF_SFMT_LDB, M32RXF_INSN_PAR_LDB, M32RXF_INSN_WRITE_LDB }, 103 { M32R_INSN_LDB_D, M32RXF_INSN_LDB_D, M32RXF_SFMT_LDB_D, NOPAR, NOPAR }, 104 { M32R_INSN_LDH, M32RXF_INSN_LDH, M32RXF_SFMT_LDH, M32RXF_INSN_PAR_LDH, M32RXF_INSN_WRITE_LDH }, 105 { M32R_INSN_LDH_D, M32RXF_INSN_LDH_D, M32RXF_SFMT_LDH_D, NOPAR, NOPAR }, 106 { M32R_INSN_LDUB, M32RXF_INSN_LDUB, M32RXF_SFMT_LDB, M32RXF_INSN_PAR_LDUB, M32RXF_INSN_WRITE_LDUB }, 107 { M32R_INSN_LDUB_D, M32RXF_INSN_LDUB_D, M32RXF_SFMT_LDB_D, NOPAR, NOPAR }, 108 { M32R_INSN_LDUH, M32RXF_INSN_LDUH, M32RXF_SFMT_LDH, M32RXF_INSN_PAR_LDUH, M32RXF_INSN_WRITE_LDUH }, 109 { M32R_INSN_LDUH_D, M32RXF_INSN_LDUH_D, M32RXF_SFMT_LDH_D, NOPAR, NOPAR }, 110 { M32R_INSN_LD_PLUS, M32RXF_INSN_LD_PLUS, M32RXF_SFMT_LD_PLUS, M32RXF_INSN_PAR_LD_PLUS, M32RXF_INSN_WRITE_LD_PLUS }, 111 { M32R_INSN_LD24, M32RXF_INSN_LD24, M32RXF_SFMT_LD24, NOPAR, NOPAR }, 112 { M32R_INSN_LDI8, M32RXF_INSN_LDI8, M32RXF_SFMT_LDI8, M32RXF_INSN_PAR_LDI8, M32RXF_INSN_WRITE_LDI8 }, 113 { M32R_INSN_LDI16, M32RXF_INSN_LDI16, M32RXF_SFMT_LDI16, NOPAR, NOPAR }, 114 { M32R_INSN_LOCK, M32RXF_INSN_LOCK, M32RXF_SFMT_LOCK, M32RXF_INSN_PAR_LOCK, M32RXF_INSN_WRITE_LOCK }, 115 { M32R_INSN_MACHI_A, M32RXF_INSN_MACHI_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACHI_A, M32RXF_INSN_WRITE_MACHI_A }, 116 { M32R_INSN_MACLO_A, M32RXF_INSN_MACLO_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACLO_A, M32RXF_INSN_WRITE_MACLO_A }, 117 { M32R_INSN_MACWHI_A, M32RXF_INSN_MACWHI_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACWHI_A, M32RXF_INSN_WRITE_MACWHI_A }, 118 { M32R_INSN_MACWLO_A, M32RXF_INSN_MACWLO_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACWLO_A, M32RXF_INSN_WRITE_MACWLO_A }, 119 { M32R_INSN_MUL, M32RXF_INSN_MUL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_MUL, M32RXF_INSN_WRITE_MUL }, 120 { M32R_INSN_MULHI_A, M32RXF_INSN_MULHI_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULHI_A, M32RXF_INSN_WRITE_MULHI_A }, 121 { M32R_INSN_MULLO_A, M32RXF_INSN_MULLO_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULLO_A, M32RXF_INSN_WRITE_MULLO_A }, 122 { M32R_INSN_MULWHI_A, M32RXF_INSN_MULWHI_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULWHI_A, M32RXF_INSN_WRITE_MULWHI_A }, 123 { M32R_INSN_MULWLO_A, M32RXF_INSN_MULWLO_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULWLO_A, M32RXF_INSN_WRITE_MULWLO_A }, 124 { M32R_INSN_MV, M32RXF_INSN_MV, M32RXF_SFMT_MV, M32RXF_INSN_PAR_MV, M32RXF_INSN_WRITE_MV }, 125 { M32R_INSN_MVFACHI_A, M32RXF_INSN_MVFACHI_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACHI_A, M32RXF_INSN_WRITE_MVFACHI_A }, 126 { M32R_INSN_MVFACLO_A, M32RXF_INSN_MVFACLO_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACLO_A, M32RXF_INSN_WRITE_MVFACLO_A }, 127 { M32R_INSN_MVFACMI_A, M32RXF_INSN_MVFACMI_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACMI_A, M32RXF_INSN_WRITE_MVFACMI_A }, 128 { M32R_INSN_MVFC, M32RXF_INSN_MVFC, M32RXF_SFMT_MVFC, M32RXF_INSN_PAR_MVFC, M32RXF_INSN_WRITE_MVFC }, 129 { M32R_INSN_MVTACHI_A, M32RXF_INSN_MVTACHI_A, M32RXF_SFMT_MVTACHI_A, M32RXF_INSN_PAR_MVTACHI_A, M32RXF_INSN_WRITE_MVTACHI_A }, 130 { M32R_INSN_MVTACLO_A, M32RXF_INSN_MVTACLO_A, M32RXF_SFMT_MVTACHI_A, M32RXF_INSN_PAR_MVTACLO_A, M32RXF_INSN_WRITE_MVTACLO_A }, 131 { M32R_INSN_MVTC, M32RXF_INSN_MVTC, M32RXF_SFMT_MVTC, M32RXF_INSN_PAR_MVTC, M32RXF_INSN_WRITE_MVTC }, 132 { M32R_INSN_NEG, M32RXF_INSN_NEG, M32RXF_SFMT_MV, M32RXF_INSN_PAR_NEG, M32RXF_INSN_WRITE_NEG }, 133 { M32R_INSN_NOP, M32RXF_INSN_NOP, M32RXF_SFMT_NOP, M32RXF_INSN_PAR_NOP, M32RXF_INSN_WRITE_NOP }, 134 { M32R_INSN_NOT, M32RXF_INSN_NOT, M32RXF_SFMT_MV, M32RXF_INSN_PAR_NOT, M32RXF_INSN_WRITE_NOT }, 135 { M32R_INSN_RAC_DSI, M32RXF_INSN_RAC_DSI, M32RXF_SFMT_RAC_DSI, M32RXF_INSN_PAR_RAC_DSI, M32RXF_INSN_WRITE_RAC_DSI }, 136 { M32R_INSN_RACH_DSI, M32RXF_INSN_RACH_DSI, M32RXF_SFMT_RAC_DSI, M32RXF_INSN_PAR_RACH_DSI, M32RXF_INSN_WRITE_RACH_DSI }, 137 { M32R_INSN_RTE, M32RXF_INSN_RTE, M32RXF_SFMT_RTE, M32RXF_INSN_PAR_RTE, M32RXF_INSN_WRITE_RTE }, 138 { M32R_INSN_SETH, M32RXF_INSN_SETH, M32RXF_SFMT_SETH, NOPAR, NOPAR }, 139 { M32R_INSN_SLL, M32RXF_INSN_SLL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SLL, M32RXF_INSN_WRITE_SLL }, 140 { M32R_INSN_SLL3, M32RXF_INSN_SLL3, M32RXF_SFMT_SLL3, NOPAR, NOPAR }, 141 { M32R_INSN_SLLI, M32RXF_INSN_SLLI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SLLI, M32RXF_INSN_WRITE_SLLI }, 142 { M32R_INSN_SRA, M32RXF_INSN_SRA, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SRA, M32RXF_INSN_WRITE_SRA }, 143 { M32R_INSN_SRA3, M32RXF_INSN_SRA3, M32RXF_SFMT_SLL3, NOPAR, NOPAR }, 144 { M32R_INSN_SRAI, M32RXF_INSN_SRAI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SRAI, M32RXF_INSN_WRITE_SRAI }, 145 { M32R_INSN_SRL, M32RXF_INSN_SRL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SRL, M32RXF_INSN_WRITE_SRL }, 146 { M32R_INSN_SRL3, M32RXF_INSN_SRL3, M32RXF_SFMT_SLL3, NOPAR, NOPAR }, 147 { M32R_INSN_SRLI, M32RXF_INSN_SRLI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SRLI, M32RXF_INSN_WRITE_SRLI }, 148 { M32R_INSN_ST, M32RXF_INSN_ST, M32RXF_SFMT_ST, M32RXF_INSN_PAR_ST, M32RXF_INSN_WRITE_ST }, 149 { M32R_INSN_ST_D, M32RXF_INSN_ST_D, M32RXF_SFMT_ST_D, NOPAR, NOPAR }, 150 { M32R_INSN_STB, M32RXF_INSN_STB, M32RXF_SFMT_STB, M32RXF_INSN_PAR_STB, M32RXF_INSN_WRITE_STB }, 151 { M32R_INSN_STB_D, M32RXF_INSN_STB_D, M32RXF_SFMT_STB_D, NOPAR, NOPAR }, 152 { M32R_INSN_STH, M32RXF_INSN_STH, M32RXF_SFMT_STH, M32RXF_INSN_PAR_STH, M32RXF_INSN_WRITE_STH }, 153 { M32R_INSN_STH_D, M32RXF_INSN_STH_D, M32RXF_SFMT_STH_D, NOPAR, NOPAR }, 154 { M32R_INSN_ST_PLUS, M32RXF_INSN_ST_PLUS, M32RXF_SFMT_ST_PLUS, M32RXF_INSN_PAR_ST_PLUS, M32RXF_INSN_WRITE_ST_PLUS }, 155 { M32R_INSN_STH_PLUS, M32RXF_INSN_STH_PLUS, M32RXF_SFMT_STH_PLUS, M32RXF_INSN_PAR_STH_PLUS, M32RXF_INSN_WRITE_STH_PLUS }, 156 { M32R_INSN_STB_PLUS, M32RXF_INSN_STB_PLUS, M32RXF_SFMT_STB_PLUS, M32RXF_INSN_PAR_STB_PLUS, M32RXF_INSN_WRITE_STB_PLUS }, 157 { M32R_INSN_ST_MINUS, M32RXF_INSN_ST_MINUS, M32RXF_SFMT_ST_PLUS, M32RXF_INSN_PAR_ST_MINUS, M32RXF_INSN_WRITE_ST_MINUS }, 158 { M32R_INSN_SUB, M32RXF_INSN_SUB, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SUB, M32RXF_INSN_WRITE_SUB }, 159 { M32R_INSN_SUBV, M32RXF_INSN_SUBV, M32RXF_SFMT_ADDV, M32RXF_INSN_PAR_SUBV, M32RXF_INSN_WRITE_SUBV }, 160 { M32R_INSN_SUBX, M32RXF_INSN_SUBX, M32RXF_SFMT_ADDX, M32RXF_INSN_PAR_SUBX, M32RXF_INSN_WRITE_SUBX }, 161 { M32R_INSN_TRAP, M32RXF_INSN_TRAP, M32RXF_SFMT_TRAP, M32RXF_INSN_PAR_TRAP, M32RXF_INSN_WRITE_TRAP }, 162 { M32R_INSN_UNLOCK, M32RXF_INSN_UNLOCK, M32RXF_SFMT_UNLOCK, M32RXF_INSN_PAR_UNLOCK, M32RXF_INSN_WRITE_UNLOCK }, 163 { M32R_INSN_SATB, M32RXF_INSN_SATB, M32RXF_SFMT_SATB, NOPAR, NOPAR }, 164 { M32R_INSN_SATH, M32RXF_INSN_SATH, M32RXF_SFMT_SATB, NOPAR, NOPAR }, 165 { M32R_INSN_SAT, M32RXF_INSN_SAT, M32RXF_SFMT_SAT, NOPAR, NOPAR }, 166 { M32R_INSN_PCMPBZ, M32RXF_INSN_PCMPBZ, M32RXF_SFMT_CMPZ, M32RXF_INSN_PAR_PCMPBZ, M32RXF_INSN_WRITE_PCMPBZ }, 167 { M32R_INSN_SADD, M32RXF_INSN_SADD, M32RXF_SFMT_SADD, M32RXF_INSN_PAR_SADD, M32RXF_INSN_WRITE_SADD }, 168 { M32R_INSN_MACWU1, M32RXF_INSN_MACWU1, M32RXF_SFMT_MACWU1, M32RXF_INSN_PAR_MACWU1, M32RXF_INSN_WRITE_MACWU1 }, 169 { M32R_INSN_MSBLO, M32RXF_INSN_MSBLO, M32RXF_SFMT_MSBLO, M32RXF_INSN_PAR_MSBLO, M32RXF_INSN_WRITE_MSBLO }, 170 { M32R_INSN_MULWU1, M32RXF_INSN_MULWU1, M32RXF_SFMT_MULWU1, M32RXF_INSN_PAR_MULWU1, M32RXF_INSN_WRITE_MULWU1 }, 171 { M32R_INSN_MACLH1, M32RXF_INSN_MACLH1, M32RXF_SFMT_MACWU1, M32RXF_INSN_PAR_MACLH1, M32RXF_INSN_WRITE_MACLH1 }, 172 { M32R_INSN_SC, M32RXF_INSN_SC, M32RXF_SFMT_SC, M32RXF_INSN_PAR_SC, M32RXF_INSN_WRITE_SC }, 173 { M32R_INSN_SNC, M32RXF_INSN_SNC, M32RXF_SFMT_SC, M32RXF_INSN_PAR_SNC, M32RXF_INSN_WRITE_SNC }, 174 { M32R_INSN_CLRPSW, M32RXF_INSN_CLRPSW, M32RXF_SFMT_CLRPSW, M32RXF_INSN_PAR_CLRPSW, M32RXF_INSN_WRITE_CLRPSW }, 175 { M32R_INSN_SETPSW, M32RXF_INSN_SETPSW, M32RXF_SFMT_SETPSW, M32RXF_INSN_PAR_SETPSW, M32RXF_INSN_WRITE_SETPSW }, 176 { M32R_INSN_BSET, M32RXF_INSN_BSET, M32RXF_SFMT_BSET, NOPAR, NOPAR }, 177 { M32R_INSN_BCLR, M32RXF_INSN_BCLR, M32RXF_SFMT_BSET, NOPAR, NOPAR }, 178 { M32R_INSN_BTST, M32RXF_INSN_BTST, M32RXF_SFMT_BTST, M32RXF_INSN_PAR_BTST, M32RXF_INSN_WRITE_BTST }, 179 }; 180 181 static const struct insn_sem m32rxf_insn_sem_invalid = 182 { 183 VIRTUAL_INSN_X_INVALID, M32RXF_INSN_X_INVALID, M32RXF_SFMT_EMPTY, NOPAR, NOPAR 184 }; 185 186 /* Initialize an IDESC from the compile-time computable parts. */ 187 188 static INLINE void 189 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) 190 { 191 const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries; 192 193 id->num = t->index; 194 id->sfmt = t->sfmt; 195 if ((int) t->type <= 0) 196 id->idata = & cgen_virtual_insn_table[- (int) t->type]; 197 else 198 id->idata = & insn_table[t->type]; 199 id->attrs = CGEN_INSN_ATTRS (id->idata); 200 /* Oh my god, a magic number. */ 201 id->length = CGEN_INSN_BITSIZE (id->idata) / 8; 202 203 #if WITH_PROFILE_MODEL_P 204 id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index]; 205 { 206 SIM_DESC sd = CPU_STATE (cpu); 207 SIM_ASSERT (t->index == id->timing->num); 208 } 209 #endif 210 211 /* Semantic pointers are initialized elsewhere. */ 212 } 213 214 /* Initialize the instruction descriptor table. */ 215 216 void 217 m32rxf_init_idesc_table (SIM_CPU *cpu) 218 { 219 IDESC *id,*tabend; 220 const struct insn_sem *t,*tend; 221 int tabsize = M32RXF_INSN__MAX; 222 IDESC *table = m32rxf_insn_data; 223 224 memset (table, 0, tabsize * sizeof (IDESC)); 225 226 /* First set all entries to the `invalid insn'. */ 227 t = & m32rxf_insn_sem_invalid; 228 for (id = table, tabend = table + tabsize; id < tabend; ++id) 229 init_idesc (cpu, id, t); 230 231 /* Now fill in the values for the chosen cpu. */ 232 for (t = m32rxf_insn_sem, tend = t + sizeof (m32rxf_insn_sem) / sizeof (*t); 233 t != tend; ++t) 234 { 235 init_idesc (cpu, & table[t->index], t); 236 if (t->par_index != NOPAR) 237 { 238 init_idesc (cpu, &table[t->par_index], t); 239 table[t->index].par_idesc = &table[t->par_index]; 240 } 241 if (t->par_index != NOPAR) 242 { 243 init_idesc (cpu, &table[t->write_index], t); 244 table[t->par_index].par_idesc = &table[t->write_index]; 245 } 246 } 247 248 /* Link the IDESC table into the cpu. */ 249 CPU_IDESC (cpu) = table; 250 } 251 252 /* Given an instruction, return a pointer to its IDESC entry. */ 253 254 const IDESC * 255 m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, 256 CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn, 257 ARGBUF *abuf) 258 { 259 /* Result of decoder. */ 260 M32RXF_INSN_TYPE itype; 261 262 { 263 CGEN_INSN_WORD insn = base_insn; 264 265 { 266 unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0))); 267 switch (val) 268 { 269 case 0 : itype = M32RXF_INSN_SUBV; goto extract_sfmt_addv; 270 case 1 : itype = M32RXF_INSN_SUBX; goto extract_sfmt_addx; 271 case 2 : itype = M32RXF_INSN_SUB; goto extract_sfmt_add; 272 case 3 : itype = M32RXF_INSN_NEG; goto extract_sfmt_mv; 273 case 4 : itype = M32RXF_INSN_CMP; goto extract_sfmt_cmp; 274 case 5 : itype = M32RXF_INSN_CMPU; goto extract_sfmt_cmp; 275 case 6 : itype = M32RXF_INSN_CMPEQ; goto extract_sfmt_cmp; 276 case 7 : 277 { 278 unsigned int val = (((insn >> 8) & (3 << 0))); 279 switch (val) 280 { 281 case 0 : 282 if ((entire_insn & 0xfff0) == 0x70) 283 { itype = M32RXF_INSN_CMPZ; goto extract_sfmt_cmpz; } 284 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 285 case 3 : 286 if ((entire_insn & 0xfff0) == 0x370) 287 { itype = M32RXF_INSN_PCMPBZ; goto extract_sfmt_cmpz; } 288 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 289 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 290 } 291 } 292 case 8 : itype = M32RXF_INSN_ADDV; goto extract_sfmt_addv; 293 case 9 : itype = M32RXF_INSN_ADDX; goto extract_sfmt_addx; 294 case 10 : itype = M32RXF_INSN_ADD; goto extract_sfmt_add; 295 case 11 : itype = M32RXF_INSN_NOT; goto extract_sfmt_mv; 296 case 12 : itype = M32RXF_INSN_AND; goto extract_sfmt_add; 297 case 13 : itype = M32RXF_INSN_XOR; goto extract_sfmt_add; 298 case 14 : itype = M32RXF_INSN_OR; goto extract_sfmt_add; 299 case 15 : 300 if ((entire_insn & 0xf8f0) == 0xf0) 301 { itype = M32RXF_INSN_BTST; goto extract_sfmt_btst; } 302 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 303 case 16 : itype = M32RXF_INSN_SRL; goto extract_sfmt_add; 304 case 18 : itype = M32RXF_INSN_SRA; goto extract_sfmt_add; 305 case 20 : itype = M32RXF_INSN_SLL; goto extract_sfmt_add; 306 case 22 : itype = M32RXF_INSN_MUL; goto extract_sfmt_add; 307 case 24 : itype = M32RXF_INSN_MV; goto extract_sfmt_mv; 308 case 25 : itype = M32RXF_INSN_MVFC; goto extract_sfmt_mvfc; 309 case 26 : itype = M32RXF_INSN_MVTC; goto extract_sfmt_mvtc; 310 case 28 : 311 { 312 unsigned int val = (((insn >> 8) & (3 << 0))); 313 switch (val) 314 { 315 case 0 : 316 if ((entire_insn & 0xfff0) == 0x1cc0) 317 { itype = M32RXF_INSN_JC; goto extract_sfmt_jc; } 318 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 319 case 1 : 320 if ((entire_insn & 0xfff0) == 0x1dc0) 321 { itype = M32RXF_INSN_JNC; goto extract_sfmt_jc; } 322 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 323 case 2 : 324 if ((entire_insn & 0xfff0) == 0x1ec0) 325 { itype = M32RXF_INSN_JL; goto extract_sfmt_jl; } 326 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 327 case 3 : 328 if ((entire_insn & 0xfff0) == 0x1fc0) 329 { itype = M32RXF_INSN_JMP; goto extract_sfmt_jmp; } 330 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 331 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 332 } 333 } 334 case 29 : 335 if ((entire_insn & 0xffff) == 0x10d6) 336 { itype = M32RXF_INSN_RTE; goto extract_sfmt_rte; } 337 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 338 case 31 : 339 if ((entire_insn & 0xfff0) == 0x10f0) 340 { itype = M32RXF_INSN_TRAP; goto extract_sfmt_trap; } 341 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 342 case 32 : itype = M32RXF_INSN_STB; goto extract_sfmt_stb; 343 case 33 : itype = M32RXF_INSN_STB_PLUS; goto extract_sfmt_stb_plus; 344 case 34 : itype = M32RXF_INSN_STH; goto extract_sfmt_sth; 345 case 35 : itype = M32RXF_INSN_STH_PLUS; goto extract_sfmt_sth_plus; 346 case 36 : itype = M32RXF_INSN_ST; goto extract_sfmt_st; 347 case 37 : itype = M32RXF_INSN_UNLOCK; goto extract_sfmt_unlock; 348 case 38 : itype = M32RXF_INSN_ST_PLUS; goto extract_sfmt_st_plus; 349 case 39 : itype = M32RXF_INSN_ST_MINUS; goto extract_sfmt_st_plus; 350 case 40 : itype = M32RXF_INSN_LDB; goto extract_sfmt_ldb; 351 case 41 : itype = M32RXF_INSN_LDUB; goto extract_sfmt_ldb; 352 case 42 : itype = M32RXF_INSN_LDH; goto extract_sfmt_ldh; 353 case 43 : itype = M32RXF_INSN_LDUH; goto extract_sfmt_ldh; 354 case 44 : itype = M32RXF_INSN_LD; goto extract_sfmt_ld; 355 case 45 : itype = M32RXF_INSN_LOCK; goto extract_sfmt_lock; 356 case 46 : itype = M32RXF_INSN_LD_PLUS; goto extract_sfmt_ld_plus; 357 case 48 : /* fall through */ 358 case 56 : itype = M32RXF_INSN_MULHI_A; goto extract_sfmt_mulhi_a; 359 case 49 : /* fall through */ 360 case 57 : itype = M32RXF_INSN_MULLO_A; goto extract_sfmt_mulhi_a; 361 case 50 : /* fall through */ 362 case 58 : itype = M32RXF_INSN_MULWHI_A; goto extract_sfmt_mulhi_a; 363 case 51 : /* fall through */ 364 case 59 : itype = M32RXF_INSN_MULWLO_A; goto extract_sfmt_mulhi_a; 365 case 52 : /* fall through */ 366 case 60 : itype = M32RXF_INSN_MACHI_A; goto extract_sfmt_machi_a; 367 case 53 : /* fall through */ 368 case 61 : itype = M32RXF_INSN_MACLO_A; goto extract_sfmt_machi_a; 369 case 54 : /* fall through */ 370 case 62 : itype = M32RXF_INSN_MACWHI_A; goto extract_sfmt_machi_a; 371 case 55 : /* fall through */ 372 case 63 : itype = M32RXF_INSN_MACWLO_A; goto extract_sfmt_machi_a; 373 case 64 : /* fall through */ 374 case 65 : /* fall through */ 375 case 66 : /* fall through */ 376 case 67 : /* fall through */ 377 case 68 : /* fall through */ 378 case 69 : /* fall through */ 379 case 70 : /* fall through */ 380 case 71 : /* fall through */ 381 case 72 : /* fall through */ 382 case 73 : /* fall through */ 383 case 74 : /* fall through */ 384 case 75 : /* fall through */ 385 case 76 : /* fall through */ 386 case 77 : /* fall through */ 387 case 78 : /* fall through */ 388 case 79 : itype = M32RXF_INSN_ADDI; goto extract_sfmt_addi; 389 case 80 : /* fall through */ 390 case 81 : itype = M32RXF_INSN_SRLI; goto extract_sfmt_slli; 391 case 82 : /* fall through */ 392 case 83 : itype = M32RXF_INSN_SRAI; goto extract_sfmt_slli; 393 case 84 : /* fall through */ 394 case 85 : itype = M32RXF_INSN_SLLI; goto extract_sfmt_slli; 395 case 87 : 396 { 397 unsigned int val = (((insn >> 0) & (1 << 0))); 398 switch (val) 399 { 400 case 0 : 401 if ((entire_insn & 0xf0f3) == 0x5070) 402 { itype = M32RXF_INSN_MVTACHI_A; goto extract_sfmt_mvtachi_a; } 403 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 404 case 1 : 405 if ((entire_insn & 0xf0f3) == 0x5071) 406 { itype = M32RXF_INSN_MVTACLO_A; goto extract_sfmt_mvtachi_a; } 407 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 408 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 409 } 410 } 411 case 88 : 412 if ((entire_insn & 0xf3f2) == 0x5080) 413 { itype = M32RXF_INSN_RACH_DSI; goto extract_sfmt_rac_dsi; } 414 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 415 case 89 : 416 if ((entire_insn & 0xf3f2) == 0x5090) 417 { itype = M32RXF_INSN_RAC_DSI; goto extract_sfmt_rac_dsi; } 418 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 419 case 90 : itype = M32RXF_INSN_MULWU1; goto extract_sfmt_mulwu1; 420 case 91 : itype = M32RXF_INSN_MACWU1; goto extract_sfmt_macwu1; 421 case 92 : itype = M32RXF_INSN_MACLH1; goto extract_sfmt_macwu1; 422 case 93 : itype = M32RXF_INSN_MSBLO; goto extract_sfmt_msblo; 423 case 94 : 424 if ((entire_insn & 0xffff) == 0x50e4) 425 { itype = M32RXF_INSN_SADD; goto extract_sfmt_sadd; } 426 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 427 case 95 : 428 { 429 unsigned int val = (((insn >> 0) & (3 << 0))); 430 switch (val) 431 { 432 case 0 : itype = M32RXF_INSN_MVFACHI_A; goto extract_sfmt_mvfachi_a; 433 case 1 : itype = M32RXF_INSN_MVFACLO_A; goto extract_sfmt_mvfachi_a; 434 case 2 : itype = M32RXF_INSN_MVFACMI_A; goto extract_sfmt_mvfachi_a; 435 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 436 } 437 } 438 case 96 : /* fall through */ 439 case 97 : /* fall through */ 440 case 98 : /* fall through */ 441 case 99 : /* fall through */ 442 case 100 : /* fall through */ 443 case 101 : /* fall through */ 444 case 102 : /* fall through */ 445 case 103 : /* fall through */ 446 case 104 : /* fall through */ 447 case 105 : /* fall through */ 448 case 106 : /* fall through */ 449 case 107 : /* fall through */ 450 case 108 : /* fall through */ 451 case 109 : /* fall through */ 452 case 110 : /* fall through */ 453 case 111 : itype = M32RXF_INSN_LDI8; goto extract_sfmt_ldi8; 454 case 112 : 455 { 456 unsigned int val = (((insn >> 7) & (15 << 1)) | ((insn >> 0) & (1 << 0))); 457 switch (val) 458 { 459 case 0 : 460 if ((entire_insn & 0xffff) == 0x7000) 461 { itype = M32RXF_INSN_NOP; goto extract_sfmt_nop; } 462 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 463 case 2 : /* fall through */ 464 case 3 : itype = M32RXF_INSN_SETPSW; goto extract_sfmt_setpsw; 465 case 4 : /* fall through */ 466 case 5 : itype = M32RXF_INSN_CLRPSW; goto extract_sfmt_clrpsw; 467 case 9 : 468 if ((entire_insn & 0xffff) == 0x7401) 469 { itype = M32RXF_INSN_SC; goto extract_sfmt_sc; } 470 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 471 case 11 : 472 if ((entire_insn & 0xffff) == 0x7501) 473 { itype = M32RXF_INSN_SNC; goto extract_sfmt_sc; } 474 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 475 case 16 : /* fall through */ 476 case 17 : itype = M32RXF_INSN_BCL8; goto extract_sfmt_bcl8; 477 case 18 : /* fall through */ 478 case 19 : itype = M32RXF_INSN_BNCL8; goto extract_sfmt_bcl8; 479 case 24 : /* fall through */ 480 case 25 : itype = M32RXF_INSN_BC8; goto extract_sfmt_bc8; 481 case 26 : /* fall through */ 482 case 27 : itype = M32RXF_INSN_BNC8; goto extract_sfmt_bc8; 483 case 28 : /* fall through */ 484 case 29 : itype = M32RXF_INSN_BL8; goto extract_sfmt_bl8; 485 case 30 : /* fall through */ 486 case 31 : itype = M32RXF_INSN_BRA8; goto extract_sfmt_bra8; 487 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 488 } 489 } 490 case 113 : /* fall through */ 491 case 114 : /* fall through */ 492 case 115 : /* fall through */ 493 case 116 : /* fall through */ 494 case 117 : /* fall through */ 495 case 118 : /* fall through */ 496 case 119 : /* fall through */ 497 case 120 : /* fall through */ 498 case 121 : /* fall through */ 499 case 122 : /* fall through */ 500 case 123 : /* fall through */ 501 case 124 : /* fall through */ 502 case 125 : /* fall through */ 503 case 126 : /* fall through */ 504 case 127 : 505 { 506 unsigned int val = (((insn >> 8) & (15 << 0))); 507 switch (val) 508 { 509 case 1 : itype = M32RXF_INSN_SETPSW; goto extract_sfmt_setpsw; 510 case 2 : itype = M32RXF_INSN_CLRPSW; goto extract_sfmt_clrpsw; 511 case 8 : itype = M32RXF_INSN_BCL8; goto extract_sfmt_bcl8; 512 case 9 : itype = M32RXF_INSN_BNCL8; goto extract_sfmt_bcl8; 513 case 12 : itype = M32RXF_INSN_BC8; goto extract_sfmt_bc8; 514 case 13 : itype = M32RXF_INSN_BNC8; goto extract_sfmt_bc8; 515 case 14 : itype = M32RXF_INSN_BL8; goto extract_sfmt_bl8; 516 case 15 : itype = M32RXF_INSN_BRA8; goto extract_sfmt_bra8; 517 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 518 } 519 } 520 case 132 : 521 if ((entire_insn & 0xfff00000) == 0x80400000) 522 { itype = M32RXF_INSN_CMPI; goto extract_sfmt_cmpi; } 523 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 524 case 133 : 525 if ((entire_insn & 0xfff00000) == 0x80500000) 526 { itype = M32RXF_INSN_CMPUI; goto extract_sfmt_cmpi; } 527 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 528 case 134 : 529 { 530 unsigned int val = (((entire_insn >> 8) & (3 << 0))); 531 switch (val) 532 { 533 case 0 : 534 if ((entire_insn & 0xf0f0ffff) == 0x80600000) 535 { itype = M32RXF_INSN_SAT; goto extract_sfmt_sat; } 536 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 537 case 2 : 538 if ((entire_insn & 0xf0f0ffff) == 0x80600200) 539 { itype = M32RXF_INSN_SATH; goto extract_sfmt_satb; } 540 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 541 case 3 : 542 if ((entire_insn & 0xf0f0ffff) == 0x80600300) 543 { itype = M32RXF_INSN_SATB; goto extract_sfmt_satb; } 544 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 545 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 546 } 547 } 548 case 136 : itype = M32RXF_INSN_ADDV3; goto extract_sfmt_addv3; 549 case 138 : itype = M32RXF_INSN_ADD3; goto extract_sfmt_add3; 550 case 140 : itype = M32RXF_INSN_AND3; goto extract_sfmt_and3; 551 case 141 : itype = M32RXF_INSN_XOR3; goto extract_sfmt_and3; 552 case 142 : itype = M32RXF_INSN_OR3; goto extract_sfmt_or3; 553 case 144 : 554 { 555 unsigned int val = (((entire_insn >> 4) & (1 << 0))); 556 switch (val) 557 { 558 case 0 : 559 if ((entire_insn & 0xf0f0ffff) == 0x90000000) 560 { itype = M32RXF_INSN_DIV; goto extract_sfmt_div; } 561 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 562 case 1 : 563 if ((entire_insn & 0xf0f0ffff) == 0x90000010) 564 { itype = M32RXF_INSN_DIVH; goto extract_sfmt_div; } 565 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 566 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 567 } 568 } 569 case 145 : 570 if ((entire_insn & 0xf0f0ffff) == 0x90100000) 571 { itype = M32RXF_INSN_DIVU; goto extract_sfmt_div; } 572 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 573 case 146 : 574 if ((entire_insn & 0xf0f0ffff) == 0x90200000) 575 { itype = M32RXF_INSN_REM; goto extract_sfmt_div; } 576 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 577 case 147 : 578 if ((entire_insn & 0xf0f0ffff) == 0x90300000) 579 { itype = M32RXF_INSN_REMU; goto extract_sfmt_div; } 580 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 581 case 152 : itype = M32RXF_INSN_SRL3; goto extract_sfmt_sll3; 582 case 154 : itype = M32RXF_INSN_SRA3; goto extract_sfmt_sll3; 583 case 156 : itype = M32RXF_INSN_SLL3; goto extract_sfmt_sll3; 584 case 159 : 585 if ((entire_insn & 0xf0ff0000) == 0x90f00000) 586 { itype = M32RXF_INSN_LDI16; goto extract_sfmt_ldi16; } 587 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 588 case 160 : itype = M32RXF_INSN_STB_D; goto extract_sfmt_stb_d; 589 case 162 : itype = M32RXF_INSN_STH_D; goto extract_sfmt_sth_d; 590 case 164 : itype = M32RXF_INSN_ST_D; goto extract_sfmt_st_d; 591 case 166 : 592 if ((entire_insn & 0xf8f00000) == 0xa0600000) 593 { itype = M32RXF_INSN_BSET; goto extract_sfmt_bset; } 594 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 595 case 167 : 596 if ((entire_insn & 0xf8f00000) == 0xa0700000) 597 { itype = M32RXF_INSN_BCLR; goto extract_sfmt_bset; } 598 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 599 case 168 : itype = M32RXF_INSN_LDB_D; goto extract_sfmt_ldb_d; 600 case 169 : itype = M32RXF_INSN_LDUB_D; goto extract_sfmt_ldb_d; 601 case 170 : itype = M32RXF_INSN_LDH_D; goto extract_sfmt_ldh_d; 602 case 171 : itype = M32RXF_INSN_LDUH_D; goto extract_sfmt_ldh_d; 603 case 172 : itype = M32RXF_INSN_LD_D; goto extract_sfmt_ld_d; 604 case 176 : itype = M32RXF_INSN_BEQ; goto extract_sfmt_beq; 605 case 177 : itype = M32RXF_INSN_BNE; goto extract_sfmt_beq; 606 case 184 : 607 if ((entire_insn & 0xfff00000) == 0xb0800000) 608 { itype = M32RXF_INSN_BEQZ; goto extract_sfmt_beqz; } 609 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 610 case 185 : 611 if ((entire_insn & 0xfff00000) == 0xb0900000) 612 { itype = M32RXF_INSN_BNEZ; goto extract_sfmt_beqz; } 613 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 614 case 186 : 615 if ((entire_insn & 0xfff00000) == 0xb0a00000) 616 { itype = M32RXF_INSN_BLTZ; goto extract_sfmt_beqz; } 617 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 618 case 187 : 619 if ((entire_insn & 0xfff00000) == 0xb0b00000) 620 { itype = M32RXF_INSN_BGEZ; goto extract_sfmt_beqz; } 621 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 622 case 188 : 623 if ((entire_insn & 0xfff00000) == 0xb0c00000) 624 { itype = M32RXF_INSN_BLEZ; goto extract_sfmt_beqz; } 625 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 626 case 189 : 627 if ((entire_insn & 0xfff00000) == 0xb0d00000) 628 { itype = M32RXF_INSN_BGTZ; goto extract_sfmt_beqz; } 629 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 630 case 220 : 631 if ((entire_insn & 0xf0ff0000) == 0xd0c00000) 632 { itype = M32RXF_INSN_SETH; goto extract_sfmt_seth; } 633 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 634 case 224 : /* fall through */ 635 case 225 : /* fall through */ 636 case 226 : /* fall through */ 637 case 227 : /* fall through */ 638 case 228 : /* fall through */ 639 case 229 : /* fall through */ 640 case 230 : /* fall through */ 641 case 231 : /* fall through */ 642 case 232 : /* fall through */ 643 case 233 : /* fall through */ 644 case 234 : /* fall through */ 645 case 235 : /* fall through */ 646 case 236 : /* fall through */ 647 case 237 : /* fall through */ 648 case 238 : /* fall through */ 649 case 239 : itype = M32RXF_INSN_LD24; goto extract_sfmt_ld24; 650 case 240 : /* fall through */ 651 case 241 : /* fall through */ 652 case 242 : /* fall through */ 653 case 243 : /* fall through */ 654 case 244 : /* fall through */ 655 case 245 : /* fall through */ 656 case 246 : /* fall through */ 657 case 247 : /* fall through */ 658 case 248 : /* fall through */ 659 case 249 : /* fall through */ 660 case 250 : /* fall through */ 661 case 251 : /* fall through */ 662 case 252 : /* fall through */ 663 case 253 : /* fall through */ 664 case 254 : /* fall through */ 665 case 255 : 666 { 667 unsigned int val = (((insn >> 8) & (7 << 0))); 668 switch (val) 669 { 670 case 0 : 671 if ((entire_insn & 0xff000000) == 0xf8000000) 672 { itype = M32RXF_INSN_BCL24; goto extract_sfmt_bcl24; } 673 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 674 case 1 : 675 if ((entire_insn & 0xff000000) == 0xf9000000) 676 { itype = M32RXF_INSN_BNCL24; goto extract_sfmt_bcl24; } 677 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 678 case 4 : 679 if ((entire_insn & 0xff000000) == 0xfc000000) 680 { itype = M32RXF_INSN_BC24; goto extract_sfmt_bc24; } 681 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 682 case 5 : 683 if ((entire_insn & 0xff000000) == 0xfd000000) 684 { itype = M32RXF_INSN_BNC24; goto extract_sfmt_bc24; } 685 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 686 case 6 : 687 if ((entire_insn & 0xff000000) == 0xfe000000) 688 { itype = M32RXF_INSN_BL24; goto extract_sfmt_bl24; } 689 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 690 case 7 : 691 if ((entire_insn & 0xff000000) == 0xff000000) 692 { itype = M32RXF_INSN_BRA24; goto extract_sfmt_bra24; } 693 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 694 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 695 } 696 } 697 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 698 } 699 } 700 } 701 702 /* The instruction has been decoded, now extract the fields. */ 703 704 extract_sfmt_empty: 705 { 706 const IDESC *idesc = &m32rxf_insn_data[itype]; 707 #define FLD(f) abuf->fields.sfmt_empty.f 708 709 710 /* Record the fields for the semantic handler. */ 711 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0)); 712 713 #undef FLD 714 return idesc; 715 } 716 717 extract_sfmt_add: 718 { 719 const IDESC *idesc = &m32rxf_insn_data[itype]; 720 CGEN_INSN_WORD insn = entire_insn; 721 #define FLD(f) abuf->fields.sfmt_add.f 722 UINT f_r1; 723 UINT f_r2; 724 725 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 726 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 727 728 /* Record the fields for the semantic handler. */ 729 FLD (f_r1) = f_r1; 730 FLD (f_r2) = f_r2; 731 FLD (i_dr) = & CPU (h_gr)[f_r1]; 732 FLD (i_sr) = & CPU (h_gr)[f_r2]; 733 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); 734 735 #if WITH_PROFILE_MODEL_P 736 /* Record the fields for profiling. */ 737 if (PROFILE_MODEL_P (current_cpu)) 738 { 739 FLD (in_dr) = f_r1; 740 FLD (in_sr) = f_r2; 741 FLD (out_dr) = f_r1; 742 } 743 #endif 744 #undef FLD 745 return idesc; 746 } 747 748 extract_sfmt_add3: 749 { 750 const IDESC *idesc = &m32rxf_insn_data[itype]; 751 CGEN_INSN_WORD insn = entire_insn; 752 #define FLD(f) abuf->fields.sfmt_add3.f 753 UINT f_r1; 754 UINT f_r2; 755 INT f_simm16; 756 757 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 758 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 759 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 760 761 /* Record the fields for the semantic handler. */ 762 FLD (f_simm16) = f_simm16; 763 FLD (f_r2) = f_r2; 764 FLD (f_r1) = f_r1; 765 FLD (i_sr) = & CPU (h_gr)[f_r2]; 766 FLD (i_dr) = & CPU (h_gr)[f_r1]; 767 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 768 769 #if WITH_PROFILE_MODEL_P 770 /* Record the fields for profiling. */ 771 if (PROFILE_MODEL_P (current_cpu)) 772 { 773 FLD (in_sr) = f_r2; 774 FLD (out_dr) = f_r1; 775 } 776 #endif 777 #undef FLD 778 return idesc; 779 } 780 781 extract_sfmt_and3: 782 { 783 const IDESC *idesc = &m32rxf_insn_data[itype]; 784 CGEN_INSN_WORD insn = entire_insn; 785 #define FLD(f) abuf->fields.sfmt_and3.f 786 UINT f_r1; 787 UINT f_r2; 788 UINT f_uimm16; 789 790 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 791 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 792 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); 793 794 /* Record the fields for the semantic handler. */ 795 FLD (f_r2) = f_r2; 796 FLD (f_uimm16) = f_uimm16; 797 FLD (f_r1) = f_r1; 798 FLD (i_sr) = & CPU (h_gr)[f_r2]; 799 FLD (i_dr) = & CPU (h_gr)[f_r1]; 800 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 801 802 #if WITH_PROFILE_MODEL_P 803 /* Record the fields for profiling. */ 804 if (PROFILE_MODEL_P (current_cpu)) 805 { 806 FLD (in_sr) = f_r2; 807 FLD (out_dr) = f_r1; 808 } 809 #endif 810 #undef FLD 811 return idesc; 812 } 813 814 extract_sfmt_or3: 815 { 816 const IDESC *idesc = &m32rxf_insn_data[itype]; 817 CGEN_INSN_WORD insn = entire_insn; 818 #define FLD(f) abuf->fields.sfmt_and3.f 819 UINT f_r1; 820 UINT f_r2; 821 UINT f_uimm16; 822 823 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 824 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 825 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); 826 827 /* Record the fields for the semantic handler. */ 828 FLD (f_r2) = f_r2; 829 FLD (f_uimm16) = f_uimm16; 830 FLD (f_r1) = f_r1; 831 FLD (i_sr) = & CPU (h_gr)[f_r2]; 832 FLD (i_dr) = & CPU (h_gr)[f_r1]; 833 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_or3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 834 835 #if WITH_PROFILE_MODEL_P 836 /* Record the fields for profiling. */ 837 if (PROFILE_MODEL_P (current_cpu)) 838 { 839 FLD (in_sr) = f_r2; 840 FLD (out_dr) = f_r1; 841 } 842 #endif 843 #undef FLD 844 return idesc; 845 } 846 847 extract_sfmt_addi: 848 { 849 const IDESC *idesc = &m32rxf_insn_data[itype]; 850 CGEN_INSN_WORD insn = entire_insn; 851 #define FLD(f) abuf->fields.sfmt_addi.f 852 UINT f_r1; 853 INT f_simm8; 854 855 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 856 f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8); 857 858 /* Record the fields for the semantic handler. */ 859 FLD (f_r1) = f_r1; 860 FLD (f_simm8) = f_simm8; 861 FLD (i_dr) = & CPU (h_gr)[f_r1]; 862 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_r1 0x%x", 'x', f_r1, "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0)); 863 864 #if WITH_PROFILE_MODEL_P 865 /* Record the fields for profiling. */ 866 if (PROFILE_MODEL_P (current_cpu)) 867 { 868 FLD (in_dr) = f_r1; 869 FLD (out_dr) = f_r1; 870 } 871 #endif 872 #undef FLD 873 return idesc; 874 } 875 876 extract_sfmt_addv: 877 { 878 const IDESC *idesc = &m32rxf_insn_data[itype]; 879 CGEN_INSN_WORD insn = entire_insn; 880 #define FLD(f) abuf->fields.sfmt_add.f 881 UINT f_r1; 882 UINT f_r2; 883 884 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 885 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 886 887 /* Record the fields for the semantic handler. */ 888 FLD (f_r1) = f_r1; 889 FLD (f_r2) = f_r2; 890 FLD (i_dr) = & CPU (h_gr)[f_r1]; 891 FLD (i_sr) = & CPU (h_gr)[f_r2]; 892 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); 893 894 #if WITH_PROFILE_MODEL_P 895 /* Record the fields for profiling. */ 896 if (PROFILE_MODEL_P (current_cpu)) 897 { 898 FLD (in_dr) = f_r1; 899 FLD (in_sr) = f_r2; 900 FLD (out_dr) = f_r1; 901 } 902 #endif 903 #undef FLD 904 return idesc; 905 } 906 907 extract_sfmt_addv3: 908 { 909 const IDESC *idesc = &m32rxf_insn_data[itype]; 910 CGEN_INSN_WORD insn = entire_insn; 911 #define FLD(f) abuf->fields.sfmt_add3.f 912 UINT f_r1; 913 UINT f_r2; 914 INT f_simm16; 915 916 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 917 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 918 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 919 920 /* Record the fields for the semantic handler. */ 921 FLD (f_simm16) = f_simm16; 922 FLD (f_r2) = f_r2; 923 FLD (f_r1) = f_r1; 924 FLD (i_sr) = & CPU (h_gr)[f_r2]; 925 FLD (i_dr) = & CPU (h_gr)[f_r1]; 926 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 927 928 #if WITH_PROFILE_MODEL_P 929 /* Record the fields for profiling. */ 930 if (PROFILE_MODEL_P (current_cpu)) 931 { 932 FLD (in_sr) = f_r2; 933 FLD (out_dr) = f_r1; 934 } 935 #endif 936 #undef FLD 937 return idesc; 938 } 939 940 extract_sfmt_addx: 941 { 942 const IDESC *idesc = &m32rxf_insn_data[itype]; 943 CGEN_INSN_WORD insn = entire_insn; 944 #define FLD(f) abuf->fields.sfmt_add.f 945 UINT f_r1; 946 UINT f_r2; 947 948 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 949 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 950 951 /* Record the fields for the semantic handler. */ 952 FLD (f_r1) = f_r1; 953 FLD (f_r2) = f_r2; 954 FLD (i_dr) = & CPU (h_gr)[f_r1]; 955 FLD (i_sr) = & CPU (h_gr)[f_r2]; 956 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); 957 958 #if WITH_PROFILE_MODEL_P 959 /* Record the fields for profiling. */ 960 if (PROFILE_MODEL_P (current_cpu)) 961 { 962 FLD (in_dr) = f_r1; 963 FLD (in_sr) = f_r2; 964 FLD (out_dr) = f_r1; 965 } 966 #endif 967 #undef FLD 968 return idesc; 969 } 970 971 extract_sfmt_bc8: 972 { 973 const IDESC *idesc = &m32rxf_insn_data[itype]; 974 CGEN_INSN_WORD insn = entire_insn; 975 #define FLD(f) abuf->fields.sfmt_bl8.f 976 SI f_disp8; 977 978 f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); 979 980 /* Record the fields for the semantic handler. */ 981 FLD (i_disp8) = f_disp8; 982 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); 983 984 #if WITH_PROFILE_MODEL_P 985 /* Record the fields for profiling. */ 986 if (PROFILE_MODEL_P (current_cpu)) 987 { 988 } 989 #endif 990 #undef FLD 991 return idesc; 992 } 993 994 extract_sfmt_bc24: 995 { 996 const IDESC *idesc = &m32rxf_insn_data[itype]; 997 CGEN_INSN_WORD insn = entire_insn; 998 #define FLD(f) abuf->fields.sfmt_bl24.f 999 SI f_disp24; 1000 1001 f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); 1002 1003 /* Record the fields for the semantic handler. */ 1004 FLD (i_disp24) = f_disp24; 1005 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); 1006 1007 #if WITH_PROFILE_MODEL_P 1008 /* Record the fields for profiling. */ 1009 if (PROFILE_MODEL_P (current_cpu)) 1010 { 1011 } 1012 #endif 1013 #undef FLD 1014 return idesc; 1015 } 1016 1017 extract_sfmt_beq: 1018 { 1019 const IDESC *idesc = &m32rxf_insn_data[itype]; 1020 CGEN_INSN_WORD insn = entire_insn; 1021 #define FLD(f) abuf->fields.sfmt_beq.f 1022 UINT f_r1; 1023 UINT f_r2; 1024 SI f_disp16; 1025 1026 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1027 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 1028 f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); 1029 1030 /* Record the fields for the semantic handler. */ 1031 FLD (f_r1) = f_r1; 1032 FLD (f_r2) = f_r2; 1033 FLD (i_disp16) = f_disp16; 1034 FLD (i_src1) = & CPU (h_gr)[f_r1]; 1035 FLD (i_src2) = & CPU (h_gr)[f_r2]; 1036 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 1037 1038 #if WITH_PROFILE_MODEL_P 1039 /* Record the fields for profiling. */ 1040 if (PROFILE_MODEL_P (current_cpu)) 1041 { 1042 FLD (in_src1) = f_r1; 1043 FLD (in_src2) = f_r2; 1044 } 1045 #endif 1046 #undef FLD 1047 return idesc; 1048 } 1049 1050 extract_sfmt_beqz: 1051 { 1052 const IDESC *idesc = &m32rxf_insn_data[itype]; 1053 CGEN_INSN_WORD insn = entire_insn; 1054 #define FLD(f) abuf->fields.sfmt_beq.f 1055 UINT f_r2; 1056 SI f_disp16; 1057 1058 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 1059 f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); 1060 1061 /* Record the fields for the semantic handler. */ 1062 FLD (f_r2) = f_r2; 1063 FLD (i_disp16) = f_disp16; 1064 FLD (i_src2) = & CPU (h_gr)[f_r2]; 1065 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqz", "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0)); 1066 1067 #if WITH_PROFILE_MODEL_P 1068 /* Record the fields for profiling. */ 1069 if (PROFILE_MODEL_P (current_cpu)) 1070 { 1071 FLD (in_src2) = f_r2; 1072 } 1073 #endif 1074 #undef FLD 1075 return idesc; 1076 } 1077 1078 extract_sfmt_bl8: 1079 { 1080 const IDESC *idesc = &m32rxf_insn_data[itype]; 1081 CGEN_INSN_WORD insn = entire_insn; 1082 #define FLD(f) abuf->fields.sfmt_bl8.f 1083 SI f_disp8; 1084 1085 f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); 1086 1087 /* Record the fields for the semantic handler. */ 1088 FLD (i_disp8) = f_disp8; 1089 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); 1090 1091 #if WITH_PROFILE_MODEL_P 1092 /* Record the fields for profiling. */ 1093 if (PROFILE_MODEL_P (current_cpu)) 1094 { 1095 FLD (out_h_gr_SI_14) = 14; 1096 } 1097 #endif 1098 #undef FLD 1099 return idesc; 1100 } 1101 1102 extract_sfmt_bl24: 1103 { 1104 const IDESC *idesc = &m32rxf_insn_data[itype]; 1105 CGEN_INSN_WORD insn = entire_insn; 1106 #define FLD(f) abuf->fields.sfmt_bl24.f 1107 SI f_disp24; 1108 1109 f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); 1110 1111 /* Record the fields for the semantic handler. */ 1112 FLD (i_disp24) = f_disp24; 1113 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); 1114 1115 #if WITH_PROFILE_MODEL_P 1116 /* Record the fields for profiling. */ 1117 if (PROFILE_MODEL_P (current_cpu)) 1118 { 1119 FLD (out_h_gr_SI_14) = 14; 1120 } 1121 #endif 1122 #undef FLD 1123 return idesc; 1124 } 1125 1126 extract_sfmt_bcl8: 1127 { 1128 const IDESC *idesc = &m32rxf_insn_data[itype]; 1129 CGEN_INSN_WORD insn = entire_insn; 1130 #define FLD(f) abuf->fields.sfmt_bl8.f 1131 SI f_disp8; 1132 1133 f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); 1134 1135 /* Record the fields for the semantic handler. */ 1136 FLD (i_disp8) = f_disp8; 1137 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); 1138 1139 #if WITH_PROFILE_MODEL_P 1140 /* Record the fields for profiling. */ 1141 if (PROFILE_MODEL_P (current_cpu)) 1142 { 1143 FLD (out_h_gr_SI_14) = 14; 1144 } 1145 #endif 1146 #undef FLD 1147 return idesc; 1148 } 1149 1150 extract_sfmt_bcl24: 1151 { 1152 const IDESC *idesc = &m32rxf_insn_data[itype]; 1153 CGEN_INSN_WORD insn = entire_insn; 1154 #define FLD(f) abuf->fields.sfmt_bl24.f 1155 SI f_disp24; 1156 1157 f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); 1158 1159 /* Record the fields for the semantic handler. */ 1160 FLD (i_disp24) = f_disp24; 1161 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); 1162 1163 #if WITH_PROFILE_MODEL_P 1164 /* Record the fields for profiling. */ 1165 if (PROFILE_MODEL_P (current_cpu)) 1166 { 1167 FLD (out_h_gr_SI_14) = 14; 1168 } 1169 #endif 1170 #undef FLD 1171 return idesc; 1172 } 1173 1174 extract_sfmt_bra8: 1175 { 1176 const IDESC *idesc = &m32rxf_insn_data[itype]; 1177 CGEN_INSN_WORD insn = entire_insn; 1178 #define FLD(f) abuf->fields.sfmt_bl8.f 1179 SI f_disp8; 1180 1181 f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); 1182 1183 /* Record the fields for the semantic handler. */ 1184 FLD (i_disp8) = f_disp8; 1185 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); 1186 1187 #if WITH_PROFILE_MODEL_P 1188 /* Record the fields for profiling. */ 1189 if (PROFILE_MODEL_P (current_cpu)) 1190 { 1191 } 1192 #endif 1193 #undef FLD 1194 return idesc; 1195 } 1196 1197 extract_sfmt_bra24: 1198 { 1199 const IDESC *idesc = &m32rxf_insn_data[itype]; 1200 CGEN_INSN_WORD insn = entire_insn; 1201 #define FLD(f) abuf->fields.sfmt_bl24.f 1202 SI f_disp24; 1203 1204 f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); 1205 1206 /* Record the fields for the semantic handler. */ 1207 FLD (i_disp24) = f_disp24; 1208 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); 1209 1210 #if WITH_PROFILE_MODEL_P 1211 /* Record the fields for profiling. */ 1212 if (PROFILE_MODEL_P (current_cpu)) 1213 { 1214 } 1215 #endif 1216 #undef FLD 1217 return idesc; 1218 } 1219 1220 extract_sfmt_cmp: 1221 { 1222 const IDESC *idesc = &m32rxf_insn_data[itype]; 1223 CGEN_INSN_WORD insn = entire_insn; 1224 #define FLD(f) abuf->fields.sfmt_st_plus.f 1225 UINT f_r1; 1226 UINT f_r2; 1227 1228 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1229 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1230 1231 /* Record the fields for the semantic handler. */ 1232 FLD (f_r1) = f_r1; 1233 FLD (f_r2) = f_r2; 1234 FLD (i_src1) = & CPU (h_gr)[f_r1]; 1235 FLD (i_src2) = & CPU (h_gr)[f_r2]; 1236 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 1237 1238 #if WITH_PROFILE_MODEL_P 1239 /* Record the fields for profiling. */ 1240 if (PROFILE_MODEL_P (current_cpu)) 1241 { 1242 FLD (in_src1) = f_r1; 1243 FLD (in_src2) = f_r2; 1244 } 1245 #endif 1246 #undef FLD 1247 return idesc; 1248 } 1249 1250 extract_sfmt_cmpi: 1251 { 1252 const IDESC *idesc = &m32rxf_insn_data[itype]; 1253 CGEN_INSN_WORD insn = entire_insn; 1254 #define FLD(f) abuf->fields.sfmt_st_d.f 1255 UINT f_r2; 1256 INT f_simm16; 1257 1258 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 1259 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 1260 1261 /* Record the fields for the semantic handler. */ 1262 FLD (f_simm16) = f_simm16; 1263 FLD (f_r2) = f_r2; 1264 FLD (i_src2) = & CPU (h_gr)[f_r2]; 1265 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0)); 1266 1267 #if WITH_PROFILE_MODEL_P 1268 /* Record the fields for profiling. */ 1269 if (PROFILE_MODEL_P (current_cpu)) 1270 { 1271 FLD (in_src2) = f_r2; 1272 } 1273 #endif 1274 #undef FLD 1275 return idesc; 1276 } 1277 1278 extract_sfmt_cmpz: 1279 { 1280 const IDESC *idesc = &m32rxf_insn_data[itype]; 1281 CGEN_INSN_WORD insn = entire_insn; 1282 #define FLD(f) abuf->fields.sfmt_st_plus.f 1283 UINT f_r2; 1284 1285 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1286 1287 /* Record the fields for the semantic handler. */ 1288 FLD (f_r2) = f_r2; 1289 FLD (i_src2) = & CPU (h_gr)[f_r2]; 1290 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpz", "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0)); 1291 1292 #if WITH_PROFILE_MODEL_P 1293 /* Record the fields for profiling. */ 1294 if (PROFILE_MODEL_P (current_cpu)) 1295 { 1296 FLD (in_src2) = f_r2; 1297 } 1298 #endif 1299 #undef FLD 1300 return idesc; 1301 } 1302 1303 extract_sfmt_div: 1304 { 1305 const IDESC *idesc = &m32rxf_insn_data[itype]; 1306 CGEN_INSN_WORD insn = entire_insn; 1307 #define FLD(f) abuf->fields.sfmt_add.f 1308 UINT f_r1; 1309 UINT f_r2; 1310 1311 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1312 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 1313 1314 /* Record the fields for the semantic handler. */ 1315 FLD (f_r1) = f_r1; 1316 FLD (f_r2) = f_r2; 1317 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1318 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1319 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); 1320 1321 #if WITH_PROFILE_MODEL_P 1322 /* Record the fields for profiling. */ 1323 if (PROFILE_MODEL_P (current_cpu)) 1324 { 1325 FLD (in_dr) = f_r1; 1326 FLD (in_sr) = f_r2; 1327 FLD (out_dr) = f_r1; 1328 } 1329 #endif 1330 #undef FLD 1331 return idesc; 1332 } 1333 1334 extract_sfmt_jc: 1335 { 1336 const IDESC *idesc = &m32rxf_insn_data[itype]; 1337 CGEN_INSN_WORD insn = entire_insn; 1338 #define FLD(f) abuf->fields.sfmt_jl.f 1339 UINT f_r2; 1340 1341 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1342 1343 /* Record the fields for the semantic handler. */ 1344 FLD (f_r2) = f_r2; 1345 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1346 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jc", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0)); 1347 1348 #if WITH_PROFILE_MODEL_P 1349 /* Record the fields for profiling. */ 1350 if (PROFILE_MODEL_P (current_cpu)) 1351 { 1352 FLD (in_sr) = f_r2; 1353 } 1354 #endif 1355 #undef FLD 1356 return idesc; 1357 } 1358 1359 extract_sfmt_jl: 1360 { 1361 const IDESC *idesc = &m32rxf_insn_data[itype]; 1362 CGEN_INSN_WORD insn = entire_insn; 1363 #define FLD(f) abuf->fields.sfmt_jl.f 1364 UINT f_r2; 1365 1366 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1367 1368 /* Record the fields for the semantic handler. */ 1369 FLD (f_r2) = f_r2; 1370 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1371 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0)); 1372 1373 #if WITH_PROFILE_MODEL_P 1374 /* Record the fields for profiling. */ 1375 if (PROFILE_MODEL_P (current_cpu)) 1376 { 1377 FLD (in_sr) = f_r2; 1378 FLD (out_h_gr_SI_14) = 14; 1379 } 1380 #endif 1381 #undef FLD 1382 return idesc; 1383 } 1384 1385 extract_sfmt_jmp: 1386 { 1387 const IDESC *idesc = &m32rxf_insn_data[itype]; 1388 CGEN_INSN_WORD insn = entire_insn; 1389 #define FLD(f) abuf->fields.sfmt_jl.f 1390 UINT f_r2; 1391 1392 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1393 1394 /* Record the fields for the semantic handler. */ 1395 FLD (f_r2) = f_r2; 1396 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1397 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0)); 1398 1399 #if WITH_PROFILE_MODEL_P 1400 /* Record the fields for profiling. */ 1401 if (PROFILE_MODEL_P (current_cpu)) 1402 { 1403 FLD (in_sr) = f_r2; 1404 } 1405 #endif 1406 #undef FLD 1407 return idesc; 1408 } 1409 1410 extract_sfmt_ld: 1411 { 1412 const IDESC *idesc = &m32rxf_insn_data[itype]; 1413 CGEN_INSN_WORD insn = entire_insn; 1414 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1415 UINT f_r1; 1416 UINT f_r2; 1417 1418 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1419 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1420 1421 /* Record the fields for the semantic handler. */ 1422 FLD (f_r2) = f_r2; 1423 FLD (f_r1) = f_r1; 1424 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1425 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1426 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1427 1428 #if WITH_PROFILE_MODEL_P 1429 /* Record the fields for profiling. */ 1430 if (PROFILE_MODEL_P (current_cpu)) 1431 { 1432 FLD (in_sr) = f_r2; 1433 FLD (out_dr) = f_r1; 1434 } 1435 #endif 1436 #undef FLD 1437 return idesc; 1438 } 1439 1440 extract_sfmt_ld_d: 1441 { 1442 const IDESC *idesc = &m32rxf_insn_data[itype]; 1443 CGEN_INSN_WORD insn = entire_insn; 1444 #define FLD(f) abuf->fields.sfmt_add3.f 1445 UINT f_r1; 1446 UINT f_r2; 1447 INT f_simm16; 1448 1449 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1450 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 1451 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 1452 1453 /* Record the fields for the semantic handler. */ 1454 FLD (f_simm16) = f_simm16; 1455 FLD (f_r2) = f_r2; 1456 FLD (f_r1) = f_r1; 1457 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1458 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1459 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1460 1461 #if WITH_PROFILE_MODEL_P 1462 /* Record the fields for profiling. */ 1463 if (PROFILE_MODEL_P (current_cpu)) 1464 { 1465 FLD (in_sr) = f_r2; 1466 FLD (out_dr) = f_r1; 1467 } 1468 #endif 1469 #undef FLD 1470 return idesc; 1471 } 1472 1473 extract_sfmt_ldb: 1474 { 1475 const IDESC *idesc = &m32rxf_insn_data[itype]; 1476 CGEN_INSN_WORD insn = entire_insn; 1477 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1478 UINT f_r1; 1479 UINT f_r2; 1480 1481 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1482 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1483 1484 /* Record the fields for the semantic handler. */ 1485 FLD (f_r2) = f_r2; 1486 FLD (f_r1) = f_r1; 1487 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1488 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1489 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1490 1491 #if WITH_PROFILE_MODEL_P 1492 /* Record the fields for profiling. */ 1493 if (PROFILE_MODEL_P (current_cpu)) 1494 { 1495 FLD (in_sr) = f_r2; 1496 FLD (out_dr) = f_r1; 1497 } 1498 #endif 1499 #undef FLD 1500 return idesc; 1501 } 1502 1503 extract_sfmt_ldb_d: 1504 { 1505 const IDESC *idesc = &m32rxf_insn_data[itype]; 1506 CGEN_INSN_WORD insn = entire_insn; 1507 #define FLD(f) abuf->fields.sfmt_add3.f 1508 UINT f_r1; 1509 UINT f_r2; 1510 INT f_simm16; 1511 1512 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1513 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 1514 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 1515 1516 /* Record the fields for the semantic handler. */ 1517 FLD (f_simm16) = f_simm16; 1518 FLD (f_r2) = f_r2; 1519 FLD (f_r1) = f_r1; 1520 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1521 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1522 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1523 1524 #if WITH_PROFILE_MODEL_P 1525 /* Record the fields for profiling. */ 1526 if (PROFILE_MODEL_P (current_cpu)) 1527 { 1528 FLD (in_sr) = f_r2; 1529 FLD (out_dr) = f_r1; 1530 } 1531 #endif 1532 #undef FLD 1533 return idesc; 1534 } 1535 1536 extract_sfmt_ldh: 1537 { 1538 const IDESC *idesc = &m32rxf_insn_data[itype]; 1539 CGEN_INSN_WORD insn = entire_insn; 1540 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1541 UINT f_r1; 1542 UINT f_r2; 1543 1544 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1545 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1546 1547 /* Record the fields for the semantic handler. */ 1548 FLD (f_r2) = f_r2; 1549 FLD (f_r1) = f_r1; 1550 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1551 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1552 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1553 1554 #if WITH_PROFILE_MODEL_P 1555 /* Record the fields for profiling. */ 1556 if (PROFILE_MODEL_P (current_cpu)) 1557 { 1558 FLD (in_sr) = f_r2; 1559 FLD (out_dr) = f_r1; 1560 } 1561 #endif 1562 #undef FLD 1563 return idesc; 1564 } 1565 1566 extract_sfmt_ldh_d: 1567 { 1568 const IDESC *idesc = &m32rxf_insn_data[itype]; 1569 CGEN_INSN_WORD insn = entire_insn; 1570 #define FLD(f) abuf->fields.sfmt_add3.f 1571 UINT f_r1; 1572 UINT f_r2; 1573 INT f_simm16; 1574 1575 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1576 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 1577 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 1578 1579 /* Record the fields for the semantic handler. */ 1580 FLD (f_simm16) = f_simm16; 1581 FLD (f_r2) = f_r2; 1582 FLD (f_r1) = f_r1; 1583 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1584 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1585 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1586 1587 #if WITH_PROFILE_MODEL_P 1588 /* Record the fields for profiling. */ 1589 if (PROFILE_MODEL_P (current_cpu)) 1590 { 1591 FLD (in_sr) = f_r2; 1592 FLD (out_dr) = f_r1; 1593 } 1594 #endif 1595 #undef FLD 1596 return idesc; 1597 } 1598 1599 extract_sfmt_ld_plus: 1600 { 1601 const IDESC *idesc = &m32rxf_insn_data[itype]; 1602 CGEN_INSN_WORD insn = entire_insn; 1603 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1604 UINT f_r1; 1605 UINT f_r2; 1606 1607 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1608 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1609 1610 /* Record the fields for the semantic handler. */ 1611 FLD (f_r2) = f_r2; 1612 FLD (f_r1) = f_r1; 1613 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1614 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1615 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_plus", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1616 1617 #if WITH_PROFILE_MODEL_P 1618 /* Record the fields for profiling. */ 1619 if (PROFILE_MODEL_P (current_cpu)) 1620 { 1621 FLD (in_sr) = f_r2; 1622 FLD (out_dr) = f_r1; 1623 FLD (out_sr) = f_r2; 1624 } 1625 #endif 1626 #undef FLD 1627 return idesc; 1628 } 1629 1630 extract_sfmt_ld24: 1631 { 1632 const IDESC *idesc = &m32rxf_insn_data[itype]; 1633 CGEN_INSN_WORD insn = entire_insn; 1634 #define FLD(f) abuf->fields.sfmt_ld24.f 1635 UINT f_r1; 1636 UINT f_uimm24; 1637 1638 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1639 f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); 1640 1641 /* Record the fields for the semantic handler. */ 1642 FLD (f_r1) = f_r1; 1643 FLD (i_uimm24) = f_uimm24; 1644 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1645 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld24", "f_r1 0x%x", 'x', f_r1, "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0)); 1646 1647 #if WITH_PROFILE_MODEL_P 1648 /* Record the fields for profiling. */ 1649 if (PROFILE_MODEL_P (current_cpu)) 1650 { 1651 FLD (out_dr) = f_r1; 1652 } 1653 #endif 1654 #undef FLD 1655 return idesc; 1656 } 1657 1658 extract_sfmt_ldi8: 1659 { 1660 const IDESC *idesc = &m32rxf_insn_data[itype]; 1661 CGEN_INSN_WORD insn = entire_insn; 1662 #define FLD(f) abuf->fields.sfmt_addi.f 1663 UINT f_r1; 1664 INT f_simm8; 1665 1666 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1667 f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8); 1668 1669 /* Record the fields for the semantic handler. */ 1670 FLD (f_simm8) = f_simm8; 1671 FLD (f_r1) = f_r1; 1672 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1673 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); 1674 1675 #if WITH_PROFILE_MODEL_P 1676 /* Record the fields for profiling. */ 1677 if (PROFILE_MODEL_P (current_cpu)) 1678 { 1679 FLD (out_dr) = f_r1; 1680 } 1681 #endif 1682 #undef FLD 1683 return idesc; 1684 } 1685 1686 extract_sfmt_ldi16: 1687 { 1688 const IDESC *idesc = &m32rxf_insn_data[itype]; 1689 CGEN_INSN_WORD insn = entire_insn; 1690 #define FLD(f) abuf->fields.sfmt_add3.f 1691 UINT f_r1; 1692 INT f_simm16; 1693 1694 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1695 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 1696 1697 /* Record the fields for the semantic handler. */ 1698 FLD (f_simm16) = f_simm16; 1699 FLD (f_r1) = f_r1; 1700 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1701 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); 1702 1703 #if WITH_PROFILE_MODEL_P 1704 /* Record the fields for profiling. */ 1705 if (PROFILE_MODEL_P (current_cpu)) 1706 { 1707 FLD (out_dr) = f_r1; 1708 } 1709 #endif 1710 #undef FLD 1711 return idesc; 1712 } 1713 1714 extract_sfmt_lock: 1715 { 1716 const IDESC *idesc = &m32rxf_insn_data[itype]; 1717 CGEN_INSN_WORD insn = entire_insn; 1718 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1719 UINT f_r1; 1720 UINT f_r2; 1721 1722 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1723 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1724 1725 /* Record the fields for the semantic handler. */ 1726 FLD (f_r2) = f_r2; 1727 FLD (f_r1) = f_r1; 1728 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1729 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1730 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lock", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1731 1732 #if WITH_PROFILE_MODEL_P 1733 /* Record the fields for profiling. */ 1734 if (PROFILE_MODEL_P (current_cpu)) 1735 { 1736 FLD (in_sr) = f_r2; 1737 FLD (out_dr) = f_r1; 1738 } 1739 #endif 1740 #undef FLD 1741 return idesc; 1742 } 1743 1744 extract_sfmt_machi_a: 1745 { 1746 const IDESC *idesc = &m32rxf_insn_data[itype]; 1747 CGEN_INSN_WORD insn = entire_insn; 1748 #define FLD(f) abuf->fields.sfmt_machi_a.f 1749 UINT f_r1; 1750 UINT f_acc; 1751 UINT f_r2; 1752 1753 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1754 f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); 1755 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1756 1757 /* Record the fields for the semantic handler. */ 1758 FLD (f_acc) = f_acc; 1759 FLD (f_r1) = f_r1; 1760 FLD (f_r2) = f_r2; 1761 FLD (i_src1) = & CPU (h_gr)[f_r1]; 1762 FLD (i_src2) = & CPU (h_gr)[f_r2]; 1763 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machi_a", "f_acc 0x%x", 'x', f_acc, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 1764 1765 #if WITH_PROFILE_MODEL_P 1766 /* Record the fields for profiling. */ 1767 if (PROFILE_MODEL_P (current_cpu)) 1768 { 1769 FLD (in_src1) = f_r1; 1770 FLD (in_src2) = f_r2; 1771 } 1772 #endif 1773 #undef FLD 1774 return idesc; 1775 } 1776 1777 extract_sfmt_mulhi_a: 1778 { 1779 const IDESC *idesc = &m32rxf_insn_data[itype]; 1780 CGEN_INSN_WORD insn = entire_insn; 1781 #define FLD(f) abuf->fields.sfmt_machi_a.f 1782 UINT f_r1; 1783 UINT f_acc; 1784 UINT f_r2; 1785 1786 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1787 f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); 1788 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1789 1790 /* Record the fields for the semantic handler. */ 1791 FLD (f_r1) = f_r1; 1792 FLD (f_r2) = f_r2; 1793 FLD (f_acc) = f_acc; 1794 FLD (i_src1) = & CPU (h_gr)[f_r1]; 1795 FLD (i_src2) = & CPU (h_gr)[f_r2]; 1796 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulhi_a", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "f_acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 1797 1798 #if WITH_PROFILE_MODEL_P 1799 /* Record the fields for profiling. */ 1800 if (PROFILE_MODEL_P (current_cpu)) 1801 { 1802 FLD (in_src1) = f_r1; 1803 FLD (in_src2) = f_r2; 1804 } 1805 #endif 1806 #undef FLD 1807 return idesc; 1808 } 1809 1810 extract_sfmt_mv: 1811 { 1812 const IDESC *idesc = &m32rxf_insn_data[itype]; 1813 CGEN_INSN_WORD insn = entire_insn; 1814 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1815 UINT f_r1; 1816 UINT f_r2; 1817 1818 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1819 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1820 1821 /* Record the fields for the semantic handler. */ 1822 FLD (f_r2) = f_r2; 1823 FLD (f_r1) = f_r1; 1824 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1825 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1826 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mv", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1827 1828 #if WITH_PROFILE_MODEL_P 1829 /* Record the fields for profiling. */ 1830 if (PROFILE_MODEL_P (current_cpu)) 1831 { 1832 FLD (in_sr) = f_r2; 1833 FLD (out_dr) = f_r1; 1834 } 1835 #endif 1836 #undef FLD 1837 return idesc; 1838 } 1839 1840 extract_sfmt_mvfachi_a: 1841 { 1842 const IDESC *idesc = &m32rxf_insn_data[itype]; 1843 CGEN_INSN_WORD insn = entire_insn; 1844 #define FLD(f) abuf->fields.sfmt_mvfachi_a.f 1845 UINT f_r1; 1846 UINT f_accs; 1847 1848 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1849 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); 1850 1851 /* Record the fields for the semantic handler. */ 1852 FLD (f_accs) = f_accs; 1853 FLD (f_r1) = f_r1; 1854 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1855 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); 1856 1857 #if WITH_PROFILE_MODEL_P 1858 /* Record the fields for profiling. */ 1859 if (PROFILE_MODEL_P (current_cpu)) 1860 { 1861 FLD (out_dr) = f_r1; 1862 } 1863 #endif 1864 #undef FLD 1865 return idesc; 1866 } 1867 1868 extract_sfmt_mvfc: 1869 { 1870 const IDESC *idesc = &m32rxf_insn_data[itype]; 1871 CGEN_INSN_WORD insn = entire_insn; 1872 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1873 UINT f_r1; 1874 UINT f_r2; 1875 1876 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1877 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1878 1879 /* Record the fields for the semantic handler. */ 1880 FLD (f_r2) = f_r2; 1881 FLD (f_r1) = f_r1; 1882 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1883 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); 1884 1885 #if WITH_PROFILE_MODEL_P 1886 /* Record the fields for profiling. */ 1887 if (PROFILE_MODEL_P (current_cpu)) 1888 { 1889 FLD (out_dr) = f_r1; 1890 } 1891 #endif 1892 #undef FLD 1893 return idesc; 1894 } 1895 1896 extract_sfmt_mvtachi_a: 1897 { 1898 const IDESC *idesc = &m32rxf_insn_data[itype]; 1899 CGEN_INSN_WORD insn = entire_insn; 1900 #define FLD(f) abuf->fields.sfmt_mvtachi_a.f 1901 UINT f_r1; 1902 UINT f_accs; 1903 1904 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1905 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); 1906 1907 /* Record the fields for the semantic handler. */ 1908 FLD (f_accs) = f_accs; 1909 FLD (f_r1) = f_r1; 1910 FLD (i_src1) = & CPU (h_gr)[f_r1]; 1911 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "src1 0x%x", 'x', f_r1, (char *) 0)); 1912 1913 #if WITH_PROFILE_MODEL_P 1914 /* Record the fields for profiling. */ 1915 if (PROFILE_MODEL_P (current_cpu)) 1916 { 1917 FLD (in_src1) = f_r1; 1918 } 1919 #endif 1920 #undef FLD 1921 return idesc; 1922 } 1923 1924 extract_sfmt_mvtc: 1925 { 1926 const IDESC *idesc = &m32rxf_insn_data[itype]; 1927 CGEN_INSN_WORD insn = entire_insn; 1928 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1929 UINT f_r1; 1930 UINT f_r2; 1931 1932 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1933 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1934 1935 /* Record the fields for the semantic handler. */ 1936 FLD (f_r2) = f_r2; 1937 FLD (f_r1) = f_r1; 1938 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1939 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); 1940 1941 #if WITH_PROFILE_MODEL_P 1942 /* Record the fields for profiling. */ 1943 if (PROFILE_MODEL_P (current_cpu)) 1944 { 1945 FLD (in_sr) = f_r2; 1946 } 1947 #endif 1948 #undef FLD 1949 return idesc; 1950 } 1951 1952 extract_sfmt_nop: 1953 { 1954 const IDESC *idesc = &m32rxf_insn_data[itype]; 1955 #define FLD(f) abuf->fields.sfmt_empty.f 1956 1957 1958 /* Record the fields for the semantic handler. */ 1959 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0)); 1960 1961 #undef FLD 1962 return idesc; 1963 } 1964 1965 extract_sfmt_rac_dsi: 1966 { 1967 const IDESC *idesc = &m32rxf_insn_data[itype]; 1968 CGEN_INSN_WORD insn = entire_insn; 1969 #define FLD(f) abuf->fields.sfmt_rac_dsi.f 1970 UINT f_accd; 1971 UINT f_accs; 1972 SI f_imm1; 1973 1974 f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2); 1975 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); 1976 f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1)); 1977 1978 /* Record the fields for the semantic handler. */ 1979 FLD (f_accs) = f_accs; 1980 FLD (f_imm1) = f_imm1; 1981 FLD (f_accd) = f_accd; 1982 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rac_dsi", "f_accs 0x%x", 'x', f_accs, "f_imm1 0x%x", 'x', f_imm1, "f_accd 0x%x", 'x', f_accd, (char *) 0)); 1983 1984 #undef FLD 1985 return idesc; 1986 } 1987 1988 extract_sfmt_rte: 1989 { 1990 const IDESC *idesc = &m32rxf_insn_data[itype]; 1991 #define FLD(f) abuf->fields.sfmt_empty.f 1992 1993 1994 /* Record the fields for the semantic handler. */ 1995 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rte", (char *) 0)); 1996 1997 #if WITH_PROFILE_MODEL_P 1998 /* Record the fields for profiling. */ 1999 if (PROFILE_MODEL_P (current_cpu)) 2000 { 2001 } 2002 #endif 2003 #undef FLD 2004 return idesc; 2005 } 2006 2007 extract_sfmt_seth: 2008 { 2009 const IDESC *idesc = &m32rxf_insn_data[itype]; 2010 CGEN_INSN_WORD insn = entire_insn; 2011 #define FLD(f) abuf->fields.sfmt_seth.f 2012 UINT f_r1; 2013 UINT f_hi16; 2014 2015 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 2016 f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); 2017 2018 /* Record the fields for the semantic handler. */ 2019 FLD (f_hi16) = f_hi16; 2020 FLD (f_r1) = f_r1; 2021 FLD (i_dr) = & CPU (h_gr)[f_r1]; 2022 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_seth", "f_hi16 0x%x", 'x', f_hi16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); 2023 2024 #if WITH_PROFILE_MODEL_P 2025 /* Record the fields for profiling. */ 2026 if (PROFILE_MODEL_P (current_cpu)) 2027 { 2028 FLD (out_dr) = f_r1; 2029 } 2030 #endif 2031 #undef FLD 2032 return idesc; 2033 } 2034 2035 extract_sfmt_sll3: 2036 { 2037 const IDESC *idesc = &m32rxf_insn_data[itype]; 2038 CGEN_INSN_WORD insn = entire_insn; 2039 #define FLD(f) abuf->fields.sfmt_add3.f 2040 UINT f_r1; 2041 UINT f_r2; 2042 INT f_simm16; 2043 2044 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 2045 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 2046 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 2047 2048 /* Record the fields for the semantic handler. */ 2049 FLD (f_simm16) = f_simm16; 2050 FLD (f_r2) = f_r2; 2051 FLD (f_r1) = f_r1; 2052 FLD (i_sr) = & CPU (h_gr)[f_r2]; 2053 FLD (i_dr) = & CPU (h_gr)[f_r1]; 2054 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 2055 2056 #if WITH_PROFILE_MODEL_P 2057 /* Record the fields for profiling. */ 2058 if (PROFILE_MODEL_P (current_cpu)) 2059 { 2060 FLD (in_sr) = f_r2; 2061 FLD (out_dr) = f_r1; 2062 } 2063 #endif 2064 #undef FLD 2065 return idesc; 2066 } 2067 2068 extract_sfmt_slli: 2069 { 2070 const IDESC *idesc = &m32rxf_insn_data[itype]; 2071 CGEN_INSN_WORD insn = entire_insn; 2072 #define FLD(f) abuf->fields.sfmt_slli.f 2073 UINT f_r1; 2074 UINT f_uimm5; 2075 2076 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2077 f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); 2078 2079 /* Record the fields for the semantic handler. */ 2080 FLD (f_r1) = f_r1; 2081 FLD (f_uimm5) = f_uimm5; 2082 FLD (i_dr) = & CPU (h_gr)[f_r1]; 2083 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slli", "f_r1 0x%x", 'x', f_r1, "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0)); 2084 2085 #if WITH_PROFILE_MODEL_P 2086 /* Record the fields for profiling. */ 2087 if (PROFILE_MODEL_P (current_cpu)) 2088 { 2089 FLD (in_dr) = f_r1; 2090 FLD (out_dr) = f_r1; 2091 } 2092 #endif 2093 #undef FLD 2094 return idesc; 2095 } 2096 2097 extract_sfmt_st: 2098 { 2099 const IDESC *idesc = &m32rxf_insn_data[itype]; 2100 CGEN_INSN_WORD insn = entire_insn; 2101 #define FLD(f) abuf->fields.sfmt_st_plus.f 2102 UINT f_r1; 2103 UINT f_r2; 2104 2105 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2106 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2107 2108 /* Record the fields for the semantic handler. */ 2109 FLD (f_r1) = f_r1; 2110 FLD (f_r2) = f_r2; 2111 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2112 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2113 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2114 2115 #if WITH_PROFILE_MODEL_P 2116 /* Record the fields for profiling. */ 2117 if (PROFILE_MODEL_P (current_cpu)) 2118 { 2119 FLD (in_src1) = f_r1; 2120 FLD (in_src2) = f_r2; 2121 } 2122 #endif 2123 #undef FLD 2124 return idesc; 2125 } 2126 2127 extract_sfmt_st_d: 2128 { 2129 const IDESC *idesc = &m32rxf_insn_data[itype]; 2130 CGEN_INSN_WORD insn = entire_insn; 2131 #define FLD(f) abuf->fields.sfmt_st_d.f 2132 UINT f_r1; 2133 UINT f_r2; 2134 INT f_simm16; 2135 2136 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 2137 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 2138 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 2139 2140 /* Record the fields for the semantic handler. */ 2141 FLD (f_simm16) = f_simm16; 2142 FLD (f_r1) = f_r1; 2143 FLD (f_r2) = f_r2; 2144 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2145 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2146 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2147 2148 #if WITH_PROFILE_MODEL_P 2149 /* Record the fields for profiling. */ 2150 if (PROFILE_MODEL_P (current_cpu)) 2151 { 2152 FLD (in_src1) = f_r1; 2153 FLD (in_src2) = f_r2; 2154 } 2155 #endif 2156 #undef FLD 2157 return idesc; 2158 } 2159 2160 extract_sfmt_stb: 2161 { 2162 const IDESC *idesc = &m32rxf_insn_data[itype]; 2163 CGEN_INSN_WORD insn = entire_insn; 2164 #define FLD(f) abuf->fields.sfmt_st_plus.f 2165 UINT f_r1; 2166 UINT f_r2; 2167 2168 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2169 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2170 2171 /* Record the fields for the semantic handler. */ 2172 FLD (f_r1) = f_r1; 2173 FLD (f_r2) = f_r2; 2174 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2175 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2176 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2177 2178 #if WITH_PROFILE_MODEL_P 2179 /* Record the fields for profiling. */ 2180 if (PROFILE_MODEL_P (current_cpu)) 2181 { 2182 FLD (in_src1) = f_r1; 2183 FLD (in_src2) = f_r2; 2184 } 2185 #endif 2186 #undef FLD 2187 return idesc; 2188 } 2189 2190 extract_sfmt_stb_d: 2191 { 2192 const IDESC *idesc = &m32rxf_insn_data[itype]; 2193 CGEN_INSN_WORD insn = entire_insn; 2194 #define FLD(f) abuf->fields.sfmt_st_d.f 2195 UINT f_r1; 2196 UINT f_r2; 2197 INT f_simm16; 2198 2199 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 2200 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 2201 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 2202 2203 /* Record the fields for the semantic handler. */ 2204 FLD (f_simm16) = f_simm16; 2205 FLD (f_r1) = f_r1; 2206 FLD (f_r2) = f_r2; 2207 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2208 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2209 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2210 2211 #if WITH_PROFILE_MODEL_P 2212 /* Record the fields for profiling. */ 2213 if (PROFILE_MODEL_P (current_cpu)) 2214 { 2215 FLD (in_src1) = f_r1; 2216 FLD (in_src2) = f_r2; 2217 } 2218 #endif 2219 #undef FLD 2220 return idesc; 2221 } 2222 2223 extract_sfmt_sth: 2224 { 2225 const IDESC *idesc = &m32rxf_insn_data[itype]; 2226 CGEN_INSN_WORD insn = entire_insn; 2227 #define FLD(f) abuf->fields.sfmt_st_plus.f 2228 UINT f_r1; 2229 UINT f_r2; 2230 2231 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2232 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2233 2234 /* Record the fields for the semantic handler. */ 2235 FLD (f_r1) = f_r1; 2236 FLD (f_r2) = f_r2; 2237 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2238 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2239 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2240 2241 #if WITH_PROFILE_MODEL_P 2242 /* Record the fields for profiling. */ 2243 if (PROFILE_MODEL_P (current_cpu)) 2244 { 2245 FLD (in_src1) = f_r1; 2246 FLD (in_src2) = f_r2; 2247 } 2248 #endif 2249 #undef FLD 2250 return idesc; 2251 } 2252 2253 extract_sfmt_sth_d: 2254 { 2255 const IDESC *idesc = &m32rxf_insn_data[itype]; 2256 CGEN_INSN_WORD insn = entire_insn; 2257 #define FLD(f) abuf->fields.sfmt_st_d.f 2258 UINT f_r1; 2259 UINT f_r2; 2260 INT f_simm16; 2261 2262 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 2263 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 2264 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 2265 2266 /* Record the fields for the semantic handler. */ 2267 FLD (f_simm16) = f_simm16; 2268 FLD (f_r1) = f_r1; 2269 FLD (f_r2) = f_r2; 2270 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2271 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2272 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2273 2274 #if WITH_PROFILE_MODEL_P 2275 /* Record the fields for profiling. */ 2276 if (PROFILE_MODEL_P (current_cpu)) 2277 { 2278 FLD (in_src1) = f_r1; 2279 FLD (in_src2) = f_r2; 2280 } 2281 #endif 2282 #undef FLD 2283 return idesc; 2284 } 2285 2286 extract_sfmt_st_plus: 2287 { 2288 const IDESC *idesc = &m32rxf_insn_data[itype]; 2289 CGEN_INSN_WORD insn = entire_insn; 2290 #define FLD(f) abuf->fields.sfmt_st_plus.f 2291 UINT f_r1; 2292 UINT f_r2; 2293 2294 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2295 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2296 2297 /* Record the fields for the semantic handler. */ 2298 FLD (f_r1) = f_r1; 2299 FLD (f_r2) = f_r2; 2300 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2301 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2302 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2303 2304 #if WITH_PROFILE_MODEL_P 2305 /* Record the fields for profiling. */ 2306 if (PROFILE_MODEL_P (current_cpu)) 2307 { 2308 FLD (in_src1) = f_r1; 2309 FLD (in_src2) = f_r2; 2310 FLD (out_src2) = f_r2; 2311 } 2312 #endif 2313 #undef FLD 2314 return idesc; 2315 } 2316 2317 extract_sfmt_sth_plus: 2318 { 2319 const IDESC *idesc = &m32rxf_insn_data[itype]; 2320 CGEN_INSN_WORD insn = entire_insn; 2321 #define FLD(f) abuf->fields.sfmt_st_plus.f 2322 UINT f_r1; 2323 UINT f_r2; 2324 2325 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2326 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2327 2328 /* Record the fields for the semantic handler. */ 2329 FLD (f_r1) = f_r1; 2330 FLD (f_r2) = f_r2; 2331 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2332 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2333 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2334 2335 #if WITH_PROFILE_MODEL_P 2336 /* Record the fields for profiling. */ 2337 if (PROFILE_MODEL_P (current_cpu)) 2338 { 2339 FLD (in_src1) = f_r1; 2340 FLD (in_src2) = f_r2; 2341 FLD (out_src2) = f_r2; 2342 } 2343 #endif 2344 #undef FLD 2345 return idesc; 2346 } 2347 2348 extract_sfmt_stb_plus: 2349 { 2350 const IDESC *idesc = &m32rxf_insn_data[itype]; 2351 CGEN_INSN_WORD insn = entire_insn; 2352 #define FLD(f) abuf->fields.sfmt_st_plus.f 2353 UINT f_r1; 2354 UINT f_r2; 2355 2356 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2357 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2358 2359 /* Record the fields for the semantic handler. */ 2360 FLD (f_r1) = f_r1; 2361 FLD (f_r2) = f_r2; 2362 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2363 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2364 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2365 2366 #if WITH_PROFILE_MODEL_P 2367 /* Record the fields for profiling. */ 2368 if (PROFILE_MODEL_P (current_cpu)) 2369 { 2370 FLD (in_src1) = f_r1; 2371 FLD (in_src2) = f_r2; 2372 FLD (out_src2) = f_r2; 2373 } 2374 #endif 2375 #undef FLD 2376 return idesc; 2377 } 2378 2379 extract_sfmt_trap: 2380 { 2381 const IDESC *idesc = &m32rxf_insn_data[itype]; 2382 CGEN_INSN_WORD insn = entire_insn; 2383 #define FLD(f) abuf->fields.sfmt_trap.f 2384 UINT f_uimm4; 2385 2386 f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2387 2388 /* Record the fields for the semantic handler. */ 2389 FLD (f_uimm4) = f_uimm4; 2390 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0)); 2391 2392 #if WITH_PROFILE_MODEL_P 2393 /* Record the fields for profiling. */ 2394 if (PROFILE_MODEL_P (current_cpu)) 2395 { 2396 } 2397 #endif 2398 #undef FLD 2399 return idesc; 2400 } 2401 2402 extract_sfmt_unlock: 2403 { 2404 const IDESC *idesc = &m32rxf_insn_data[itype]; 2405 CGEN_INSN_WORD insn = entire_insn; 2406 #define FLD(f) abuf->fields.sfmt_st_plus.f 2407 UINT f_r1; 2408 UINT f_r2; 2409 2410 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2411 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2412 2413 /* Record the fields for the semantic handler. */ 2414 FLD (f_r1) = f_r1; 2415 FLD (f_r2) = f_r2; 2416 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2417 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2418 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_unlock", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2419 2420 #if WITH_PROFILE_MODEL_P 2421 /* Record the fields for profiling. */ 2422 if (PROFILE_MODEL_P (current_cpu)) 2423 { 2424 FLD (in_src1) = f_r1; 2425 FLD (in_src2) = f_r2; 2426 } 2427 #endif 2428 #undef FLD 2429 return idesc; 2430 } 2431 2432 extract_sfmt_satb: 2433 { 2434 const IDESC *idesc = &m32rxf_insn_data[itype]; 2435 CGEN_INSN_WORD insn = entire_insn; 2436 #define FLD(f) abuf->fields.sfmt_ld_plus.f 2437 UINT f_r1; 2438 UINT f_r2; 2439 2440 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 2441 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 2442 2443 /* Record the fields for the semantic handler. */ 2444 FLD (f_r2) = f_r2; 2445 FLD (f_r1) = f_r1; 2446 FLD (i_sr) = & CPU (h_gr)[f_r2]; 2447 FLD (i_dr) = & CPU (h_gr)[f_r1]; 2448 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_satb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 2449 2450 #if WITH_PROFILE_MODEL_P 2451 /* Record the fields for profiling. */ 2452 if (PROFILE_MODEL_P (current_cpu)) 2453 { 2454 FLD (in_sr) = f_r2; 2455 FLD (out_dr) = f_r1; 2456 } 2457 #endif 2458 #undef FLD 2459 return idesc; 2460 } 2461 2462 extract_sfmt_sat: 2463 { 2464 const IDESC *idesc = &m32rxf_insn_data[itype]; 2465 CGEN_INSN_WORD insn = entire_insn; 2466 #define FLD(f) abuf->fields.sfmt_ld_plus.f 2467 UINT f_r1; 2468 UINT f_r2; 2469 2470 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 2471 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 2472 2473 /* Record the fields for the semantic handler. */ 2474 FLD (f_r2) = f_r2; 2475 FLD (f_r1) = f_r1; 2476 FLD (i_sr) = & CPU (h_gr)[f_r2]; 2477 FLD (i_dr) = & CPU (h_gr)[f_r1]; 2478 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sat", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 2479 2480 #if WITH_PROFILE_MODEL_P 2481 /* Record the fields for profiling. */ 2482 if (PROFILE_MODEL_P (current_cpu)) 2483 { 2484 FLD (in_sr) = f_r2; 2485 FLD (out_dr) = f_r1; 2486 } 2487 #endif 2488 #undef FLD 2489 return idesc; 2490 } 2491 2492 extract_sfmt_sadd: 2493 { 2494 const IDESC *idesc = &m32rxf_insn_data[itype]; 2495 #define FLD(f) abuf->fields.sfmt_empty.f 2496 2497 2498 /* Record the fields for the semantic handler. */ 2499 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sadd", (char *) 0)); 2500 2501 #undef FLD 2502 return idesc; 2503 } 2504 2505 extract_sfmt_macwu1: 2506 { 2507 const IDESC *idesc = &m32rxf_insn_data[itype]; 2508 CGEN_INSN_WORD insn = entire_insn; 2509 #define FLD(f) abuf->fields.sfmt_st_plus.f 2510 UINT f_r1; 2511 UINT f_r2; 2512 2513 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2514 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2515 2516 /* Record the fields for the semantic handler. */ 2517 FLD (f_r1) = f_r1; 2518 FLD (f_r2) = f_r2; 2519 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2520 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2521 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_macwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2522 2523 #if WITH_PROFILE_MODEL_P 2524 /* Record the fields for profiling. */ 2525 if (PROFILE_MODEL_P (current_cpu)) 2526 { 2527 FLD (in_src1) = f_r1; 2528 FLD (in_src2) = f_r2; 2529 } 2530 #endif 2531 #undef FLD 2532 return idesc; 2533 } 2534 2535 extract_sfmt_msblo: 2536 { 2537 const IDESC *idesc = &m32rxf_insn_data[itype]; 2538 CGEN_INSN_WORD insn = entire_insn; 2539 #define FLD(f) abuf->fields.sfmt_st_plus.f 2540 UINT f_r1; 2541 UINT f_r2; 2542 2543 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2544 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2545 2546 /* Record the fields for the semantic handler. */ 2547 FLD (f_r1) = f_r1; 2548 FLD (f_r2) = f_r2; 2549 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2550 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2551 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_msblo", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2552 2553 #if WITH_PROFILE_MODEL_P 2554 /* Record the fields for profiling. */ 2555 if (PROFILE_MODEL_P (current_cpu)) 2556 { 2557 FLD (in_src1) = f_r1; 2558 FLD (in_src2) = f_r2; 2559 } 2560 #endif 2561 #undef FLD 2562 return idesc; 2563 } 2564 2565 extract_sfmt_mulwu1: 2566 { 2567 const IDESC *idesc = &m32rxf_insn_data[itype]; 2568 CGEN_INSN_WORD insn = entire_insn; 2569 #define FLD(f) abuf->fields.sfmt_st_plus.f 2570 UINT f_r1; 2571 UINT f_r2; 2572 2573 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2574 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2575 2576 /* Record the fields for the semantic handler. */ 2577 FLD (f_r1) = f_r1; 2578 FLD (f_r2) = f_r2; 2579 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2580 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2581 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2582 2583 #if WITH_PROFILE_MODEL_P 2584 /* Record the fields for profiling. */ 2585 if (PROFILE_MODEL_P (current_cpu)) 2586 { 2587 FLD (in_src1) = f_r1; 2588 FLD (in_src2) = f_r2; 2589 } 2590 #endif 2591 #undef FLD 2592 return idesc; 2593 } 2594 2595 extract_sfmt_sc: 2596 { 2597 const IDESC *idesc = &m32rxf_insn_data[itype]; 2598 #define FLD(f) abuf->fields.sfmt_empty.f 2599 2600 2601 /* Record the fields for the semantic handler. */ 2602 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sc", (char *) 0)); 2603 2604 #undef FLD 2605 return idesc; 2606 } 2607 2608 extract_sfmt_clrpsw: 2609 { 2610 const IDESC *idesc = &m32rxf_insn_data[itype]; 2611 CGEN_INSN_WORD insn = entire_insn; 2612 #define FLD(f) abuf->fields.sfmt_clrpsw.f 2613 UINT f_uimm8; 2614 2615 f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); 2616 2617 /* Record the fields for the semantic handler. */ 2618 FLD (f_uimm8) = f_uimm8; 2619 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0)); 2620 2621 #undef FLD 2622 return idesc; 2623 } 2624 2625 extract_sfmt_setpsw: 2626 { 2627 const IDESC *idesc = &m32rxf_insn_data[itype]; 2628 CGEN_INSN_WORD insn = entire_insn; 2629 #define FLD(f) abuf->fields.sfmt_clrpsw.f 2630 UINT f_uimm8; 2631 2632 f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); 2633 2634 /* Record the fields for the semantic handler. */ 2635 FLD (f_uimm8) = f_uimm8; 2636 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_setpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0)); 2637 2638 #undef FLD 2639 return idesc; 2640 } 2641 2642 extract_sfmt_bset: 2643 { 2644 const IDESC *idesc = &m32rxf_insn_data[itype]; 2645 CGEN_INSN_WORD insn = entire_insn; 2646 #define FLD(f) abuf->fields.sfmt_bset.f 2647 UINT f_uimm3; 2648 UINT f_r2; 2649 INT f_simm16; 2650 2651 f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); 2652 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 2653 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 2654 2655 /* Record the fields for the semantic handler. */ 2656 FLD (f_simm16) = f_simm16; 2657 FLD (f_r2) = f_r2; 2658 FLD (f_uimm3) = f_uimm3; 2659 FLD (i_sr) = & CPU (h_gr)[f_r2]; 2660 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bset", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0)); 2661 2662 #if WITH_PROFILE_MODEL_P 2663 /* Record the fields for profiling. */ 2664 if (PROFILE_MODEL_P (current_cpu)) 2665 { 2666 FLD (in_sr) = f_r2; 2667 } 2668 #endif 2669 #undef FLD 2670 return idesc; 2671 } 2672 2673 extract_sfmt_btst: 2674 { 2675 const IDESC *idesc = &m32rxf_insn_data[itype]; 2676 CGEN_INSN_WORD insn = entire_insn; 2677 #define FLD(f) abuf->fields.sfmt_bset.f 2678 UINT f_uimm3; 2679 UINT f_r2; 2680 2681 f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); 2682 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2683 2684 /* Record the fields for the semantic handler. */ 2685 FLD (f_r2) = f_r2; 2686 FLD (f_uimm3) = f_uimm3; 2687 FLD (i_sr) = & CPU (h_gr)[f_r2]; 2688 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btst", "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0)); 2689 2690 #if WITH_PROFILE_MODEL_P 2691 /* Record the fields for profiling. */ 2692 if (PROFILE_MODEL_P (current_cpu)) 2693 { 2694 FLD (in_sr) = f_r2; 2695 } 2696 #endif 2697 #undef FLD 2698 return idesc; 2699 } 2700 2701 } 2702