1 /* Simulator instruction decoder for m32rbf. 2 3 THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5 Copyright 1996-2013 Free Software Foundation, Inc. 6 7 This file is part of the GNU simulators. 8 9 This file is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License along 20 with this program; if not, see <http://www.gnu.org/licenses/>. 21 22 */ 23 24 #define WANT_CPU m32rbf 25 #define WANT_CPU_M32RBF 26 27 #include "sim-main.h" 28 #include "sim-assert.h" 29 30 /* The instruction descriptor array. 31 This is computed at runtime. Space for it is not malloc'd to save a 32 teensy bit of cpu in the decoder. Moving it to malloc space is trivial 33 but won't be done until necessary (we don't currently support the runtime 34 addition of instructions nor an SMP machine with different cpus). */ 35 static IDESC m32rbf_insn_data[M32RBF_INSN__MAX]; 36 37 /* Commas between elements are contained in the macros. 38 Some of these are conditionally compiled out. */ 39 40 static const struct insn_sem m32rbf_insn_sem[] = 41 { 42 { VIRTUAL_INSN_X_INVALID, M32RBF_INSN_X_INVALID, M32RBF_SFMT_EMPTY }, 43 { VIRTUAL_INSN_X_AFTER, M32RBF_INSN_X_AFTER, M32RBF_SFMT_EMPTY }, 44 { VIRTUAL_INSN_X_BEFORE, M32RBF_INSN_X_BEFORE, M32RBF_SFMT_EMPTY }, 45 { VIRTUAL_INSN_X_CTI_CHAIN, M32RBF_INSN_X_CTI_CHAIN, M32RBF_SFMT_EMPTY }, 46 { VIRTUAL_INSN_X_CHAIN, M32RBF_INSN_X_CHAIN, M32RBF_SFMT_EMPTY }, 47 { VIRTUAL_INSN_X_BEGIN, M32RBF_INSN_X_BEGIN, M32RBF_SFMT_EMPTY }, 48 { M32R_INSN_ADD, M32RBF_INSN_ADD, M32RBF_SFMT_ADD }, 49 { M32R_INSN_ADD3, M32RBF_INSN_ADD3, M32RBF_SFMT_ADD3 }, 50 { M32R_INSN_AND, M32RBF_INSN_AND, M32RBF_SFMT_ADD }, 51 { M32R_INSN_AND3, M32RBF_INSN_AND3, M32RBF_SFMT_AND3 }, 52 { M32R_INSN_OR, M32RBF_INSN_OR, M32RBF_SFMT_ADD }, 53 { M32R_INSN_OR3, M32RBF_INSN_OR3, M32RBF_SFMT_OR3 }, 54 { M32R_INSN_XOR, M32RBF_INSN_XOR, M32RBF_SFMT_ADD }, 55 { M32R_INSN_XOR3, M32RBF_INSN_XOR3, M32RBF_SFMT_AND3 }, 56 { M32R_INSN_ADDI, M32RBF_INSN_ADDI, M32RBF_SFMT_ADDI }, 57 { M32R_INSN_ADDV, M32RBF_INSN_ADDV, M32RBF_SFMT_ADDV }, 58 { M32R_INSN_ADDV3, M32RBF_INSN_ADDV3, M32RBF_SFMT_ADDV3 }, 59 { M32R_INSN_ADDX, M32RBF_INSN_ADDX, M32RBF_SFMT_ADDX }, 60 { M32R_INSN_BC8, M32RBF_INSN_BC8, M32RBF_SFMT_BC8 }, 61 { M32R_INSN_BC24, M32RBF_INSN_BC24, M32RBF_SFMT_BC24 }, 62 { M32R_INSN_BEQ, M32RBF_INSN_BEQ, M32RBF_SFMT_BEQ }, 63 { M32R_INSN_BEQZ, M32RBF_INSN_BEQZ, M32RBF_SFMT_BEQZ }, 64 { M32R_INSN_BGEZ, M32RBF_INSN_BGEZ, M32RBF_SFMT_BEQZ }, 65 { M32R_INSN_BGTZ, M32RBF_INSN_BGTZ, M32RBF_SFMT_BEQZ }, 66 { M32R_INSN_BLEZ, M32RBF_INSN_BLEZ, M32RBF_SFMT_BEQZ }, 67 { M32R_INSN_BLTZ, M32RBF_INSN_BLTZ, M32RBF_SFMT_BEQZ }, 68 { M32R_INSN_BNEZ, M32RBF_INSN_BNEZ, M32RBF_SFMT_BEQZ }, 69 { M32R_INSN_BL8, M32RBF_INSN_BL8, M32RBF_SFMT_BL8 }, 70 { M32R_INSN_BL24, M32RBF_INSN_BL24, M32RBF_SFMT_BL24 }, 71 { M32R_INSN_BNC8, M32RBF_INSN_BNC8, M32RBF_SFMT_BC8 }, 72 { M32R_INSN_BNC24, M32RBF_INSN_BNC24, M32RBF_SFMT_BC24 }, 73 { M32R_INSN_BNE, M32RBF_INSN_BNE, M32RBF_SFMT_BEQ }, 74 { M32R_INSN_BRA8, M32RBF_INSN_BRA8, M32RBF_SFMT_BRA8 }, 75 { M32R_INSN_BRA24, M32RBF_INSN_BRA24, M32RBF_SFMT_BRA24 }, 76 { M32R_INSN_CMP, M32RBF_INSN_CMP, M32RBF_SFMT_CMP }, 77 { M32R_INSN_CMPI, M32RBF_INSN_CMPI, M32RBF_SFMT_CMPI }, 78 { M32R_INSN_CMPU, M32RBF_INSN_CMPU, M32RBF_SFMT_CMP }, 79 { M32R_INSN_CMPUI, M32RBF_INSN_CMPUI, M32RBF_SFMT_CMPI }, 80 { M32R_INSN_DIV, M32RBF_INSN_DIV, M32RBF_SFMT_DIV }, 81 { M32R_INSN_DIVU, M32RBF_INSN_DIVU, M32RBF_SFMT_DIV }, 82 { M32R_INSN_REM, M32RBF_INSN_REM, M32RBF_SFMT_DIV }, 83 { M32R_INSN_REMU, M32RBF_INSN_REMU, M32RBF_SFMT_DIV }, 84 { M32R_INSN_JL, M32RBF_INSN_JL, M32RBF_SFMT_JL }, 85 { M32R_INSN_JMP, M32RBF_INSN_JMP, M32RBF_SFMT_JMP }, 86 { M32R_INSN_LD, M32RBF_INSN_LD, M32RBF_SFMT_LD }, 87 { M32R_INSN_LD_D, M32RBF_INSN_LD_D, M32RBF_SFMT_LD_D }, 88 { M32R_INSN_LDB, M32RBF_INSN_LDB, M32RBF_SFMT_LDB }, 89 { M32R_INSN_LDB_D, M32RBF_INSN_LDB_D, M32RBF_SFMT_LDB_D }, 90 { M32R_INSN_LDH, M32RBF_INSN_LDH, M32RBF_SFMT_LDH }, 91 { M32R_INSN_LDH_D, M32RBF_INSN_LDH_D, M32RBF_SFMT_LDH_D }, 92 { M32R_INSN_LDUB, M32RBF_INSN_LDUB, M32RBF_SFMT_LDB }, 93 { M32R_INSN_LDUB_D, M32RBF_INSN_LDUB_D, M32RBF_SFMT_LDB_D }, 94 { M32R_INSN_LDUH, M32RBF_INSN_LDUH, M32RBF_SFMT_LDH }, 95 { M32R_INSN_LDUH_D, M32RBF_INSN_LDUH_D, M32RBF_SFMT_LDH_D }, 96 { M32R_INSN_LD_PLUS, M32RBF_INSN_LD_PLUS, M32RBF_SFMT_LD_PLUS }, 97 { M32R_INSN_LD24, M32RBF_INSN_LD24, M32RBF_SFMT_LD24 }, 98 { M32R_INSN_LDI8, M32RBF_INSN_LDI8, M32RBF_SFMT_LDI8 }, 99 { M32R_INSN_LDI16, M32RBF_INSN_LDI16, M32RBF_SFMT_LDI16 }, 100 { M32R_INSN_LOCK, M32RBF_INSN_LOCK, M32RBF_SFMT_LOCK }, 101 { M32R_INSN_MACHI, M32RBF_INSN_MACHI, M32RBF_SFMT_MACHI }, 102 { M32R_INSN_MACLO, M32RBF_INSN_MACLO, M32RBF_SFMT_MACHI }, 103 { M32R_INSN_MACWHI, M32RBF_INSN_MACWHI, M32RBF_SFMT_MACHI }, 104 { M32R_INSN_MACWLO, M32RBF_INSN_MACWLO, M32RBF_SFMT_MACHI }, 105 { M32R_INSN_MUL, M32RBF_INSN_MUL, M32RBF_SFMT_ADD }, 106 { M32R_INSN_MULHI, M32RBF_INSN_MULHI, M32RBF_SFMT_MULHI }, 107 { M32R_INSN_MULLO, M32RBF_INSN_MULLO, M32RBF_SFMT_MULHI }, 108 { M32R_INSN_MULWHI, M32RBF_INSN_MULWHI, M32RBF_SFMT_MULHI }, 109 { M32R_INSN_MULWLO, M32RBF_INSN_MULWLO, M32RBF_SFMT_MULHI }, 110 { M32R_INSN_MV, M32RBF_INSN_MV, M32RBF_SFMT_MV }, 111 { M32R_INSN_MVFACHI, M32RBF_INSN_MVFACHI, M32RBF_SFMT_MVFACHI }, 112 { M32R_INSN_MVFACLO, M32RBF_INSN_MVFACLO, M32RBF_SFMT_MVFACHI }, 113 { M32R_INSN_MVFACMI, M32RBF_INSN_MVFACMI, M32RBF_SFMT_MVFACHI }, 114 { M32R_INSN_MVFC, M32RBF_INSN_MVFC, M32RBF_SFMT_MVFC }, 115 { M32R_INSN_MVTACHI, M32RBF_INSN_MVTACHI, M32RBF_SFMT_MVTACHI }, 116 { M32R_INSN_MVTACLO, M32RBF_INSN_MVTACLO, M32RBF_SFMT_MVTACHI }, 117 { M32R_INSN_MVTC, M32RBF_INSN_MVTC, M32RBF_SFMT_MVTC }, 118 { M32R_INSN_NEG, M32RBF_INSN_NEG, M32RBF_SFMT_MV }, 119 { M32R_INSN_NOP, M32RBF_INSN_NOP, M32RBF_SFMT_NOP }, 120 { M32R_INSN_NOT, M32RBF_INSN_NOT, M32RBF_SFMT_MV }, 121 { M32R_INSN_RAC, M32RBF_INSN_RAC, M32RBF_SFMT_RAC }, 122 { M32R_INSN_RACH, M32RBF_INSN_RACH, M32RBF_SFMT_RAC }, 123 { M32R_INSN_RTE, M32RBF_INSN_RTE, M32RBF_SFMT_RTE }, 124 { M32R_INSN_SETH, M32RBF_INSN_SETH, M32RBF_SFMT_SETH }, 125 { M32R_INSN_SLL, M32RBF_INSN_SLL, M32RBF_SFMT_ADD }, 126 { M32R_INSN_SLL3, M32RBF_INSN_SLL3, M32RBF_SFMT_SLL3 }, 127 { M32R_INSN_SLLI, M32RBF_INSN_SLLI, M32RBF_SFMT_SLLI }, 128 { M32R_INSN_SRA, M32RBF_INSN_SRA, M32RBF_SFMT_ADD }, 129 { M32R_INSN_SRA3, M32RBF_INSN_SRA3, M32RBF_SFMT_SLL3 }, 130 { M32R_INSN_SRAI, M32RBF_INSN_SRAI, M32RBF_SFMT_SLLI }, 131 { M32R_INSN_SRL, M32RBF_INSN_SRL, M32RBF_SFMT_ADD }, 132 { M32R_INSN_SRL3, M32RBF_INSN_SRL3, M32RBF_SFMT_SLL3 }, 133 { M32R_INSN_SRLI, M32RBF_INSN_SRLI, M32RBF_SFMT_SLLI }, 134 { M32R_INSN_ST, M32RBF_INSN_ST, M32RBF_SFMT_ST }, 135 { M32R_INSN_ST_D, M32RBF_INSN_ST_D, M32RBF_SFMT_ST_D }, 136 { M32R_INSN_STB, M32RBF_INSN_STB, M32RBF_SFMT_STB }, 137 { M32R_INSN_STB_D, M32RBF_INSN_STB_D, M32RBF_SFMT_STB_D }, 138 { M32R_INSN_STH, M32RBF_INSN_STH, M32RBF_SFMT_STH }, 139 { M32R_INSN_STH_D, M32RBF_INSN_STH_D, M32RBF_SFMT_STH_D }, 140 { M32R_INSN_ST_PLUS, M32RBF_INSN_ST_PLUS, M32RBF_SFMT_ST_PLUS }, 141 { M32R_INSN_ST_MINUS, M32RBF_INSN_ST_MINUS, M32RBF_SFMT_ST_PLUS }, 142 { M32R_INSN_SUB, M32RBF_INSN_SUB, M32RBF_SFMT_ADD }, 143 { M32R_INSN_SUBV, M32RBF_INSN_SUBV, M32RBF_SFMT_ADDV }, 144 { M32R_INSN_SUBX, M32RBF_INSN_SUBX, M32RBF_SFMT_ADDX }, 145 { M32R_INSN_TRAP, M32RBF_INSN_TRAP, M32RBF_SFMT_TRAP }, 146 { M32R_INSN_UNLOCK, M32RBF_INSN_UNLOCK, M32RBF_SFMT_UNLOCK }, 147 { M32R_INSN_CLRPSW, M32RBF_INSN_CLRPSW, M32RBF_SFMT_CLRPSW }, 148 { M32R_INSN_SETPSW, M32RBF_INSN_SETPSW, M32RBF_SFMT_SETPSW }, 149 { M32R_INSN_BSET, M32RBF_INSN_BSET, M32RBF_SFMT_BSET }, 150 { M32R_INSN_BCLR, M32RBF_INSN_BCLR, M32RBF_SFMT_BSET }, 151 { M32R_INSN_BTST, M32RBF_INSN_BTST, M32RBF_SFMT_BTST }, 152 }; 153 154 static const struct insn_sem m32rbf_insn_sem_invalid = 155 { 156 VIRTUAL_INSN_X_INVALID, M32RBF_INSN_X_INVALID, M32RBF_SFMT_EMPTY 157 }; 158 159 /* Initialize an IDESC from the compile-time computable parts. */ 160 161 static INLINE void 162 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) 163 { 164 const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries; 165 166 id->num = t->index; 167 id->sfmt = t->sfmt; 168 if ((int) t->type <= 0) 169 id->idata = & cgen_virtual_insn_table[- (int) t->type]; 170 else 171 id->idata = & insn_table[t->type]; 172 id->attrs = CGEN_INSN_ATTRS (id->idata); 173 /* Oh my god, a magic number. */ 174 id->length = CGEN_INSN_BITSIZE (id->idata) / 8; 175 176 #if WITH_PROFILE_MODEL_P 177 id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index]; 178 { 179 SIM_DESC sd = CPU_STATE (cpu); 180 SIM_ASSERT (t->index == id->timing->num); 181 } 182 #endif 183 184 /* Semantic pointers are initialized elsewhere. */ 185 } 186 187 /* Initialize the instruction descriptor table. */ 188 189 void 190 m32rbf_init_idesc_table (SIM_CPU *cpu) 191 { 192 IDESC *id,*tabend; 193 const struct insn_sem *t,*tend; 194 int tabsize = M32RBF_INSN__MAX; 195 IDESC *table = m32rbf_insn_data; 196 197 memset (table, 0, tabsize * sizeof (IDESC)); 198 199 /* First set all entries to the `invalid insn'. */ 200 t = & m32rbf_insn_sem_invalid; 201 for (id = table, tabend = table + tabsize; id < tabend; ++id) 202 init_idesc (cpu, id, t); 203 204 /* Now fill in the values for the chosen cpu. */ 205 for (t = m32rbf_insn_sem, tend = t + sizeof (m32rbf_insn_sem) / sizeof (*t); 206 t != tend; ++t) 207 { 208 init_idesc (cpu, & table[t->index], t); 209 } 210 211 /* Link the IDESC table into the cpu. */ 212 CPU_IDESC (cpu) = table; 213 } 214 215 /* Given an instruction, return a pointer to its IDESC entry. */ 216 217 const IDESC * 218 m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, 219 CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn, 220 ARGBUF *abuf) 221 { 222 /* Result of decoder. */ 223 M32RBF_INSN_TYPE itype; 224 225 { 226 CGEN_INSN_WORD insn = base_insn; 227 228 { 229 unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0))); 230 switch (val) 231 { 232 case 0 : itype = M32RBF_INSN_SUBV; goto extract_sfmt_addv; 233 case 1 : itype = M32RBF_INSN_SUBX; goto extract_sfmt_addx; 234 case 2 : itype = M32RBF_INSN_SUB; goto extract_sfmt_add; 235 case 3 : itype = M32RBF_INSN_NEG; goto extract_sfmt_mv; 236 case 4 : itype = M32RBF_INSN_CMP; goto extract_sfmt_cmp; 237 case 5 : itype = M32RBF_INSN_CMPU; goto extract_sfmt_cmp; 238 case 8 : itype = M32RBF_INSN_ADDV; goto extract_sfmt_addv; 239 case 9 : itype = M32RBF_INSN_ADDX; goto extract_sfmt_addx; 240 case 10 : itype = M32RBF_INSN_ADD; goto extract_sfmt_add; 241 case 11 : itype = M32RBF_INSN_NOT; goto extract_sfmt_mv; 242 case 12 : itype = M32RBF_INSN_AND; goto extract_sfmt_add; 243 case 13 : itype = M32RBF_INSN_XOR; goto extract_sfmt_add; 244 case 14 : itype = M32RBF_INSN_OR; goto extract_sfmt_add; 245 case 15 : 246 if ((entire_insn & 0xf8f0) == 0xf0) 247 { itype = M32RBF_INSN_BTST; goto extract_sfmt_btst; } 248 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 249 case 16 : itype = M32RBF_INSN_SRL; goto extract_sfmt_add; 250 case 18 : itype = M32RBF_INSN_SRA; goto extract_sfmt_add; 251 case 20 : itype = M32RBF_INSN_SLL; goto extract_sfmt_add; 252 case 22 : itype = M32RBF_INSN_MUL; goto extract_sfmt_add; 253 case 24 : itype = M32RBF_INSN_MV; goto extract_sfmt_mv; 254 case 25 : itype = M32RBF_INSN_MVFC; goto extract_sfmt_mvfc; 255 case 26 : itype = M32RBF_INSN_MVTC; goto extract_sfmt_mvtc; 256 case 28 : 257 { 258 unsigned int val = (((insn >> 8) & (1 << 0))); 259 switch (val) 260 { 261 case 0 : 262 if ((entire_insn & 0xfff0) == 0x1ec0) 263 { itype = M32RBF_INSN_JL; goto extract_sfmt_jl; } 264 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 265 case 1 : 266 if ((entire_insn & 0xfff0) == 0x1fc0) 267 { itype = M32RBF_INSN_JMP; goto extract_sfmt_jmp; } 268 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 269 default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 270 } 271 } 272 case 29 : 273 if ((entire_insn & 0xffff) == 0x10d6) 274 { itype = M32RBF_INSN_RTE; goto extract_sfmt_rte; } 275 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 276 case 31 : 277 if ((entire_insn & 0xfff0) == 0x10f0) 278 { itype = M32RBF_INSN_TRAP; goto extract_sfmt_trap; } 279 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 280 case 32 : itype = M32RBF_INSN_STB; goto extract_sfmt_stb; 281 case 34 : itype = M32RBF_INSN_STH; goto extract_sfmt_sth; 282 case 36 : itype = M32RBF_INSN_ST; goto extract_sfmt_st; 283 case 37 : itype = M32RBF_INSN_UNLOCK; goto extract_sfmt_unlock; 284 case 38 : itype = M32RBF_INSN_ST_PLUS; goto extract_sfmt_st_plus; 285 case 39 : itype = M32RBF_INSN_ST_MINUS; goto extract_sfmt_st_plus; 286 case 40 : itype = M32RBF_INSN_LDB; goto extract_sfmt_ldb; 287 case 41 : itype = M32RBF_INSN_LDUB; goto extract_sfmt_ldb; 288 case 42 : itype = M32RBF_INSN_LDH; goto extract_sfmt_ldh; 289 case 43 : itype = M32RBF_INSN_LDUH; goto extract_sfmt_ldh; 290 case 44 : itype = M32RBF_INSN_LD; goto extract_sfmt_ld; 291 case 45 : itype = M32RBF_INSN_LOCK; goto extract_sfmt_lock; 292 case 46 : itype = M32RBF_INSN_LD_PLUS; goto extract_sfmt_ld_plus; 293 case 48 : itype = M32RBF_INSN_MULHI; goto extract_sfmt_mulhi; 294 case 49 : itype = M32RBF_INSN_MULLO; goto extract_sfmt_mulhi; 295 case 50 : itype = M32RBF_INSN_MULWHI; goto extract_sfmt_mulhi; 296 case 51 : itype = M32RBF_INSN_MULWLO; goto extract_sfmt_mulhi; 297 case 52 : itype = M32RBF_INSN_MACHI; goto extract_sfmt_machi; 298 case 53 : itype = M32RBF_INSN_MACLO; goto extract_sfmt_machi; 299 case 54 : itype = M32RBF_INSN_MACWHI; goto extract_sfmt_machi; 300 case 55 : itype = M32RBF_INSN_MACWLO; goto extract_sfmt_machi; 301 case 64 : /* fall through */ 302 case 65 : /* fall through */ 303 case 66 : /* fall through */ 304 case 67 : /* fall through */ 305 case 68 : /* fall through */ 306 case 69 : /* fall through */ 307 case 70 : /* fall through */ 308 case 71 : /* fall through */ 309 case 72 : /* fall through */ 310 case 73 : /* fall through */ 311 case 74 : /* fall through */ 312 case 75 : /* fall through */ 313 case 76 : /* fall through */ 314 case 77 : /* fall through */ 315 case 78 : /* fall through */ 316 case 79 : itype = M32RBF_INSN_ADDI; goto extract_sfmt_addi; 317 case 80 : /* fall through */ 318 case 81 : itype = M32RBF_INSN_SRLI; goto extract_sfmt_slli; 319 case 82 : /* fall through */ 320 case 83 : itype = M32RBF_INSN_SRAI; goto extract_sfmt_slli; 321 case 84 : /* fall through */ 322 case 85 : itype = M32RBF_INSN_SLLI; goto extract_sfmt_slli; 323 case 87 : 324 { 325 unsigned int val = (((insn >> 0) & (1 << 0))); 326 switch (val) 327 { 328 case 0 : 329 if ((entire_insn & 0xf0ff) == 0x5070) 330 { itype = M32RBF_INSN_MVTACHI; goto extract_sfmt_mvtachi; } 331 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 332 case 1 : 333 if ((entire_insn & 0xf0ff) == 0x5071) 334 { itype = M32RBF_INSN_MVTACLO; goto extract_sfmt_mvtachi; } 335 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 336 default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 337 } 338 } 339 case 88 : 340 if ((entire_insn & 0xffff) == 0x5080) 341 { itype = M32RBF_INSN_RACH; goto extract_sfmt_rac; } 342 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 343 case 89 : 344 if ((entire_insn & 0xffff) == 0x5090) 345 { itype = M32RBF_INSN_RAC; goto extract_sfmt_rac; } 346 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 347 case 95 : 348 { 349 unsigned int val = (((insn >> 0) & (3 << 0))); 350 switch (val) 351 { 352 case 0 : 353 if ((entire_insn & 0xf0ff) == 0x50f0) 354 { itype = M32RBF_INSN_MVFACHI; goto extract_sfmt_mvfachi; } 355 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 356 case 1 : 357 if ((entire_insn & 0xf0ff) == 0x50f1) 358 { itype = M32RBF_INSN_MVFACLO; goto extract_sfmt_mvfachi; } 359 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 360 case 2 : 361 if ((entire_insn & 0xf0ff) == 0x50f2) 362 { itype = M32RBF_INSN_MVFACMI; goto extract_sfmt_mvfachi; } 363 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 364 default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 365 } 366 } 367 case 96 : /* fall through */ 368 case 97 : /* fall through */ 369 case 98 : /* fall through */ 370 case 99 : /* fall through */ 371 case 100 : /* fall through */ 372 case 101 : /* fall through */ 373 case 102 : /* fall through */ 374 case 103 : /* fall through */ 375 case 104 : /* fall through */ 376 case 105 : /* fall through */ 377 case 106 : /* fall through */ 378 case 107 : /* fall through */ 379 case 108 : /* fall through */ 380 case 109 : /* fall through */ 381 case 110 : /* fall through */ 382 case 111 : itype = M32RBF_INSN_LDI8; goto extract_sfmt_ldi8; 383 case 112 : 384 { 385 unsigned int val = (((insn >> 8) & (15 << 0))); 386 switch (val) 387 { 388 case 0 : 389 if ((entire_insn & 0xffff) == 0x7000) 390 { itype = M32RBF_INSN_NOP; goto extract_sfmt_nop; } 391 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 392 case 1 : itype = M32RBF_INSN_SETPSW; goto extract_sfmt_setpsw; 393 case 2 : itype = M32RBF_INSN_CLRPSW; goto extract_sfmt_clrpsw; 394 case 12 : itype = M32RBF_INSN_BC8; goto extract_sfmt_bc8; 395 case 13 : itype = M32RBF_INSN_BNC8; goto extract_sfmt_bc8; 396 case 14 : itype = M32RBF_INSN_BL8; goto extract_sfmt_bl8; 397 case 15 : itype = M32RBF_INSN_BRA8; goto extract_sfmt_bra8; 398 default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 399 } 400 } 401 case 113 : /* fall through */ 402 case 114 : /* fall through */ 403 case 115 : /* fall through */ 404 case 116 : /* fall through */ 405 case 117 : /* fall through */ 406 case 118 : /* fall through */ 407 case 119 : /* fall through */ 408 case 120 : /* fall through */ 409 case 121 : /* fall through */ 410 case 122 : /* fall through */ 411 case 123 : /* fall through */ 412 case 124 : /* fall through */ 413 case 125 : /* fall through */ 414 case 126 : /* fall through */ 415 case 127 : 416 { 417 unsigned int val = (((insn >> 8) & (15 << 0))); 418 switch (val) 419 { 420 case 1 : itype = M32RBF_INSN_SETPSW; goto extract_sfmt_setpsw; 421 case 2 : itype = M32RBF_INSN_CLRPSW; goto extract_sfmt_clrpsw; 422 case 12 : itype = M32RBF_INSN_BC8; goto extract_sfmt_bc8; 423 case 13 : itype = M32RBF_INSN_BNC8; goto extract_sfmt_bc8; 424 case 14 : itype = M32RBF_INSN_BL8; goto extract_sfmt_bl8; 425 case 15 : itype = M32RBF_INSN_BRA8; goto extract_sfmt_bra8; 426 default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 427 } 428 } 429 case 132 : 430 if ((entire_insn & 0xfff00000) == 0x80400000) 431 { itype = M32RBF_INSN_CMPI; goto extract_sfmt_cmpi; } 432 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 433 case 133 : 434 if ((entire_insn & 0xfff00000) == 0x80500000) 435 { itype = M32RBF_INSN_CMPUI; goto extract_sfmt_cmpi; } 436 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 437 case 136 : itype = M32RBF_INSN_ADDV3; goto extract_sfmt_addv3; 438 case 138 : itype = M32RBF_INSN_ADD3; goto extract_sfmt_add3; 439 case 140 : itype = M32RBF_INSN_AND3; goto extract_sfmt_and3; 440 case 141 : itype = M32RBF_INSN_XOR3; goto extract_sfmt_and3; 441 case 142 : itype = M32RBF_INSN_OR3; goto extract_sfmt_or3; 442 case 144 : 443 if ((entire_insn & 0xf0f0ffff) == 0x90000000) 444 { itype = M32RBF_INSN_DIV; goto extract_sfmt_div; } 445 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 446 case 145 : 447 if ((entire_insn & 0xf0f0ffff) == 0x90100000) 448 { itype = M32RBF_INSN_DIVU; goto extract_sfmt_div; } 449 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 450 case 146 : 451 if ((entire_insn & 0xf0f0ffff) == 0x90200000) 452 { itype = M32RBF_INSN_REM; goto extract_sfmt_div; } 453 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 454 case 147 : 455 if ((entire_insn & 0xf0f0ffff) == 0x90300000) 456 { itype = M32RBF_INSN_REMU; goto extract_sfmt_div; } 457 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 458 case 152 : itype = M32RBF_INSN_SRL3; goto extract_sfmt_sll3; 459 case 154 : itype = M32RBF_INSN_SRA3; goto extract_sfmt_sll3; 460 case 156 : itype = M32RBF_INSN_SLL3; goto extract_sfmt_sll3; 461 case 159 : 462 if ((entire_insn & 0xf0ff0000) == 0x90f00000) 463 { itype = M32RBF_INSN_LDI16; goto extract_sfmt_ldi16; } 464 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 465 case 160 : itype = M32RBF_INSN_STB_D; goto extract_sfmt_stb_d; 466 case 162 : itype = M32RBF_INSN_STH_D; goto extract_sfmt_sth_d; 467 case 164 : itype = M32RBF_INSN_ST_D; goto extract_sfmt_st_d; 468 case 166 : 469 if ((entire_insn & 0xf8f00000) == 0xa0600000) 470 { itype = M32RBF_INSN_BSET; goto extract_sfmt_bset; } 471 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 472 case 167 : 473 if ((entire_insn & 0xf8f00000) == 0xa0700000) 474 { itype = M32RBF_INSN_BCLR; goto extract_sfmt_bset; } 475 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 476 case 168 : itype = M32RBF_INSN_LDB_D; goto extract_sfmt_ldb_d; 477 case 169 : itype = M32RBF_INSN_LDUB_D; goto extract_sfmt_ldb_d; 478 case 170 : itype = M32RBF_INSN_LDH_D; goto extract_sfmt_ldh_d; 479 case 171 : itype = M32RBF_INSN_LDUH_D; goto extract_sfmt_ldh_d; 480 case 172 : itype = M32RBF_INSN_LD_D; goto extract_sfmt_ld_d; 481 case 176 : itype = M32RBF_INSN_BEQ; goto extract_sfmt_beq; 482 case 177 : itype = M32RBF_INSN_BNE; goto extract_sfmt_beq; 483 case 184 : 484 if ((entire_insn & 0xfff00000) == 0xb0800000) 485 { itype = M32RBF_INSN_BEQZ; goto extract_sfmt_beqz; } 486 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 487 case 185 : 488 if ((entire_insn & 0xfff00000) == 0xb0900000) 489 { itype = M32RBF_INSN_BNEZ; goto extract_sfmt_beqz; } 490 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 491 case 186 : 492 if ((entire_insn & 0xfff00000) == 0xb0a00000) 493 { itype = M32RBF_INSN_BLTZ; goto extract_sfmt_beqz; } 494 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 495 case 187 : 496 if ((entire_insn & 0xfff00000) == 0xb0b00000) 497 { itype = M32RBF_INSN_BGEZ; goto extract_sfmt_beqz; } 498 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 499 case 188 : 500 if ((entire_insn & 0xfff00000) == 0xb0c00000) 501 { itype = M32RBF_INSN_BLEZ; goto extract_sfmt_beqz; } 502 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 503 case 189 : 504 if ((entire_insn & 0xfff00000) == 0xb0d00000) 505 { itype = M32RBF_INSN_BGTZ; goto extract_sfmt_beqz; } 506 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 507 case 220 : 508 if ((entire_insn & 0xf0ff0000) == 0xd0c00000) 509 { itype = M32RBF_INSN_SETH; goto extract_sfmt_seth; } 510 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 511 case 224 : /* fall through */ 512 case 225 : /* fall through */ 513 case 226 : /* fall through */ 514 case 227 : /* fall through */ 515 case 228 : /* fall through */ 516 case 229 : /* fall through */ 517 case 230 : /* fall through */ 518 case 231 : /* fall through */ 519 case 232 : /* fall through */ 520 case 233 : /* fall through */ 521 case 234 : /* fall through */ 522 case 235 : /* fall through */ 523 case 236 : /* fall through */ 524 case 237 : /* fall through */ 525 case 238 : /* fall through */ 526 case 239 : itype = M32RBF_INSN_LD24; goto extract_sfmt_ld24; 527 case 240 : /* fall through */ 528 case 241 : /* fall through */ 529 case 242 : /* fall through */ 530 case 243 : /* fall through */ 531 case 244 : /* fall through */ 532 case 245 : /* fall through */ 533 case 246 : /* fall through */ 534 case 247 : /* fall through */ 535 case 248 : /* fall through */ 536 case 249 : /* fall through */ 537 case 250 : /* fall through */ 538 case 251 : /* fall through */ 539 case 252 : /* fall through */ 540 case 253 : /* fall through */ 541 case 254 : /* fall through */ 542 case 255 : 543 { 544 unsigned int val = (((insn >> 8) & (3 << 0))); 545 switch (val) 546 { 547 case 0 : 548 if ((entire_insn & 0xff000000) == 0xfc000000) 549 { itype = M32RBF_INSN_BC24; goto extract_sfmt_bc24; } 550 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 551 case 1 : 552 if ((entire_insn & 0xff000000) == 0xfd000000) 553 { itype = M32RBF_INSN_BNC24; goto extract_sfmt_bc24; } 554 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 555 case 2 : 556 if ((entire_insn & 0xff000000) == 0xfe000000) 557 { itype = M32RBF_INSN_BL24; goto extract_sfmt_bl24; } 558 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 559 case 3 : 560 if ((entire_insn & 0xff000000) == 0xff000000) 561 { itype = M32RBF_INSN_BRA24; goto extract_sfmt_bra24; } 562 itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 563 default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 564 } 565 } 566 default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; 567 } 568 } 569 } 570 571 /* The instruction has been decoded, now extract the fields. */ 572 573 extract_sfmt_empty: 574 { 575 const IDESC *idesc = &m32rbf_insn_data[itype]; 576 #define FLD(f) abuf->fields.sfmt_empty.f 577 578 579 /* Record the fields for the semantic handler. */ 580 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0)); 581 582 #undef FLD 583 return idesc; 584 } 585 586 extract_sfmt_add: 587 { 588 const IDESC *idesc = &m32rbf_insn_data[itype]; 589 CGEN_INSN_WORD insn = entire_insn; 590 #define FLD(f) abuf->fields.sfmt_add.f 591 UINT f_r1; 592 UINT f_r2; 593 594 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 595 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 596 597 /* Record the fields for the semantic handler. */ 598 FLD (f_r1) = f_r1; 599 FLD (f_r2) = f_r2; 600 FLD (i_dr) = & CPU (h_gr)[f_r1]; 601 FLD (i_sr) = & CPU (h_gr)[f_r2]; 602 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); 603 604 #if WITH_PROFILE_MODEL_P 605 /* Record the fields for profiling. */ 606 if (PROFILE_MODEL_P (current_cpu)) 607 { 608 FLD (in_dr) = f_r1; 609 FLD (in_sr) = f_r2; 610 FLD (out_dr) = f_r1; 611 } 612 #endif 613 #undef FLD 614 return idesc; 615 } 616 617 extract_sfmt_add3: 618 { 619 const IDESC *idesc = &m32rbf_insn_data[itype]; 620 CGEN_INSN_WORD insn = entire_insn; 621 #define FLD(f) abuf->fields.sfmt_add3.f 622 UINT f_r1; 623 UINT f_r2; 624 INT f_simm16; 625 626 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 627 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 628 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 629 630 /* Record the fields for the semantic handler. */ 631 FLD (f_simm16) = f_simm16; 632 FLD (f_r2) = f_r2; 633 FLD (f_r1) = f_r1; 634 FLD (i_sr) = & CPU (h_gr)[f_r2]; 635 FLD (i_dr) = & CPU (h_gr)[f_r1]; 636 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 637 638 #if WITH_PROFILE_MODEL_P 639 /* Record the fields for profiling. */ 640 if (PROFILE_MODEL_P (current_cpu)) 641 { 642 FLD (in_sr) = f_r2; 643 FLD (out_dr) = f_r1; 644 } 645 #endif 646 #undef FLD 647 return idesc; 648 } 649 650 extract_sfmt_and3: 651 { 652 const IDESC *idesc = &m32rbf_insn_data[itype]; 653 CGEN_INSN_WORD insn = entire_insn; 654 #define FLD(f) abuf->fields.sfmt_and3.f 655 UINT f_r1; 656 UINT f_r2; 657 UINT f_uimm16; 658 659 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 660 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 661 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); 662 663 /* Record the fields for the semantic handler. */ 664 FLD (f_r2) = f_r2; 665 FLD (f_uimm16) = f_uimm16; 666 FLD (f_r1) = f_r1; 667 FLD (i_sr) = & CPU (h_gr)[f_r2]; 668 FLD (i_dr) = & CPU (h_gr)[f_r1]; 669 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 670 671 #if WITH_PROFILE_MODEL_P 672 /* Record the fields for profiling. */ 673 if (PROFILE_MODEL_P (current_cpu)) 674 { 675 FLD (in_sr) = f_r2; 676 FLD (out_dr) = f_r1; 677 } 678 #endif 679 #undef FLD 680 return idesc; 681 } 682 683 extract_sfmt_or3: 684 { 685 const IDESC *idesc = &m32rbf_insn_data[itype]; 686 CGEN_INSN_WORD insn = entire_insn; 687 #define FLD(f) abuf->fields.sfmt_and3.f 688 UINT f_r1; 689 UINT f_r2; 690 UINT f_uimm16; 691 692 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 693 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 694 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); 695 696 /* Record the fields for the semantic handler. */ 697 FLD (f_r2) = f_r2; 698 FLD (f_uimm16) = f_uimm16; 699 FLD (f_r1) = f_r1; 700 FLD (i_sr) = & CPU (h_gr)[f_r2]; 701 FLD (i_dr) = & CPU (h_gr)[f_r1]; 702 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_or3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 703 704 #if WITH_PROFILE_MODEL_P 705 /* Record the fields for profiling. */ 706 if (PROFILE_MODEL_P (current_cpu)) 707 { 708 FLD (in_sr) = f_r2; 709 FLD (out_dr) = f_r1; 710 } 711 #endif 712 #undef FLD 713 return idesc; 714 } 715 716 extract_sfmt_addi: 717 { 718 const IDESC *idesc = &m32rbf_insn_data[itype]; 719 CGEN_INSN_WORD insn = entire_insn; 720 #define FLD(f) abuf->fields.sfmt_addi.f 721 UINT f_r1; 722 INT f_simm8; 723 724 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 725 f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8); 726 727 /* Record the fields for the semantic handler. */ 728 FLD (f_r1) = f_r1; 729 FLD (f_simm8) = f_simm8; 730 FLD (i_dr) = & CPU (h_gr)[f_r1]; 731 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_r1 0x%x", 'x', f_r1, "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0)); 732 733 #if WITH_PROFILE_MODEL_P 734 /* Record the fields for profiling. */ 735 if (PROFILE_MODEL_P (current_cpu)) 736 { 737 FLD (in_dr) = f_r1; 738 FLD (out_dr) = f_r1; 739 } 740 #endif 741 #undef FLD 742 return idesc; 743 } 744 745 extract_sfmt_addv: 746 { 747 const IDESC *idesc = &m32rbf_insn_data[itype]; 748 CGEN_INSN_WORD insn = entire_insn; 749 #define FLD(f) abuf->fields.sfmt_add.f 750 UINT f_r1; 751 UINT f_r2; 752 753 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 754 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 755 756 /* Record the fields for the semantic handler. */ 757 FLD (f_r1) = f_r1; 758 FLD (f_r2) = f_r2; 759 FLD (i_dr) = & CPU (h_gr)[f_r1]; 760 FLD (i_sr) = & CPU (h_gr)[f_r2]; 761 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); 762 763 #if WITH_PROFILE_MODEL_P 764 /* Record the fields for profiling. */ 765 if (PROFILE_MODEL_P (current_cpu)) 766 { 767 FLD (in_dr) = f_r1; 768 FLD (in_sr) = f_r2; 769 FLD (out_dr) = f_r1; 770 } 771 #endif 772 #undef FLD 773 return idesc; 774 } 775 776 extract_sfmt_addv3: 777 { 778 const IDESC *idesc = &m32rbf_insn_data[itype]; 779 CGEN_INSN_WORD insn = entire_insn; 780 #define FLD(f) abuf->fields.sfmt_add3.f 781 UINT f_r1; 782 UINT f_r2; 783 INT f_simm16; 784 785 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 786 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 787 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 788 789 /* Record the fields for the semantic handler. */ 790 FLD (f_simm16) = f_simm16; 791 FLD (f_r2) = f_r2; 792 FLD (f_r1) = f_r1; 793 FLD (i_sr) = & CPU (h_gr)[f_r2]; 794 FLD (i_dr) = & CPU (h_gr)[f_r1]; 795 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 796 797 #if WITH_PROFILE_MODEL_P 798 /* Record the fields for profiling. */ 799 if (PROFILE_MODEL_P (current_cpu)) 800 { 801 FLD (in_sr) = f_r2; 802 FLD (out_dr) = f_r1; 803 } 804 #endif 805 #undef FLD 806 return idesc; 807 } 808 809 extract_sfmt_addx: 810 { 811 const IDESC *idesc = &m32rbf_insn_data[itype]; 812 CGEN_INSN_WORD insn = entire_insn; 813 #define FLD(f) abuf->fields.sfmt_add.f 814 UINT f_r1; 815 UINT f_r2; 816 817 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 818 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 819 820 /* Record the fields for the semantic handler. */ 821 FLD (f_r1) = f_r1; 822 FLD (f_r2) = f_r2; 823 FLD (i_dr) = & CPU (h_gr)[f_r1]; 824 FLD (i_sr) = & CPU (h_gr)[f_r2]; 825 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); 826 827 #if WITH_PROFILE_MODEL_P 828 /* Record the fields for profiling. */ 829 if (PROFILE_MODEL_P (current_cpu)) 830 { 831 FLD (in_dr) = f_r1; 832 FLD (in_sr) = f_r2; 833 FLD (out_dr) = f_r1; 834 } 835 #endif 836 #undef FLD 837 return idesc; 838 } 839 840 extract_sfmt_bc8: 841 { 842 const IDESC *idesc = &m32rbf_insn_data[itype]; 843 CGEN_INSN_WORD insn = entire_insn; 844 #define FLD(f) abuf->fields.sfmt_bl8.f 845 SI f_disp8; 846 847 f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); 848 849 /* Record the fields for the semantic handler. */ 850 FLD (i_disp8) = f_disp8; 851 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); 852 853 #if WITH_PROFILE_MODEL_P 854 /* Record the fields for profiling. */ 855 if (PROFILE_MODEL_P (current_cpu)) 856 { 857 } 858 #endif 859 #undef FLD 860 return idesc; 861 } 862 863 extract_sfmt_bc24: 864 { 865 const IDESC *idesc = &m32rbf_insn_data[itype]; 866 CGEN_INSN_WORD insn = entire_insn; 867 #define FLD(f) abuf->fields.sfmt_bl24.f 868 SI f_disp24; 869 870 f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); 871 872 /* Record the fields for the semantic handler. */ 873 FLD (i_disp24) = f_disp24; 874 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); 875 876 #if WITH_PROFILE_MODEL_P 877 /* Record the fields for profiling. */ 878 if (PROFILE_MODEL_P (current_cpu)) 879 { 880 } 881 #endif 882 #undef FLD 883 return idesc; 884 } 885 886 extract_sfmt_beq: 887 { 888 const IDESC *idesc = &m32rbf_insn_data[itype]; 889 CGEN_INSN_WORD insn = entire_insn; 890 #define FLD(f) abuf->fields.sfmt_beq.f 891 UINT f_r1; 892 UINT f_r2; 893 SI f_disp16; 894 895 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 896 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 897 f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); 898 899 /* Record the fields for the semantic handler. */ 900 FLD (f_r1) = f_r1; 901 FLD (f_r2) = f_r2; 902 FLD (i_disp16) = f_disp16; 903 FLD (i_src1) = & CPU (h_gr)[f_r1]; 904 FLD (i_src2) = & CPU (h_gr)[f_r2]; 905 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 906 907 #if WITH_PROFILE_MODEL_P 908 /* Record the fields for profiling. */ 909 if (PROFILE_MODEL_P (current_cpu)) 910 { 911 FLD (in_src1) = f_r1; 912 FLD (in_src2) = f_r2; 913 } 914 #endif 915 #undef FLD 916 return idesc; 917 } 918 919 extract_sfmt_beqz: 920 { 921 const IDESC *idesc = &m32rbf_insn_data[itype]; 922 CGEN_INSN_WORD insn = entire_insn; 923 #define FLD(f) abuf->fields.sfmt_beq.f 924 UINT f_r2; 925 SI f_disp16; 926 927 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 928 f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); 929 930 /* Record the fields for the semantic handler. */ 931 FLD (f_r2) = f_r2; 932 FLD (i_disp16) = f_disp16; 933 FLD (i_src2) = & CPU (h_gr)[f_r2]; 934 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqz", "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0)); 935 936 #if WITH_PROFILE_MODEL_P 937 /* Record the fields for profiling. */ 938 if (PROFILE_MODEL_P (current_cpu)) 939 { 940 FLD (in_src2) = f_r2; 941 } 942 #endif 943 #undef FLD 944 return idesc; 945 } 946 947 extract_sfmt_bl8: 948 { 949 const IDESC *idesc = &m32rbf_insn_data[itype]; 950 CGEN_INSN_WORD insn = entire_insn; 951 #define FLD(f) abuf->fields.sfmt_bl8.f 952 SI f_disp8; 953 954 f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); 955 956 /* Record the fields for the semantic handler. */ 957 FLD (i_disp8) = f_disp8; 958 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); 959 960 #if WITH_PROFILE_MODEL_P 961 /* Record the fields for profiling. */ 962 if (PROFILE_MODEL_P (current_cpu)) 963 { 964 FLD (out_h_gr_SI_14) = 14; 965 } 966 #endif 967 #undef FLD 968 return idesc; 969 } 970 971 extract_sfmt_bl24: 972 { 973 const IDESC *idesc = &m32rbf_insn_data[itype]; 974 CGEN_INSN_WORD insn = entire_insn; 975 #define FLD(f) abuf->fields.sfmt_bl24.f 976 SI f_disp24; 977 978 f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); 979 980 /* Record the fields for the semantic handler. */ 981 FLD (i_disp24) = f_disp24; 982 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); 983 984 #if WITH_PROFILE_MODEL_P 985 /* Record the fields for profiling. */ 986 if (PROFILE_MODEL_P (current_cpu)) 987 { 988 FLD (out_h_gr_SI_14) = 14; 989 } 990 #endif 991 #undef FLD 992 return idesc; 993 } 994 995 extract_sfmt_bra8: 996 { 997 const IDESC *idesc = &m32rbf_insn_data[itype]; 998 CGEN_INSN_WORD insn = entire_insn; 999 #define FLD(f) abuf->fields.sfmt_bl8.f 1000 SI f_disp8; 1001 1002 f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); 1003 1004 /* Record the fields for the semantic handler. */ 1005 FLD (i_disp8) = f_disp8; 1006 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); 1007 1008 #if WITH_PROFILE_MODEL_P 1009 /* Record the fields for profiling. */ 1010 if (PROFILE_MODEL_P (current_cpu)) 1011 { 1012 } 1013 #endif 1014 #undef FLD 1015 return idesc; 1016 } 1017 1018 extract_sfmt_bra24: 1019 { 1020 const IDESC *idesc = &m32rbf_insn_data[itype]; 1021 CGEN_INSN_WORD insn = entire_insn; 1022 #define FLD(f) abuf->fields.sfmt_bl24.f 1023 SI f_disp24; 1024 1025 f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); 1026 1027 /* Record the fields for the semantic handler. */ 1028 FLD (i_disp24) = f_disp24; 1029 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); 1030 1031 #if WITH_PROFILE_MODEL_P 1032 /* Record the fields for profiling. */ 1033 if (PROFILE_MODEL_P (current_cpu)) 1034 { 1035 } 1036 #endif 1037 #undef FLD 1038 return idesc; 1039 } 1040 1041 extract_sfmt_cmp: 1042 { 1043 const IDESC *idesc = &m32rbf_insn_data[itype]; 1044 CGEN_INSN_WORD insn = entire_insn; 1045 #define FLD(f) abuf->fields.sfmt_st_plus.f 1046 UINT f_r1; 1047 UINT f_r2; 1048 1049 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1050 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1051 1052 /* Record the fields for the semantic handler. */ 1053 FLD (f_r1) = f_r1; 1054 FLD (f_r2) = f_r2; 1055 FLD (i_src1) = & CPU (h_gr)[f_r1]; 1056 FLD (i_src2) = & CPU (h_gr)[f_r2]; 1057 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 1058 1059 #if WITH_PROFILE_MODEL_P 1060 /* Record the fields for profiling. */ 1061 if (PROFILE_MODEL_P (current_cpu)) 1062 { 1063 FLD (in_src1) = f_r1; 1064 FLD (in_src2) = f_r2; 1065 } 1066 #endif 1067 #undef FLD 1068 return idesc; 1069 } 1070 1071 extract_sfmt_cmpi: 1072 { 1073 const IDESC *idesc = &m32rbf_insn_data[itype]; 1074 CGEN_INSN_WORD insn = entire_insn; 1075 #define FLD(f) abuf->fields.sfmt_st_d.f 1076 UINT f_r2; 1077 INT f_simm16; 1078 1079 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 1080 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 1081 1082 /* Record the fields for the semantic handler. */ 1083 FLD (f_simm16) = f_simm16; 1084 FLD (f_r2) = f_r2; 1085 FLD (i_src2) = & CPU (h_gr)[f_r2]; 1086 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0)); 1087 1088 #if WITH_PROFILE_MODEL_P 1089 /* Record the fields for profiling. */ 1090 if (PROFILE_MODEL_P (current_cpu)) 1091 { 1092 FLD (in_src2) = f_r2; 1093 } 1094 #endif 1095 #undef FLD 1096 return idesc; 1097 } 1098 1099 extract_sfmt_div: 1100 { 1101 const IDESC *idesc = &m32rbf_insn_data[itype]; 1102 CGEN_INSN_WORD insn = entire_insn; 1103 #define FLD(f) abuf->fields.sfmt_add.f 1104 UINT f_r1; 1105 UINT f_r2; 1106 1107 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1108 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 1109 1110 /* Record the fields for the semantic handler. */ 1111 FLD (f_r1) = f_r1; 1112 FLD (f_r2) = f_r2; 1113 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1114 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1115 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); 1116 1117 #if WITH_PROFILE_MODEL_P 1118 /* Record the fields for profiling. */ 1119 if (PROFILE_MODEL_P (current_cpu)) 1120 { 1121 FLD (in_dr) = f_r1; 1122 FLD (in_sr) = f_r2; 1123 FLD (out_dr) = f_r1; 1124 } 1125 #endif 1126 #undef FLD 1127 return idesc; 1128 } 1129 1130 extract_sfmt_jl: 1131 { 1132 const IDESC *idesc = &m32rbf_insn_data[itype]; 1133 CGEN_INSN_WORD insn = entire_insn; 1134 #define FLD(f) abuf->fields.sfmt_jl.f 1135 UINT f_r2; 1136 1137 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1138 1139 /* Record the fields for the semantic handler. */ 1140 FLD (f_r2) = f_r2; 1141 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1142 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0)); 1143 1144 #if WITH_PROFILE_MODEL_P 1145 /* Record the fields for profiling. */ 1146 if (PROFILE_MODEL_P (current_cpu)) 1147 { 1148 FLD (in_sr) = f_r2; 1149 FLD (out_h_gr_SI_14) = 14; 1150 } 1151 #endif 1152 #undef FLD 1153 return idesc; 1154 } 1155 1156 extract_sfmt_jmp: 1157 { 1158 const IDESC *idesc = &m32rbf_insn_data[itype]; 1159 CGEN_INSN_WORD insn = entire_insn; 1160 #define FLD(f) abuf->fields.sfmt_jl.f 1161 UINT f_r2; 1162 1163 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1164 1165 /* Record the fields for the semantic handler. */ 1166 FLD (f_r2) = f_r2; 1167 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1168 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0)); 1169 1170 #if WITH_PROFILE_MODEL_P 1171 /* Record the fields for profiling. */ 1172 if (PROFILE_MODEL_P (current_cpu)) 1173 { 1174 FLD (in_sr) = f_r2; 1175 } 1176 #endif 1177 #undef FLD 1178 return idesc; 1179 } 1180 1181 extract_sfmt_ld: 1182 { 1183 const IDESC *idesc = &m32rbf_insn_data[itype]; 1184 CGEN_INSN_WORD insn = entire_insn; 1185 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1186 UINT f_r1; 1187 UINT f_r2; 1188 1189 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1190 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1191 1192 /* Record the fields for the semantic handler. */ 1193 FLD (f_r2) = f_r2; 1194 FLD (f_r1) = f_r1; 1195 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1196 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1197 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1198 1199 #if WITH_PROFILE_MODEL_P 1200 /* Record the fields for profiling. */ 1201 if (PROFILE_MODEL_P (current_cpu)) 1202 { 1203 FLD (in_sr) = f_r2; 1204 FLD (out_dr) = f_r1; 1205 } 1206 #endif 1207 #undef FLD 1208 return idesc; 1209 } 1210 1211 extract_sfmt_ld_d: 1212 { 1213 const IDESC *idesc = &m32rbf_insn_data[itype]; 1214 CGEN_INSN_WORD insn = entire_insn; 1215 #define FLD(f) abuf->fields.sfmt_add3.f 1216 UINT f_r1; 1217 UINT f_r2; 1218 INT f_simm16; 1219 1220 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1221 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 1222 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 1223 1224 /* Record the fields for the semantic handler. */ 1225 FLD (f_simm16) = f_simm16; 1226 FLD (f_r2) = f_r2; 1227 FLD (f_r1) = f_r1; 1228 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1229 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1230 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1231 1232 #if WITH_PROFILE_MODEL_P 1233 /* Record the fields for profiling. */ 1234 if (PROFILE_MODEL_P (current_cpu)) 1235 { 1236 FLD (in_sr) = f_r2; 1237 FLD (out_dr) = f_r1; 1238 } 1239 #endif 1240 #undef FLD 1241 return idesc; 1242 } 1243 1244 extract_sfmt_ldb: 1245 { 1246 const IDESC *idesc = &m32rbf_insn_data[itype]; 1247 CGEN_INSN_WORD insn = entire_insn; 1248 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1249 UINT f_r1; 1250 UINT f_r2; 1251 1252 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1253 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1254 1255 /* Record the fields for the semantic handler. */ 1256 FLD (f_r2) = f_r2; 1257 FLD (f_r1) = f_r1; 1258 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1259 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1260 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1261 1262 #if WITH_PROFILE_MODEL_P 1263 /* Record the fields for profiling. */ 1264 if (PROFILE_MODEL_P (current_cpu)) 1265 { 1266 FLD (in_sr) = f_r2; 1267 FLD (out_dr) = f_r1; 1268 } 1269 #endif 1270 #undef FLD 1271 return idesc; 1272 } 1273 1274 extract_sfmt_ldb_d: 1275 { 1276 const IDESC *idesc = &m32rbf_insn_data[itype]; 1277 CGEN_INSN_WORD insn = entire_insn; 1278 #define FLD(f) abuf->fields.sfmt_add3.f 1279 UINT f_r1; 1280 UINT f_r2; 1281 INT f_simm16; 1282 1283 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1284 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 1285 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 1286 1287 /* Record the fields for the semantic handler. */ 1288 FLD (f_simm16) = f_simm16; 1289 FLD (f_r2) = f_r2; 1290 FLD (f_r1) = f_r1; 1291 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1292 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1293 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1294 1295 #if WITH_PROFILE_MODEL_P 1296 /* Record the fields for profiling. */ 1297 if (PROFILE_MODEL_P (current_cpu)) 1298 { 1299 FLD (in_sr) = f_r2; 1300 FLD (out_dr) = f_r1; 1301 } 1302 #endif 1303 #undef FLD 1304 return idesc; 1305 } 1306 1307 extract_sfmt_ldh: 1308 { 1309 const IDESC *idesc = &m32rbf_insn_data[itype]; 1310 CGEN_INSN_WORD insn = entire_insn; 1311 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1312 UINT f_r1; 1313 UINT f_r2; 1314 1315 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1316 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1317 1318 /* Record the fields for the semantic handler. */ 1319 FLD (f_r2) = f_r2; 1320 FLD (f_r1) = f_r1; 1321 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1322 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1323 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1324 1325 #if WITH_PROFILE_MODEL_P 1326 /* Record the fields for profiling. */ 1327 if (PROFILE_MODEL_P (current_cpu)) 1328 { 1329 FLD (in_sr) = f_r2; 1330 FLD (out_dr) = f_r1; 1331 } 1332 #endif 1333 #undef FLD 1334 return idesc; 1335 } 1336 1337 extract_sfmt_ldh_d: 1338 { 1339 const IDESC *idesc = &m32rbf_insn_data[itype]; 1340 CGEN_INSN_WORD insn = entire_insn; 1341 #define FLD(f) abuf->fields.sfmt_add3.f 1342 UINT f_r1; 1343 UINT f_r2; 1344 INT f_simm16; 1345 1346 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1347 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 1348 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 1349 1350 /* Record the fields for the semantic handler. */ 1351 FLD (f_simm16) = f_simm16; 1352 FLD (f_r2) = f_r2; 1353 FLD (f_r1) = f_r1; 1354 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1355 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1356 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1357 1358 #if WITH_PROFILE_MODEL_P 1359 /* Record the fields for profiling. */ 1360 if (PROFILE_MODEL_P (current_cpu)) 1361 { 1362 FLD (in_sr) = f_r2; 1363 FLD (out_dr) = f_r1; 1364 } 1365 #endif 1366 #undef FLD 1367 return idesc; 1368 } 1369 1370 extract_sfmt_ld_plus: 1371 { 1372 const IDESC *idesc = &m32rbf_insn_data[itype]; 1373 CGEN_INSN_WORD insn = entire_insn; 1374 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1375 UINT f_r1; 1376 UINT f_r2; 1377 1378 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1379 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1380 1381 /* Record the fields for the semantic handler. */ 1382 FLD (f_r2) = f_r2; 1383 FLD (f_r1) = f_r1; 1384 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1385 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1386 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_plus", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1387 1388 #if WITH_PROFILE_MODEL_P 1389 /* Record the fields for profiling. */ 1390 if (PROFILE_MODEL_P (current_cpu)) 1391 { 1392 FLD (in_sr) = f_r2; 1393 FLD (out_dr) = f_r1; 1394 FLD (out_sr) = f_r2; 1395 } 1396 #endif 1397 #undef FLD 1398 return idesc; 1399 } 1400 1401 extract_sfmt_ld24: 1402 { 1403 const IDESC *idesc = &m32rbf_insn_data[itype]; 1404 CGEN_INSN_WORD insn = entire_insn; 1405 #define FLD(f) abuf->fields.sfmt_ld24.f 1406 UINT f_r1; 1407 UINT f_uimm24; 1408 1409 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1410 f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); 1411 1412 /* Record the fields for the semantic handler. */ 1413 FLD (f_r1) = f_r1; 1414 FLD (i_uimm24) = f_uimm24; 1415 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1416 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld24", "f_r1 0x%x", 'x', f_r1, "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0)); 1417 1418 #if WITH_PROFILE_MODEL_P 1419 /* Record the fields for profiling. */ 1420 if (PROFILE_MODEL_P (current_cpu)) 1421 { 1422 FLD (out_dr) = f_r1; 1423 } 1424 #endif 1425 #undef FLD 1426 return idesc; 1427 } 1428 1429 extract_sfmt_ldi8: 1430 { 1431 const IDESC *idesc = &m32rbf_insn_data[itype]; 1432 CGEN_INSN_WORD insn = entire_insn; 1433 #define FLD(f) abuf->fields.sfmt_addi.f 1434 UINT f_r1; 1435 INT f_simm8; 1436 1437 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1438 f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8); 1439 1440 /* Record the fields for the semantic handler. */ 1441 FLD (f_simm8) = f_simm8; 1442 FLD (f_r1) = f_r1; 1443 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1444 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); 1445 1446 #if WITH_PROFILE_MODEL_P 1447 /* Record the fields for profiling. */ 1448 if (PROFILE_MODEL_P (current_cpu)) 1449 { 1450 FLD (out_dr) = f_r1; 1451 } 1452 #endif 1453 #undef FLD 1454 return idesc; 1455 } 1456 1457 extract_sfmt_ldi16: 1458 { 1459 const IDESC *idesc = &m32rbf_insn_data[itype]; 1460 CGEN_INSN_WORD insn = entire_insn; 1461 #define FLD(f) abuf->fields.sfmt_add3.f 1462 UINT f_r1; 1463 INT f_simm16; 1464 1465 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1466 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 1467 1468 /* Record the fields for the semantic handler. */ 1469 FLD (f_simm16) = f_simm16; 1470 FLD (f_r1) = f_r1; 1471 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1472 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); 1473 1474 #if WITH_PROFILE_MODEL_P 1475 /* Record the fields for profiling. */ 1476 if (PROFILE_MODEL_P (current_cpu)) 1477 { 1478 FLD (out_dr) = f_r1; 1479 } 1480 #endif 1481 #undef FLD 1482 return idesc; 1483 } 1484 1485 extract_sfmt_lock: 1486 { 1487 const IDESC *idesc = &m32rbf_insn_data[itype]; 1488 CGEN_INSN_WORD insn = entire_insn; 1489 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1490 UINT f_r1; 1491 UINT f_r2; 1492 1493 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1494 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1495 1496 /* Record the fields for the semantic handler. */ 1497 FLD (f_r2) = f_r2; 1498 FLD (f_r1) = f_r1; 1499 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1500 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1501 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lock", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1502 1503 #if WITH_PROFILE_MODEL_P 1504 /* Record the fields for profiling. */ 1505 if (PROFILE_MODEL_P (current_cpu)) 1506 { 1507 FLD (in_sr) = f_r2; 1508 FLD (out_dr) = f_r1; 1509 } 1510 #endif 1511 #undef FLD 1512 return idesc; 1513 } 1514 1515 extract_sfmt_machi: 1516 { 1517 const IDESC *idesc = &m32rbf_insn_data[itype]; 1518 CGEN_INSN_WORD insn = entire_insn; 1519 #define FLD(f) abuf->fields.sfmt_st_plus.f 1520 UINT f_r1; 1521 UINT f_r2; 1522 1523 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1524 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1525 1526 /* Record the fields for the semantic handler. */ 1527 FLD (f_r1) = f_r1; 1528 FLD (f_r2) = f_r2; 1529 FLD (i_src1) = & CPU (h_gr)[f_r1]; 1530 FLD (i_src2) = & CPU (h_gr)[f_r2]; 1531 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machi", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 1532 1533 #if WITH_PROFILE_MODEL_P 1534 /* Record the fields for profiling. */ 1535 if (PROFILE_MODEL_P (current_cpu)) 1536 { 1537 FLD (in_src1) = f_r1; 1538 FLD (in_src2) = f_r2; 1539 } 1540 #endif 1541 #undef FLD 1542 return idesc; 1543 } 1544 1545 extract_sfmt_mulhi: 1546 { 1547 const IDESC *idesc = &m32rbf_insn_data[itype]; 1548 CGEN_INSN_WORD insn = entire_insn; 1549 #define FLD(f) abuf->fields.sfmt_st_plus.f 1550 UINT f_r1; 1551 UINT f_r2; 1552 1553 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1554 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1555 1556 /* Record the fields for the semantic handler. */ 1557 FLD (f_r1) = f_r1; 1558 FLD (f_r2) = f_r2; 1559 FLD (i_src1) = & CPU (h_gr)[f_r1]; 1560 FLD (i_src2) = & CPU (h_gr)[f_r2]; 1561 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulhi", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 1562 1563 #if WITH_PROFILE_MODEL_P 1564 /* Record the fields for profiling. */ 1565 if (PROFILE_MODEL_P (current_cpu)) 1566 { 1567 FLD (in_src1) = f_r1; 1568 FLD (in_src2) = f_r2; 1569 } 1570 #endif 1571 #undef FLD 1572 return idesc; 1573 } 1574 1575 extract_sfmt_mv: 1576 { 1577 const IDESC *idesc = &m32rbf_insn_data[itype]; 1578 CGEN_INSN_WORD insn = entire_insn; 1579 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1580 UINT f_r1; 1581 UINT f_r2; 1582 1583 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1584 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1585 1586 /* Record the fields for the semantic handler. */ 1587 FLD (f_r2) = f_r2; 1588 FLD (f_r1) = f_r1; 1589 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1590 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1591 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mv", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1592 1593 #if WITH_PROFILE_MODEL_P 1594 /* Record the fields for profiling. */ 1595 if (PROFILE_MODEL_P (current_cpu)) 1596 { 1597 FLD (in_sr) = f_r2; 1598 FLD (out_dr) = f_r1; 1599 } 1600 #endif 1601 #undef FLD 1602 return idesc; 1603 } 1604 1605 extract_sfmt_mvfachi: 1606 { 1607 const IDESC *idesc = &m32rbf_insn_data[itype]; 1608 CGEN_INSN_WORD insn = entire_insn; 1609 #define FLD(f) abuf->fields.sfmt_seth.f 1610 UINT f_r1; 1611 1612 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1613 1614 /* Record the fields for the semantic handler. */ 1615 FLD (f_r1) = f_r1; 1616 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1617 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfachi", "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); 1618 1619 #if WITH_PROFILE_MODEL_P 1620 /* Record the fields for profiling. */ 1621 if (PROFILE_MODEL_P (current_cpu)) 1622 { 1623 FLD (out_dr) = f_r1; 1624 } 1625 #endif 1626 #undef FLD 1627 return idesc; 1628 } 1629 1630 extract_sfmt_mvfc: 1631 { 1632 const IDESC *idesc = &m32rbf_insn_data[itype]; 1633 CGEN_INSN_WORD insn = entire_insn; 1634 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1635 UINT f_r1; 1636 UINT f_r2; 1637 1638 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1639 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1640 1641 /* Record the fields for the semantic handler. */ 1642 FLD (f_r2) = f_r2; 1643 FLD (f_r1) = f_r1; 1644 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1645 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); 1646 1647 #if WITH_PROFILE_MODEL_P 1648 /* Record the fields for profiling. */ 1649 if (PROFILE_MODEL_P (current_cpu)) 1650 { 1651 FLD (out_dr) = f_r1; 1652 } 1653 #endif 1654 #undef FLD 1655 return idesc; 1656 } 1657 1658 extract_sfmt_mvtachi: 1659 { 1660 const IDESC *idesc = &m32rbf_insn_data[itype]; 1661 CGEN_INSN_WORD insn = entire_insn; 1662 #define FLD(f) abuf->fields.sfmt_st_plus.f 1663 UINT f_r1; 1664 1665 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1666 1667 /* Record the fields for the semantic handler. */ 1668 FLD (f_r1) = f_r1; 1669 FLD (i_src1) = & CPU (h_gr)[f_r1]; 1670 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtachi", "f_r1 0x%x", 'x', f_r1, "src1 0x%x", 'x', f_r1, (char *) 0)); 1671 1672 #if WITH_PROFILE_MODEL_P 1673 /* Record the fields for profiling. */ 1674 if (PROFILE_MODEL_P (current_cpu)) 1675 { 1676 FLD (in_src1) = f_r1; 1677 } 1678 #endif 1679 #undef FLD 1680 return idesc; 1681 } 1682 1683 extract_sfmt_mvtc: 1684 { 1685 const IDESC *idesc = &m32rbf_insn_data[itype]; 1686 CGEN_INSN_WORD insn = entire_insn; 1687 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1688 UINT f_r1; 1689 UINT f_r2; 1690 1691 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1692 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1693 1694 /* Record the fields for the semantic handler. */ 1695 FLD (f_r2) = f_r2; 1696 FLD (f_r1) = f_r1; 1697 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1698 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); 1699 1700 #if WITH_PROFILE_MODEL_P 1701 /* Record the fields for profiling. */ 1702 if (PROFILE_MODEL_P (current_cpu)) 1703 { 1704 FLD (in_sr) = f_r2; 1705 } 1706 #endif 1707 #undef FLD 1708 return idesc; 1709 } 1710 1711 extract_sfmt_nop: 1712 { 1713 const IDESC *idesc = &m32rbf_insn_data[itype]; 1714 #define FLD(f) abuf->fields.sfmt_empty.f 1715 1716 1717 /* Record the fields for the semantic handler. */ 1718 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0)); 1719 1720 #undef FLD 1721 return idesc; 1722 } 1723 1724 extract_sfmt_rac: 1725 { 1726 const IDESC *idesc = &m32rbf_insn_data[itype]; 1727 #define FLD(f) abuf->fields.sfmt_empty.f 1728 1729 1730 /* Record the fields for the semantic handler. */ 1731 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rac", (char *) 0)); 1732 1733 #undef FLD 1734 return idesc; 1735 } 1736 1737 extract_sfmt_rte: 1738 { 1739 const IDESC *idesc = &m32rbf_insn_data[itype]; 1740 #define FLD(f) abuf->fields.sfmt_empty.f 1741 1742 1743 /* Record the fields for the semantic handler. */ 1744 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rte", (char *) 0)); 1745 1746 #if WITH_PROFILE_MODEL_P 1747 /* Record the fields for profiling. */ 1748 if (PROFILE_MODEL_P (current_cpu)) 1749 { 1750 } 1751 #endif 1752 #undef FLD 1753 return idesc; 1754 } 1755 1756 extract_sfmt_seth: 1757 { 1758 const IDESC *idesc = &m32rbf_insn_data[itype]; 1759 CGEN_INSN_WORD insn = entire_insn; 1760 #define FLD(f) abuf->fields.sfmt_seth.f 1761 UINT f_r1; 1762 UINT f_hi16; 1763 1764 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1765 f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); 1766 1767 /* Record the fields for the semantic handler. */ 1768 FLD (f_hi16) = f_hi16; 1769 FLD (f_r1) = f_r1; 1770 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1771 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_seth", "f_hi16 0x%x", 'x', f_hi16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); 1772 1773 #if WITH_PROFILE_MODEL_P 1774 /* Record the fields for profiling. */ 1775 if (PROFILE_MODEL_P (current_cpu)) 1776 { 1777 FLD (out_dr) = f_r1; 1778 } 1779 #endif 1780 #undef FLD 1781 return idesc; 1782 } 1783 1784 extract_sfmt_sll3: 1785 { 1786 const IDESC *idesc = &m32rbf_insn_data[itype]; 1787 CGEN_INSN_WORD insn = entire_insn; 1788 #define FLD(f) abuf->fields.sfmt_add3.f 1789 UINT f_r1; 1790 UINT f_r2; 1791 INT f_simm16; 1792 1793 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1794 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 1795 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 1796 1797 /* Record the fields for the semantic handler. */ 1798 FLD (f_simm16) = f_simm16; 1799 FLD (f_r2) = f_r2; 1800 FLD (f_r1) = f_r1; 1801 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1802 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1803 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1804 1805 #if WITH_PROFILE_MODEL_P 1806 /* Record the fields for profiling. */ 1807 if (PROFILE_MODEL_P (current_cpu)) 1808 { 1809 FLD (in_sr) = f_r2; 1810 FLD (out_dr) = f_r1; 1811 } 1812 #endif 1813 #undef FLD 1814 return idesc; 1815 } 1816 1817 extract_sfmt_slli: 1818 { 1819 const IDESC *idesc = &m32rbf_insn_data[itype]; 1820 CGEN_INSN_WORD insn = entire_insn; 1821 #define FLD(f) abuf->fields.sfmt_slli.f 1822 UINT f_r1; 1823 UINT f_uimm5; 1824 1825 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1826 f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); 1827 1828 /* Record the fields for the semantic handler. */ 1829 FLD (f_r1) = f_r1; 1830 FLD (f_uimm5) = f_uimm5; 1831 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1832 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slli", "f_r1 0x%x", 'x', f_r1, "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0)); 1833 1834 #if WITH_PROFILE_MODEL_P 1835 /* Record the fields for profiling. */ 1836 if (PROFILE_MODEL_P (current_cpu)) 1837 { 1838 FLD (in_dr) = f_r1; 1839 FLD (out_dr) = f_r1; 1840 } 1841 #endif 1842 #undef FLD 1843 return idesc; 1844 } 1845 1846 extract_sfmt_st: 1847 { 1848 const IDESC *idesc = &m32rbf_insn_data[itype]; 1849 CGEN_INSN_WORD insn = entire_insn; 1850 #define FLD(f) abuf->fields.sfmt_st_plus.f 1851 UINT f_r1; 1852 UINT f_r2; 1853 1854 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1855 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1856 1857 /* Record the fields for the semantic handler. */ 1858 FLD (f_r1) = f_r1; 1859 FLD (f_r2) = f_r2; 1860 FLD (i_src1) = & CPU (h_gr)[f_r1]; 1861 FLD (i_src2) = & CPU (h_gr)[f_r2]; 1862 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 1863 1864 #if WITH_PROFILE_MODEL_P 1865 /* Record the fields for profiling. */ 1866 if (PROFILE_MODEL_P (current_cpu)) 1867 { 1868 FLD (in_src1) = f_r1; 1869 FLD (in_src2) = f_r2; 1870 } 1871 #endif 1872 #undef FLD 1873 return idesc; 1874 } 1875 1876 extract_sfmt_st_d: 1877 { 1878 const IDESC *idesc = &m32rbf_insn_data[itype]; 1879 CGEN_INSN_WORD insn = entire_insn; 1880 #define FLD(f) abuf->fields.sfmt_st_d.f 1881 UINT f_r1; 1882 UINT f_r2; 1883 INT f_simm16; 1884 1885 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1886 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 1887 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 1888 1889 /* Record the fields for the semantic handler. */ 1890 FLD (f_simm16) = f_simm16; 1891 FLD (f_r1) = f_r1; 1892 FLD (f_r2) = f_r2; 1893 FLD (i_src1) = & CPU (h_gr)[f_r1]; 1894 FLD (i_src2) = & CPU (h_gr)[f_r2]; 1895 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 1896 1897 #if WITH_PROFILE_MODEL_P 1898 /* Record the fields for profiling. */ 1899 if (PROFILE_MODEL_P (current_cpu)) 1900 { 1901 FLD (in_src1) = f_r1; 1902 FLD (in_src2) = f_r2; 1903 } 1904 #endif 1905 #undef FLD 1906 return idesc; 1907 } 1908 1909 extract_sfmt_stb: 1910 { 1911 const IDESC *idesc = &m32rbf_insn_data[itype]; 1912 CGEN_INSN_WORD insn = entire_insn; 1913 #define FLD(f) abuf->fields.sfmt_st_plus.f 1914 UINT f_r1; 1915 UINT f_r2; 1916 1917 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1918 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1919 1920 /* Record the fields for the semantic handler. */ 1921 FLD (f_r1) = f_r1; 1922 FLD (f_r2) = f_r2; 1923 FLD (i_src1) = & CPU (h_gr)[f_r1]; 1924 FLD (i_src2) = & CPU (h_gr)[f_r2]; 1925 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 1926 1927 #if WITH_PROFILE_MODEL_P 1928 /* Record the fields for profiling. */ 1929 if (PROFILE_MODEL_P (current_cpu)) 1930 { 1931 FLD (in_src1) = f_r1; 1932 FLD (in_src2) = f_r2; 1933 } 1934 #endif 1935 #undef FLD 1936 return idesc; 1937 } 1938 1939 extract_sfmt_stb_d: 1940 { 1941 const IDESC *idesc = &m32rbf_insn_data[itype]; 1942 CGEN_INSN_WORD insn = entire_insn; 1943 #define FLD(f) abuf->fields.sfmt_st_d.f 1944 UINT f_r1; 1945 UINT f_r2; 1946 INT f_simm16; 1947 1948 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1949 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 1950 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 1951 1952 /* Record the fields for the semantic handler. */ 1953 FLD (f_simm16) = f_simm16; 1954 FLD (f_r1) = f_r1; 1955 FLD (f_r2) = f_r2; 1956 FLD (i_src1) = & CPU (h_gr)[f_r1]; 1957 FLD (i_src2) = & CPU (h_gr)[f_r2]; 1958 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 1959 1960 #if WITH_PROFILE_MODEL_P 1961 /* Record the fields for profiling. */ 1962 if (PROFILE_MODEL_P (current_cpu)) 1963 { 1964 FLD (in_src1) = f_r1; 1965 FLD (in_src2) = f_r2; 1966 } 1967 #endif 1968 #undef FLD 1969 return idesc; 1970 } 1971 1972 extract_sfmt_sth: 1973 { 1974 const IDESC *idesc = &m32rbf_insn_data[itype]; 1975 CGEN_INSN_WORD insn = entire_insn; 1976 #define FLD(f) abuf->fields.sfmt_st_plus.f 1977 UINT f_r1; 1978 UINT f_r2; 1979 1980 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1981 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1982 1983 /* Record the fields for the semantic handler. */ 1984 FLD (f_r1) = f_r1; 1985 FLD (f_r2) = f_r2; 1986 FLD (i_src1) = & CPU (h_gr)[f_r1]; 1987 FLD (i_src2) = & CPU (h_gr)[f_r2]; 1988 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 1989 1990 #if WITH_PROFILE_MODEL_P 1991 /* Record the fields for profiling. */ 1992 if (PROFILE_MODEL_P (current_cpu)) 1993 { 1994 FLD (in_src1) = f_r1; 1995 FLD (in_src2) = f_r2; 1996 } 1997 #endif 1998 #undef FLD 1999 return idesc; 2000 } 2001 2002 extract_sfmt_sth_d: 2003 { 2004 const IDESC *idesc = &m32rbf_insn_data[itype]; 2005 CGEN_INSN_WORD insn = entire_insn; 2006 #define FLD(f) abuf->fields.sfmt_st_d.f 2007 UINT f_r1; 2008 UINT f_r2; 2009 INT f_simm16; 2010 2011 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 2012 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 2013 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 2014 2015 /* Record the fields for the semantic handler. */ 2016 FLD (f_simm16) = f_simm16; 2017 FLD (f_r1) = f_r1; 2018 FLD (f_r2) = f_r2; 2019 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2020 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2021 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2022 2023 #if WITH_PROFILE_MODEL_P 2024 /* Record the fields for profiling. */ 2025 if (PROFILE_MODEL_P (current_cpu)) 2026 { 2027 FLD (in_src1) = f_r1; 2028 FLD (in_src2) = f_r2; 2029 } 2030 #endif 2031 #undef FLD 2032 return idesc; 2033 } 2034 2035 extract_sfmt_st_plus: 2036 { 2037 const IDESC *idesc = &m32rbf_insn_data[itype]; 2038 CGEN_INSN_WORD insn = entire_insn; 2039 #define FLD(f) abuf->fields.sfmt_st_plus.f 2040 UINT f_r1; 2041 UINT f_r2; 2042 2043 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2044 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2045 2046 /* Record the fields for the semantic handler. */ 2047 FLD (f_r1) = f_r1; 2048 FLD (f_r2) = f_r2; 2049 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2050 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2051 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2052 2053 #if WITH_PROFILE_MODEL_P 2054 /* Record the fields for profiling. */ 2055 if (PROFILE_MODEL_P (current_cpu)) 2056 { 2057 FLD (in_src1) = f_r1; 2058 FLD (in_src2) = f_r2; 2059 FLD (out_src2) = f_r2; 2060 } 2061 #endif 2062 #undef FLD 2063 return idesc; 2064 } 2065 2066 extract_sfmt_trap: 2067 { 2068 const IDESC *idesc = &m32rbf_insn_data[itype]; 2069 CGEN_INSN_WORD insn = entire_insn; 2070 #define FLD(f) abuf->fields.sfmt_trap.f 2071 UINT f_uimm4; 2072 2073 f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2074 2075 /* Record the fields for the semantic handler. */ 2076 FLD (f_uimm4) = f_uimm4; 2077 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0)); 2078 2079 #if WITH_PROFILE_MODEL_P 2080 /* Record the fields for profiling. */ 2081 if (PROFILE_MODEL_P (current_cpu)) 2082 { 2083 } 2084 #endif 2085 #undef FLD 2086 return idesc; 2087 } 2088 2089 extract_sfmt_unlock: 2090 { 2091 const IDESC *idesc = &m32rbf_insn_data[itype]; 2092 CGEN_INSN_WORD insn = entire_insn; 2093 #define FLD(f) abuf->fields.sfmt_st_plus.f 2094 UINT f_r1; 2095 UINT f_r2; 2096 2097 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2098 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2099 2100 /* Record the fields for the semantic handler. */ 2101 FLD (f_r1) = f_r1; 2102 FLD (f_r2) = f_r2; 2103 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2104 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2105 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_unlock", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2106 2107 #if WITH_PROFILE_MODEL_P 2108 /* Record the fields for profiling. */ 2109 if (PROFILE_MODEL_P (current_cpu)) 2110 { 2111 FLD (in_src1) = f_r1; 2112 FLD (in_src2) = f_r2; 2113 } 2114 #endif 2115 #undef FLD 2116 return idesc; 2117 } 2118 2119 extract_sfmt_clrpsw: 2120 { 2121 const IDESC *idesc = &m32rbf_insn_data[itype]; 2122 CGEN_INSN_WORD insn = entire_insn; 2123 #define FLD(f) abuf->fields.sfmt_clrpsw.f 2124 UINT f_uimm8; 2125 2126 f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); 2127 2128 /* Record the fields for the semantic handler. */ 2129 FLD (f_uimm8) = f_uimm8; 2130 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0)); 2131 2132 #undef FLD 2133 return idesc; 2134 } 2135 2136 extract_sfmt_setpsw: 2137 { 2138 const IDESC *idesc = &m32rbf_insn_data[itype]; 2139 CGEN_INSN_WORD insn = entire_insn; 2140 #define FLD(f) abuf->fields.sfmt_clrpsw.f 2141 UINT f_uimm8; 2142 2143 f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); 2144 2145 /* Record the fields for the semantic handler. */ 2146 FLD (f_uimm8) = f_uimm8; 2147 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_setpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0)); 2148 2149 #undef FLD 2150 return idesc; 2151 } 2152 2153 extract_sfmt_bset: 2154 { 2155 const IDESC *idesc = &m32rbf_insn_data[itype]; 2156 CGEN_INSN_WORD insn = entire_insn; 2157 #define FLD(f) abuf->fields.sfmt_bset.f 2158 UINT f_uimm3; 2159 UINT f_r2; 2160 INT f_simm16; 2161 2162 f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); 2163 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 2164 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 2165 2166 /* Record the fields for the semantic handler. */ 2167 FLD (f_simm16) = f_simm16; 2168 FLD (f_r2) = f_r2; 2169 FLD (f_uimm3) = f_uimm3; 2170 FLD (i_sr) = & CPU (h_gr)[f_r2]; 2171 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bset", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0)); 2172 2173 #if WITH_PROFILE_MODEL_P 2174 /* Record the fields for profiling. */ 2175 if (PROFILE_MODEL_P (current_cpu)) 2176 { 2177 FLD (in_sr) = f_r2; 2178 } 2179 #endif 2180 #undef FLD 2181 return idesc; 2182 } 2183 2184 extract_sfmt_btst: 2185 { 2186 const IDESC *idesc = &m32rbf_insn_data[itype]; 2187 CGEN_INSN_WORD insn = entire_insn; 2188 #define FLD(f) abuf->fields.sfmt_bset.f 2189 UINT f_uimm3; 2190 UINT f_r2; 2191 2192 f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); 2193 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2194 2195 /* Record the fields for the semantic handler. */ 2196 FLD (f_r2) = f_r2; 2197 FLD (f_uimm3) = f_uimm3; 2198 FLD (i_sr) = & CPU (h_gr)[f_r2]; 2199 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btst", "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0)); 2200 2201 #if WITH_PROFILE_MODEL_P 2202 /* Record the fields for profiling. */ 2203 if (PROFILE_MODEL_P (current_cpu)) 2204 { 2205 FLD (in_sr) = f_r2; 2206 } 2207 #endif 2208 #undef FLD 2209 return idesc; 2210 } 2211 2212 } 2213