1 /* Simulator instruction semantics for lm32bf. 2 3 THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5 Copyright 1996-2020 Free Software Foundation, Inc. 6 7 This file is part of the GNU simulators. 8 9 This file is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License along 20 with this program; if not, see <http://www.gnu.org/licenses/>. 21 22 */ 23 24 #ifdef DEFINE_LABELS 25 26 /* The labels have the case they have because the enum of insn types 27 is all uppercase and in the non-stdc case the insn symbol is built 28 into the enum name. */ 29 30 static struct { 31 int index; 32 void *label; 33 } labels[] = { 34 { LM32BF_INSN_X_INVALID, && case_sem_INSN_X_INVALID }, 35 { LM32BF_INSN_X_AFTER, && case_sem_INSN_X_AFTER }, 36 { LM32BF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE }, 37 { LM32BF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN }, 38 { LM32BF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN }, 39 { LM32BF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN }, 40 { LM32BF_INSN_ADD, && case_sem_INSN_ADD }, 41 { LM32BF_INSN_ADDI, && case_sem_INSN_ADDI }, 42 { LM32BF_INSN_AND, && case_sem_INSN_AND }, 43 { LM32BF_INSN_ANDI, && case_sem_INSN_ANDI }, 44 { LM32BF_INSN_ANDHII, && case_sem_INSN_ANDHII }, 45 { LM32BF_INSN_B, && case_sem_INSN_B }, 46 { LM32BF_INSN_BI, && case_sem_INSN_BI }, 47 { LM32BF_INSN_BE, && case_sem_INSN_BE }, 48 { LM32BF_INSN_BG, && case_sem_INSN_BG }, 49 { LM32BF_INSN_BGE, && case_sem_INSN_BGE }, 50 { LM32BF_INSN_BGEU, && case_sem_INSN_BGEU }, 51 { LM32BF_INSN_BGU, && case_sem_INSN_BGU }, 52 { LM32BF_INSN_BNE, && case_sem_INSN_BNE }, 53 { LM32BF_INSN_CALL, && case_sem_INSN_CALL }, 54 { LM32BF_INSN_CALLI, && case_sem_INSN_CALLI }, 55 { LM32BF_INSN_CMPE, && case_sem_INSN_CMPE }, 56 { LM32BF_INSN_CMPEI, && case_sem_INSN_CMPEI }, 57 { LM32BF_INSN_CMPG, && case_sem_INSN_CMPG }, 58 { LM32BF_INSN_CMPGI, && case_sem_INSN_CMPGI }, 59 { LM32BF_INSN_CMPGE, && case_sem_INSN_CMPGE }, 60 { LM32BF_INSN_CMPGEI, && case_sem_INSN_CMPGEI }, 61 { LM32BF_INSN_CMPGEU, && case_sem_INSN_CMPGEU }, 62 { LM32BF_INSN_CMPGEUI, && case_sem_INSN_CMPGEUI }, 63 { LM32BF_INSN_CMPGU, && case_sem_INSN_CMPGU }, 64 { LM32BF_INSN_CMPGUI, && case_sem_INSN_CMPGUI }, 65 { LM32BF_INSN_CMPNE, && case_sem_INSN_CMPNE }, 66 { LM32BF_INSN_CMPNEI, && case_sem_INSN_CMPNEI }, 67 { LM32BF_INSN_DIVU, && case_sem_INSN_DIVU }, 68 { LM32BF_INSN_LB, && case_sem_INSN_LB }, 69 { LM32BF_INSN_LBU, && case_sem_INSN_LBU }, 70 { LM32BF_INSN_LH, && case_sem_INSN_LH }, 71 { LM32BF_INSN_LHU, && case_sem_INSN_LHU }, 72 { LM32BF_INSN_LW, && case_sem_INSN_LW }, 73 { LM32BF_INSN_MODU, && case_sem_INSN_MODU }, 74 { LM32BF_INSN_MUL, && case_sem_INSN_MUL }, 75 { LM32BF_INSN_MULI, && case_sem_INSN_MULI }, 76 { LM32BF_INSN_NOR, && case_sem_INSN_NOR }, 77 { LM32BF_INSN_NORI, && case_sem_INSN_NORI }, 78 { LM32BF_INSN_OR, && case_sem_INSN_OR }, 79 { LM32BF_INSN_ORI, && case_sem_INSN_ORI }, 80 { LM32BF_INSN_ORHII, && case_sem_INSN_ORHII }, 81 { LM32BF_INSN_RCSR, && case_sem_INSN_RCSR }, 82 { LM32BF_INSN_SB, && case_sem_INSN_SB }, 83 { LM32BF_INSN_SEXTB, && case_sem_INSN_SEXTB }, 84 { LM32BF_INSN_SEXTH, && case_sem_INSN_SEXTH }, 85 { LM32BF_INSN_SH, && case_sem_INSN_SH }, 86 { LM32BF_INSN_SL, && case_sem_INSN_SL }, 87 { LM32BF_INSN_SLI, && case_sem_INSN_SLI }, 88 { LM32BF_INSN_SR, && case_sem_INSN_SR }, 89 { LM32BF_INSN_SRI, && case_sem_INSN_SRI }, 90 { LM32BF_INSN_SRU, && case_sem_INSN_SRU }, 91 { LM32BF_INSN_SRUI, && case_sem_INSN_SRUI }, 92 { LM32BF_INSN_SUB, && case_sem_INSN_SUB }, 93 { LM32BF_INSN_SW, && case_sem_INSN_SW }, 94 { LM32BF_INSN_USER, && case_sem_INSN_USER }, 95 { LM32BF_INSN_WCSR, && case_sem_INSN_WCSR }, 96 { LM32BF_INSN_XOR, && case_sem_INSN_XOR }, 97 { LM32BF_INSN_XORI, && case_sem_INSN_XORI }, 98 { LM32BF_INSN_XNOR, && case_sem_INSN_XNOR }, 99 { LM32BF_INSN_XNORI, && case_sem_INSN_XNORI }, 100 { LM32BF_INSN_BREAK, && case_sem_INSN_BREAK }, 101 { LM32BF_INSN_SCALL, && case_sem_INSN_SCALL }, 102 { 0, 0 } 103 }; 104 int i; 105 106 for (i = 0; labels[i].label != 0; ++i) 107 { 108 #if FAST_P 109 CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label; 110 #else 111 CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label; 112 #endif 113 } 114 115 #undef DEFINE_LABELS 116 #endif /* DEFINE_LABELS */ 117 118 #ifdef DEFINE_SWITCH 119 120 /* If hyper-fast [well not unnecessarily slow] execution is selected, turn 121 off frills like tracing and profiling. */ 122 /* FIXME: A better way would be to have CGEN_TRACE_RESULT check for something 123 that can cause it to be optimized out. Another way would be to emit 124 special handlers into the instruction "stream". */ 125 126 #if FAST_P 127 #undef CGEN_TRACE_RESULT 128 #define CGEN_TRACE_RESULT(cpu, abuf, name, type, val) 129 #endif 130 131 #undef GET_ATTR 132 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr) 133 134 { 135 136 #if WITH_SCACHE_PBB 137 138 /* Branch to next handler without going around main loop. */ 139 #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case 140 SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) 141 142 #else /* ! WITH_SCACHE_PBB */ 143 144 #define NEXT(vpc) BREAK (sem) 145 #ifdef __GNUC__ 146 #if FAST_P 147 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab) 148 #else 149 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab) 150 #endif 151 #else 152 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num) 153 #endif 154 155 #endif /* ! WITH_SCACHE_PBB */ 156 157 { 158 159 CASE (sem, INSN_X_INVALID) : /* --invalid-- */ 160 { 161 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 162 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 163 #define FLD(f) abuf->fields.sfmt_empty.f 164 int UNUSED written = 0; 165 IADDR UNUSED pc = abuf->addr; 166 vpc = SEM_NEXT_VPC (sem_arg, pc, 0); 167 168 { 169 /* Update the recorded pc in the cpu state struct. 170 Only necessary for WITH_SCACHE case, but to avoid the 171 conditional compilation .... */ 172 SET_H_PC (pc); 173 /* Virtual insns have zero size. Overwrite vpc with address of next insn 174 using the default-insn-bitsize spec. When executing insns in parallel 175 we may want to queue the fault and continue execution. */ 176 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 177 vpc = sim_engine_invalid_insn (current_cpu, pc, vpc); 178 } 179 180 #undef FLD 181 } 182 NEXT (vpc); 183 184 CASE (sem, INSN_X_AFTER) : /* --after-- */ 185 { 186 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 187 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 188 #define FLD(f) abuf->fields.sfmt_empty.f 189 int UNUSED written = 0; 190 IADDR UNUSED pc = abuf->addr; 191 vpc = SEM_NEXT_VPC (sem_arg, pc, 0); 192 193 { 194 #if WITH_SCACHE_PBB_LM32BF 195 lm32bf_pbb_after (current_cpu, sem_arg); 196 #endif 197 } 198 199 #undef FLD 200 } 201 NEXT (vpc); 202 203 CASE (sem, INSN_X_BEFORE) : /* --before-- */ 204 { 205 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 206 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 207 #define FLD(f) abuf->fields.sfmt_empty.f 208 int UNUSED written = 0; 209 IADDR UNUSED pc = abuf->addr; 210 vpc = SEM_NEXT_VPC (sem_arg, pc, 0); 211 212 { 213 #if WITH_SCACHE_PBB_LM32BF 214 lm32bf_pbb_before (current_cpu, sem_arg); 215 #endif 216 } 217 218 #undef FLD 219 } 220 NEXT (vpc); 221 222 CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */ 223 { 224 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 225 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 226 #define FLD(f) abuf->fields.sfmt_empty.f 227 int UNUSED written = 0; 228 IADDR UNUSED pc = abuf->addr; 229 vpc = SEM_NEXT_VPC (sem_arg, pc, 0); 230 231 { 232 #if WITH_SCACHE_PBB_LM32BF 233 #ifdef DEFINE_SWITCH 234 vpc = lm32bf_pbb_cti_chain (current_cpu, sem_arg, 235 pbb_br_type, pbb_br_npc); 236 BREAK (sem); 237 #else 238 /* FIXME: Allow provision of explicit ifmt spec in insn spec. */ 239 vpc = lm32bf_pbb_cti_chain (current_cpu, sem_arg, 240 CPU_PBB_BR_TYPE (current_cpu), 241 CPU_PBB_BR_NPC (current_cpu)); 242 #endif 243 #endif 244 } 245 246 #undef FLD 247 } 248 NEXT (vpc); 249 250 CASE (sem, INSN_X_CHAIN) : /* --chain-- */ 251 { 252 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 253 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 254 #define FLD(f) abuf->fields.sfmt_empty.f 255 int UNUSED written = 0; 256 IADDR UNUSED pc = abuf->addr; 257 vpc = SEM_NEXT_VPC (sem_arg, pc, 0); 258 259 { 260 #if WITH_SCACHE_PBB_LM32BF 261 vpc = lm32bf_pbb_chain (current_cpu, sem_arg); 262 #ifdef DEFINE_SWITCH 263 BREAK (sem); 264 #endif 265 #endif 266 } 267 268 #undef FLD 269 } 270 NEXT (vpc); 271 272 CASE (sem, INSN_X_BEGIN) : /* --begin-- */ 273 { 274 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 275 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 276 #define FLD(f) abuf->fields.sfmt_empty.f 277 int UNUSED written = 0; 278 IADDR UNUSED pc = abuf->addr; 279 vpc = SEM_NEXT_VPC (sem_arg, pc, 0); 280 281 { 282 #if WITH_SCACHE_PBB_LM32BF 283 #if defined DEFINE_SWITCH || defined FAST_P 284 /* In the switch case FAST_P is a constant, allowing several optimizations 285 in any called inline functions. */ 286 vpc = lm32bf_pbb_begin (current_cpu, FAST_P); 287 #else 288 #if 0 /* cgen engine can't handle dynamic fast/full switching yet. */ 289 vpc = lm32bf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu))); 290 #else 291 vpc = lm32bf_pbb_begin (current_cpu, 0); 292 #endif 293 #endif 294 #endif 295 } 296 297 #undef FLD 298 } 299 NEXT (vpc); 300 301 CASE (sem, INSN_ADD) : /* add $r2,$r0,$r1 */ 302 { 303 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 304 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 305 #define FLD(f) abuf->fields.sfmt_user.f 306 int UNUSED written = 0; 307 IADDR UNUSED pc = abuf->addr; 308 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 309 310 { 311 SI opval = ADDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])); 312 CPU (h_gr[FLD (f_r2)]) = opval; 313 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 314 } 315 316 #undef FLD 317 } 318 NEXT (vpc); 319 320 CASE (sem, INSN_ADDI) : /* addi $r1,$r0,$imm */ 321 { 322 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 323 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 324 #define FLD(f) abuf->fields.sfmt_addi.f 325 int UNUSED written = 0; 326 IADDR UNUSED pc = abuf->addr; 327 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 328 329 { 330 SI opval = ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))); 331 CPU (h_gr[FLD (f_r1)]) = opval; 332 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 333 } 334 335 #undef FLD 336 } 337 NEXT (vpc); 338 339 CASE (sem, INSN_AND) : /* and $r2,$r0,$r1 */ 340 { 341 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 342 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 343 #define FLD(f) abuf->fields.sfmt_user.f 344 int UNUSED written = 0; 345 IADDR UNUSED pc = abuf->addr; 346 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 347 348 { 349 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])); 350 CPU (h_gr[FLD (f_r2)]) = opval; 351 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 352 } 353 354 #undef FLD 355 } 356 NEXT (vpc); 357 358 CASE (sem, INSN_ANDI) : /* andi $r1,$r0,$uimm */ 359 { 360 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 361 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 362 #define FLD(f) abuf->fields.sfmt_andi.f 363 int UNUSED written = 0; 364 IADDR UNUSED pc = abuf->addr; 365 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 366 367 { 368 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm))); 369 CPU (h_gr[FLD (f_r1)]) = opval; 370 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 371 } 372 373 #undef FLD 374 } 375 NEXT (vpc); 376 377 CASE (sem, INSN_ANDHII) : /* andhi $r1,$r0,$hi16 */ 378 { 379 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 380 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 381 #define FLD(f) abuf->fields.sfmt_andi.f 382 int UNUSED written = 0; 383 IADDR UNUSED pc = abuf->addr; 384 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 385 386 { 387 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), SLLSI (FLD (f_uimm), 16)); 388 CPU (h_gr[FLD (f_r1)]) = opval; 389 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 390 } 391 392 #undef FLD 393 } 394 NEXT (vpc); 395 396 CASE (sem, INSN_B) : /* b $r0 */ 397 { 398 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 399 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 400 #define FLD(f) abuf->fields.sfmt_be.f 401 int UNUSED written = 0; 402 IADDR UNUSED pc = abuf->addr; 403 SEM_BRANCH_INIT 404 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 405 406 { 407 USI opval = lm32bf_b_insn (current_cpu, CPU (h_gr[FLD (f_r0)]), FLD (f_r0)); 408 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); 409 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 410 } 411 412 SEM_BRANCH_FINI (vpc); 413 #undef FLD 414 } 415 NEXT (vpc); 416 417 CASE (sem, INSN_BI) : /* bi $call */ 418 { 419 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 420 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 421 #define FLD(f) abuf->fields.sfmt_bi.f 422 int UNUSED written = 0; 423 IADDR UNUSED pc = abuf->addr; 424 SEM_BRANCH_INIT 425 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 426 427 { 428 USI opval = EXTSISI (FLD (i_call)); 429 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); 430 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 431 } 432 433 SEM_BRANCH_FINI (vpc); 434 #undef FLD 435 } 436 NEXT (vpc); 437 438 CASE (sem, INSN_BE) : /* be $r0,$r1,$branch */ 439 { 440 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 441 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 442 #define FLD(f) abuf->fields.sfmt_be.f 443 int UNUSED written = 0; 444 IADDR UNUSED pc = abuf->addr; 445 SEM_BRANCH_INIT 446 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 447 448 if (EQSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) { 449 { 450 USI opval = FLD (i_branch); 451 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 452 written |= (1 << 3); 453 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 454 } 455 } 456 457 abuf->written = written; 458 SEM_BRANCH_FINI (vpc); 459 #undef FLD 460 } 461 NEXT (vpc); 462 463 CASE (sem, INSN_BG) : /* bg $r0,$r1,$branch */ 464 { 465 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 466 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 467 #define FLD(f) abuf->fields.sfmt_be.f 468 int UNUSED written = 0; 469 IADDR UNUSED pc = abuf->addr; 470 SEM_BRANCH_INIT 471 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 472 473 if (GTSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) { 474 { 475 USI opval = FLD (i_branch); 476 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 477 written |= (1 << 3); 478 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 479 } 480 } 481 482 abuf->written = written; 483 SEM_BRANCH_FINI (vpc); 484 #undef FLD 485 } 486 NEXT (vpc); 487 488 CASE (sem, INSN_BGE) : /* bge $r0,$r1,$branch */ 489 { 490 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 491 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 492 #define FLD(f) abuf->fields.sfmt_be.f 493 int UNUSED written = 0; 494 IADDR UNUSED pc = abuf->addr; 495 SEM_BRANCH_INIT 496 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 497 498 if (GESI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) { 499 { 500 USI opval = FLD (i_branch); 501 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 502 written |= (1 << 3); 503 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 504 } 505 } 506 507 abuf->written = written; 508 SEM_BRANCH_FINI (vpc); 509 #undef FLD 510 } 511 NEXT (vpc); 512 513 CASE (sem, INSN_BGEU) : /* bgeu $r0,$r1,$branch */ 514 { 515 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 516 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 517 #define FLD(f) abuf->fields.sfmt_be.f 518 int UNUSED written = 0; 519 IADDR UNUSED pc = abuf->addr; 520 SEM_BRANCH_INIT 521 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 522 523 if (GEUSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) { 524 { 525 USI opval = FLD (i_branch); 526 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 527 written |= (1 << 3); 528 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 529 } 530 } 531 532 abuf->written = written; 533 SEM_BRANCH_FINI (vpc); 534 #undef FLD 535 } 536 NEXT (vpc); 537 538 CASE (sem, INSN_BGU) : /* bgu $r0,$r1,$branch */ 539 { 540 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 541 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 542 #define FLD(f) abuf->fields.sfmt_be.f 543 int UNUSED written = 0; 544 IADDR UNUSED pc = abuf->addr; 545 SEM_BRANCH_INIT 546 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 547 548 if (GTUSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) { 549 { 550 USI opval = FLD (i_branch); 551 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 552 written |= (1 << 3); 553 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 554 } 555 } 556 557 abuf->written = written; 558 SEM_BRANCH_FINI (vpc); 559 #undef FLD 560 } 561 NEXT (vpc); 562 563 CASE (sem, INSN_BNE) : /* bne $r0,$r1,$branch */ 564 { 565 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 566 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 567 #define FLD(f) abuf->fields.sfmt_be.f 568 int UNUSED written = 0; 569 IADDR UNUSED pc = abuf->addr; 570 SEM_BRANCH_INIT 571 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 572 573 if (NESI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) { 574 { 575 USI opval = FLD (i_branch); 576 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 577 written |= (1 << 3); 578 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 579 } 580 } 581 582 abuf->written = written; 583 SEM_BRANCH_FINI (vpc); 584 #undef FLD 585 } 586 NEXT (vpc); 587 588 CASE (sem, INSN_CALL) : /* call $r0 */ 589 { 590 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 591 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 592 #define FLD(f) abuf->fields.sfmt_be.f 593 int UNUSED written = 0; 594 IADDR UNUSED pc = abuf->addr; 595 SEM_BRANCH_INIT 596 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 597 598 { 599 { 600 SI opval = ADDSI (pc, 4); 601 CPU (h_gr[((UINT) 29)]) = opval; 602 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 603 } 604 { 605 USI opval = CPU (h_gr[FLD (f_r0)]); 606 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); 607 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 608 } 609 } 610 611 SEM_BRANCH_FINI (vpc); 612 #undef FLD 613 } 614 NEXT (vpc); 615 616 CASE (sem, INSN_CALLI) : /* calli $call */ 617 { 618 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 619 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 620 #define FLD(f) abuf->fields.sfmt_bi.f 621 int UNUSED written = 0; 622 IADDR UNUSED pc = abuf->addr; 623 SEM_BRANCH_INIT 624 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 625 626 { 627 { 628 SI opval = ADDSI (pc, 4); 629 CPU (h_gr[((UINT) 29)]) = opval; 630 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 631 } 632 { 633 USI opval = EXTSISI (FLD (i_call)); 634 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); 635 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 636 } 637 } 638 639 SEM_BRANCH_FINI (vpc); 640 #undef FLD 641 } 642 NEXT (vpc); 643 644 CASE (sem, INSN_CMPE) : /* cmpe $r2,$r0,$r1 */ 645 { 646 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 647 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 648 #define FLD(f) abuf->fields.sfmt_user.f 649 int UNUSED written = 0; 650 IADDR UNUSED pc = abuf->addr; 651 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 652 653 { 654 SI opval = EQSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])); 655 CPU (h_gr[FLD (f_r2)]) = opval; 656 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 657 } 658 659 #undef FLD 660 } 661 NEXT (vpc); 662 663 CASE (sem, INSN_CMPEI) : /* cmpei $r1,$r0,$imm */ 664 { 665 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 666 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 667 #define FLD(f) abuf->fields.sfmt_addi.f 668 int UNUSED written = 0; 669 IADDR UNUSED pc = abuf->addr; 670 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 671 672 { 673 SI opval = EQSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))); 674 CPU (h_gr[FLD (f_r1)]) = opval; 675 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 676 } 677 678 #undef FLD 679 } 680 NEXT (vpc); 681 682 CASE (sem, INSN_CMPG) : /* cmpg $r2,$r0,$r1 */ 683 { 684 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 685 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 686 #define FLD(f) abuf->fields.sfmt_user.f 687 int UNUSED written = 0; 688 IADDR UNUSED pc = abuf->addr; 689 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 690 691 { 692 SI opval = GTSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])); 693 CPU (h_gr[FLD (f_r2)]) = opval; 694 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 695 } 696 697 #undef FLD 698 } 699 NEXT (vpc); 700 701 CASE (sem, INSN_CMPGI) : /* cmpgi $r1,$r0,$imm */ 702 { 703 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 704 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 705 #define FLD(f) abuf->fields.sfmt_addi.f 706 int UNUSED written = 0; 707 IADDR UNUSED pc = abuf->addr; 708 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 709 710 { 711 SI opval = GTSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))); 712 CPU (h_gr[FLD (f_r1)]) = opval; 713 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 714 } 715 716 #undef FLD 717 } 718 NEXT (vpc); 719 720 CASE (sem, INSN_CMPGE) : /* cmpge $r2,$r0,$r1 */ 721 { 722 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 723 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 724 #define FLD(f) abuf->fields.sfmt_user.f 725 int UNUSED written = 0; 726 IADDR UNUSED pc = abuf->addr; 727 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 728 729 { 730 SI opval = GESI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])); 731 CPU (h_gr[FLD (f_r2)]) = opval; 732 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 733 } 734 735 #undef FLD 736 } 737 NEXT (vpc); 738 739 CASE (sem, INSN_CMPGEI) : /* cmpgei $r1,$r0,$imm */ 740 { 741 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 742 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 743 #define FLD(f) abuf->fields.sfmt_addi.f 744 int UNUSED written = 0; 745 IADDR UNUSED pc = abuf->addr; 746 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 747 748 { 749 SI opval = GESI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))); 750 CPU (h_gr[FLD (f_r1)]) = opval; 751 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 752 } 753 754 #undef FLD 755 } 756 NEXT (vpc); 757 758 CASE (sem, INSN_CMPGEU) : /* cmpgeu $r2,$r0,$r1 */ 759 { 760 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 761 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 762 #define FLD(f) abuf->fields.sfmt_user.f 763 int UNUSED written = 0; 764 IADDR UNUSED pc = abuf->addr; 765 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 766 767 { 768 SI opval = GEUSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])); 769 CPU (h_gr[FLD (f_r2)]) = opval; 770 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 771 } 772 773 #undef FLD 774 } 775 NEXT (vpc); 776 777 CASE (sem, INSN_CMPGEUI) : /* cmpgeui $r1,$r0,$uimm */ 778 { 779 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 780 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 781 #define FLD(f) abuf->fields.sfmt_andi.f 782 int UNUSED written = 0; 783 IADDR UNUSED pc = abuf->addr; 784 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 785 786 { 787 SI opval = GEUSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm))); 788 CPU (h_gr[FLD (f_r1)]) = opval; 789 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 790 } 791 792 #undef FLD 793 } 794 NEXT (vpc); 795 796 CASE (sem, INSN_CMPGU) : /* cmpgu $r2,$r0,$r1 */ 797 { 798 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 799 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 800 #define FLD(f) abuf->fields.sfmt_user.f 801 int UNUSED written = 0; 802 IADDR UNUSED pc = abuf->addr; 803 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 804 805 { 806 SI opval = GTUSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])); 807 CPU (h_gr[FLD (f_r2)]) = opval; 808 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 809 } 810 811 #undef FLD 812 } 813 NEXT (vpc); 814 815 CASE (sem, INSN_CMPGUI) : /* cmpgui $r1,$r0,$uimm */ 816 { 817 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 818 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 819 #define FLD(f) abuf->fields.sfmt_andi.f 820 int UNUSED written = 0; 821 IADDR UNUSED pc = abuf->addr; 822 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 823 824 { 825 SI opval = GTUSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm))); 826 CPU (h_gr[FLD (f_r1)]) = opval; 827 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 828 } 829 830 #undef FLD 831 } 832 NEXT (vpc); 833 834 CASE (sem, INSN_CMPNE) : /* cmpne $r2,$r0,$r1 */ 835 { 836 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 837 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 838 #define FLD(f) abuf->fields.sfmt_user.f 839 int UNUSED written = 0; 840 IADDR UNUSED pc = abuf->addr; 841 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 842 843 { 844 SI opval = NESI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])); 845 CPU (h_gr[FLD (f_r2)]) = opval; 846 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 847 } 848 849 #undef FLD 850 } 851 NEXT (vpc); 852 853 CASE (sem, INSN_CMPNEI) : /* cmpnei $r1,$r0,$imm */ 854 { 855 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 856 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 857 #define FLD(f) abuf->fields.sfmt_addi.f 858 int UNUSED written = 0; 859 IADDR UNUSED pc = abuf->addr; 860 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 861 862 { 863 SI opval = NESI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))); 864 CPU (h_gr[FLD (f_r1)]) = opval; 865 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 866 } 867 868 #undef FLD 869 } 870 NEXT (vpc); 871 872 CASE (sem, INSN_DIVU) : /* divu $r2,$r0,$r1 */ 873 { 874 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 875 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 876 #define FLD(f) abuf->fields.sfmt_user.f 877 int UNUSED written = 0; 878 IADDR UNUSED pc = abuf->addr; 879 SEM_BRANCH_INIT 880 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 881 882 { 883 USI opval = lm32bf_divu_insn (current_cpu, pc, FLD (f_r0), FLD (f_r1), FLD (f_r2)); 884 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); 885 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 886 } 887 888 SEM_BRANCH_FINI (vpc); 889 #undef FLD 890 } 891 NEXT (vpc); 892 893 CASE (sem, INSN_LB) : /* lb $r1,($r0+$imm) */ 894 { 895 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 896 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 897 #define FLD(f) abuf->fields.sfmt_addi.f 898 int UNUSED written = 0; 899 IADDR UNUSED pc = abuf->addr; 900 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 901 902 { 903 SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))))); 904 CPU (h_gr[FLD (f_r1)]) = opval; 905 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 906 } 907 908 #undef FLD 909 } 910 NEXT (vpc); 911 912 CASE (sem, INSN_LBU) : /* lbu $r1,($r0+$imm) */ 913 { 914 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 915 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 916 #define FLD(f) abuf->fields.sfmt_addi.f 917 int UNUSED written = 0; 918 IADDR UNUSED pc = abuf->addr; 919 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 920 921 { 922 SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))))); 923 CPU (h_gr[FLD (f_r1)]) = opval; 924 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 925 } 926 927 #undef FLD 928 } 929 NEXT (vpc); 930 931 CASE (sem, INSN_LH) : /* lh $r1,($r0+$imm) */ 932 { 933 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 934 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 935 #define FLD(f) abuf->fields.sfmt_addi.f 936 int UNUSED written = 0; 937 IADDR UNUSED pc = abuf->addr; 938 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 939 940 { 941 SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))))); 942 CPU (h_gr[FLD (f_r1)]) = opval; 943 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 944 } 945 946 #undef FLD 947 } 948 NEXT (vpc); 949 950 CASE (sem, INSN_LHU) : /* lhu $r1,($r0+$imm) */ 951 { 952 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 953 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 954 #define FLD(f) abuf->fields.sfmt_addi.f 955 int UNUSED written = 0; 956 IADDR UNUSED pc = abuf->addr; 957 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 958 959 { 960 SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))))); 961 CPU (h_gr[FLD (f_r1)]) = opval; 962 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 963 } 964 965 #undef FLD 966 } 967 NEXT (vpc); 968 969 CASE (sem, INSN_LW) : /* lw $r1,($r0+$imm) */ 970 { 971 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 972 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 973 #define FLD(f) abuf->fields.sfmt_addi.f 974 int UNUSED written = 0; 975 IADDR UNUSED pc = abuf->addr; 976 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 977 978 { 979 SI opval = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))))); 980 CPU (h_gr[FLD (f_r1)]) = opval; 981 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 982 } 983 984 #undef FLD 985 } 986 NEXT (vpc); 987 988 CASE (sem, INSN_MODU) : /* modu $r2,$r0,$r1 */ 989 { 990 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 991 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 992 #define FLD(f) abuf->fields.sfmt_user.f 993 int UNUSED written = 0; 994 IADDR UNUSED pc = abuf->addr; 995 SEM_BRANCH_INIT 996 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 997 998 { 999 USI opval = lm32bf_modu_insn (current_cpu, pc, FLD (f_r0), FLD (f_r1), FLD (f_r2)); 1000 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); 1001 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1002 } 1003 1004 SEM_BRANCH_FINI (vpc); 1005 #undef FLD 1006 } 1007 NEXT (vpc); 1008 1009 CASE (sem, INSN_MUL) : /* mul $r2,$r0,$r1 */ 1010 { 1011 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1012 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1013 #define FLD(f) abuf->fields.sfmt_user.f 1014 int UNUSED written = 0; 1015 IADDR UNUSED pc = abuf->addr; 1016 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1017 1018 { 1019 SI opval = MULSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])); 1020 CPU (h_gr[FLD (f_r2)]) = opval; 1021 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1022 } 1023 1024 #undef FLD 1025 } 1026 NEXT (vpc); 1027 1028 CASE (sem, INSN_MULI) : /* muli $r1,$r0,$imm */ 1029 { 1030 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1031 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1032 #define FLD(f) abuf->fields.sfmt_addi.f 1033 int UNUSED written = 0; 1034 IADDR UNUSED pc = abuf->addr; 1035 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1036 1037 { 1038 SI opval = MULSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))); 1039 CPU (h_gr[FLD (f_r1)]) = opval; 1040 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1041 } 1042 1043 #undef FLD 1044 } 1045 NEXT (vpc); 1046 1047 CASE (sem, INSN_NOR) : /* nor $r2,$r0,$r1 */ 1048 { 1049 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1050 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1051 #define FLD(f) abuf->fields.sfmt_user.f 1052 int UNUSED written = 0; 1053 IADDR UNUSED pc = abuf->addr; 1054 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1055 1056 { 1057 SI opval = INVSI (ORSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))); 1058 CPU (h_gr[FLD (f_r2)]) = opval; 1059 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1060 } 1061 1062 #undef FLD 1063 } 1064 NEXT (vpc); 1065 1066 CASE (sem, INSN_NORI) : /* nori $r1,$r0,$uimm */ 1067 { 1068 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1069 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1070 #define FLD(f) abuf->fields.sfmt_andi.f 1071 int UNUSED written = 0; 1072 IADDR UNUSED pc = abuf->addr; 1073 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1074 1075 { 1076 SI opval = INVSI (ORSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)))); 1077 CPU (h_gr[FLD (f_r1)]) = opval; 1078 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1079 } 1080 1081 #undef FLD 1082 } 1083 NEXT (vpc); 1084 1085 CASE (sem, INSN_OR) : /* or $r2,$r0,$r1 */ 1086 { 1087 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1088 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1089 #define FLD(f) abuf->fields.sfmt_user.f 1090 int UNUSED written = 0; 1091 IADDR UNUSED pc = abuf->addr; 1092 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1093 1094 { 1095 SI opval = ORSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])); 1096 CPU (h_gr[FLD (f_r2)]) = opval; 1097 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1098 } 1099 1100 #undef FLD 1101 } 1102 NEXT (vpc); 1103 1104 CASE (sem, INSN_ORI) : /* ori $r1,$r0,$lo16 */ 1105 { 1106 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1107 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1108 #define FLD(f) abuf->fields.sfmt_andi.f 1109 int UNUSED written = 0; 1110 IADDR UNUSED pc = abuf->addr; 1111 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1112 1113 { 1114 SI opval = ORSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm))); 1115 CPU (h_gr[FLD (f_r1)]) = opval; 1116 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1117 } 1118 1119 #undef FLD 1120 } 1121 NEXT (vpc); 1122 1123 CASE (sem, INSN_ORHII) : /* orhi $r1,$r0,$hi16 */ 1124 { 1125 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1126 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1127 #define FLD(f) abuf->fields.sfmt_andi.f 1128 int UNUSED written = 0; 1129 IADDR UNUSED pc = abuf->addr; 1130 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1131 1132 { 1133 SI opval = ORSI (CPU (h_gr[FLD (f_r0)]), SLLSI (FLD (f_uimm), 16)); 1134 CPU (h_gr[FLD (f_r1)]) = opval; 1135 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1136 } 1137 1138 #undef FLD 1139 } 1140 NEXT (vpc); 1141 1142 CASE (sem, INSN_RCSR) : /* rcsr $r2,$csr */ 1143 { 1144 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1145 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1146 #define FLD(f) abuf->fields.sfmt_rcsr.f 1147 int UNUSED written = 0; 1148 IADDR UNUSED pc = abuf->addr; 1149 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1150 1151 { 1152 SI opval = CPU (h_csr[FLD (f_csr)]); 1153 CPU (h_gr[FLD (f_r2)]) = opval; 1154 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1155 } 1156 1157 #undef FLD 1158 } 1159 NEXT (vpc); 1160 1161 CASE (sem, INSN_SB) : /* sb ($r0+$imm),$r1 */ 1162 { 1163 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1164 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1165 #define FLD(f) abuf->fields.sfmt_addi.f 1166 int UNUSED written = 0; 1167 IADDR UNUSED pc = abuf->addr; 1168 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1169 1170 { 1171 QI opval = CPU (h_gr[FLD (f_r1)]); 1172 SETMEMQI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval); 1173 CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 1174 } 1175 1176 #undef FLD 1177 } 1178 NEXT (vpc); 1179 1180 CASE (sem, INSN_SEXTB) : /* sextb $r2,$r0 */ 1181 { 1182 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1183 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1184 #define FLD(f) abuf->fields.sfmt_user.f 1185 int UNUSED written = 0; 1186 IADDR UNUSED pc = abuf->addr; 1187 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1188 1189 { 1190 SI opval = EXTQISI (TRUNCSIQI (CPU (h_gr[FLD (f_r0)]))); 1191 CPU (h_gr[FLD (f_r2)]) = opval; 1192 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1193 } 1194 1195 #undef FLD 1196 } 1197 NEXT (vpc); 1198 1199 CASE (sem, INSN_SEXTH) : /* sexth $r2,$r0 */ 1200 { 1201 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1202 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1203 #define FLD(f) abuf->fields.sfmt_user.f 1204 int UNUSED written = 0; 1205 IADDR UNUSED pc = abuf->addr; 1206 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1207 1208 { 1209 SI opval = EXTHISI (TRUNCSIHI (CPU (h_gr[FLD (f_r0)]))); 1210 CPU (h_gr[FLD (f_r2)]) = opval; 1211 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1212 } 1213 1214 #undef FLD 1215 } 1216 NEXT (vpc); 1217 1218 CASE (sem, INSN_SH) : /* sh ($r0+$imm),$r1 */ 1219 { 1220 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1221 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1222 #define FLD(f) abuf->fields.sfmt_addi.f 1223 int UNUSED written = 0; 1224 IADDR UNUSED pc = abuf->addr; 1225 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1226 1227 { 1228 HI opval = CPU (h_gr[FLD (f_r1)]); 1229 SETMEMHI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval); 1230 CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 1231 } 1232 1233 #undef FLD 1234 } 1235 NEXT (vpc); 1236 1237 CASE (sem, INSN_SL) : /* sl $r2,$r0,$r1 */ 1238 { 1239 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1240 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1241 #define FLD(f) abuf->fields.sfmt_user.f 1242 int UNUSED written = 0; 1243 IADDR UNUSED pc = abuf->addr; 1244 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1245 1246 { 1247 SI opval = SLLSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])); 1248 CPU (h_gr[FLD (f_r2)]) = opval; 1249 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1250 } 1251 1252 #undef FLD 1253 } 1254 NEXT (vpc); 1255 1256 CASE (sem, INSN_SLI) : /* sli $r1,$r0,$imm */ 1257 { 1258 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1259 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1260 #define FLD(f) abuf->fields.sfmt_addi.f 1261 int UNUSED written = 0; 1262 IADDR UNUSED pc = abuf->addr; 1263 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1264 1265 { 1266 SI opval = SLLSI (CPU (h_gr[FLD (f_r0)]), FLD (f_imm)); 1267 CPU (h_gr[FLD (f_r1)]) = opval; 1268 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1269 } 1270 1271 #undef FLD 1272 } 1273 NEXT (vpc); 1274 1275 CASE (sem, INSN_SR) : /* sr $r2,$r0,$r1 */ 1276 { 1277 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1278 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1279 #define FLD(f) abuf->fields.sfmt_user.f 1280 int UNUSED written = 0; 1281 IADDR UNUSED pc = abuf->addr; 1282 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1283 1284 { 1285 SI opval = SRASI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])); 1286 CPU (h_gr[FLD (f_r2)]) = opval; 1287 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1288 } 1289 1290 #undef FLD 1291 } 1292 NEXT (vpc); 1293 1294 CASE (sem, INSN_SRI) : /* sri $r1,$r0,$imm */ 1295 { 1296 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1297 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1298 #define FLD(f) abuf->fields.sfmt_addi.f 1299 int UNUSED written = 0; 1300 IADDR UNUSED pc = abuf->addr; 1301 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1302 1303 { 1304 SI opval = SRASI (CPU (h_gr[FLD (f_r0)]), FLD (f_imm)); 1305 CPU (h_gr[FLD (f_r1)]) = opval; 1306 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1307 } 1308 1309 #undef FLD 1310 } 1311 NEXT (vpc); 1312 1313 CASE (sem, INSN_SRU) : /* sru $r2,$r0,$r1 */ 1314 { 1315 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1316 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1317 #define FLD(f) abuf->fields.sfmt_user.f 1318 int UNUSED written = 0; 1319 IADDR UNUSED pc = abuf->addr; 1320 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1321 1322 { 1323 SI opval = SRLSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])); 1324 CPU (h_gr[FLD (f_r2)]) = opval; 1325 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1326 } 1327 1328 #undef FLD 1329 } 1330 NEXT (vpc); 1331 1332 CASE (sem, INSN_SRUI) : /* srui $r1,$r0,$imm */ 1333 { 1334 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1335 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1336 #define FLD(f) abuf->fields.sfmt_addi.f 1337 int UNUSED written = 0; 1338 IADDR UNUSED pc = abuf->addr; 1339 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1340 1341 { 1342 SI opval = SRLSI (CPU (h_gr[FLD (f_r0)]), FLD (f_imm)); 1343 CPU (h_gr[FLD (f_r1)]) = opval; 1344 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1345 } 1346 1347 #undef FLD 1348 } 1349 NEXT (vpc); 1350 1351 CASE (sem, INSN_SUB) : /* sub $r2,$r0,$r1 */ 1352 { 1353 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1354 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1355 #define FLD(f) abuf->fields.sfmt_user.f 1356 int UNUSED written = 0; 1357 IADDR UNUSED pc = abuf->addr; 1358 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1359 1360 { 1361 SI opval = SUBSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])); 1362 CPU (h_gr[FLD (f_r2)]) = opval; 1363 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1364 } 1365 1366 #undef FLD 1367 } 1368 NEXT (vpc); 1369 1370 CASE (sem, INSN_SW) : /* sw ($r0+$imm),$r1 */ 1371 { 1372 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1373 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1374 #define FLD(f) abuf->fields.sfmt_addi.f 1375 int UNUSED written = 0; 1376 IADDR UNUSED pc = abuf->addr; 1377 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1378 1379 { 1380 SI opval = CPU (h_gr[FLD (f_r1)]); 1381 SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval); 1382 CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 1383 } 1384 1385 #undef FLD 1386 } 1387 NEXT (vpc); 1388 1389 CASE (sem, INSN_USER) : /* user $r2,$r0,$r1,$user */ 1390 { 1391 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1392 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1393 #define FLD(f) abuf->fields.sfmt_user.f 1394 int UNUSED written = 0; 1395 IADDR UNUSED pc = abuf->addr; 1396 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1397 1398 { 1399 SI opval = lm32bf_user_insn (current_cpu, CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]), FLD (f_user)); 1400 CPU (h_gr[FLD (f_r2)]) = opval; 1401 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1402 } 1403 1404 #undef FLD 1405 } 1406 NEXT (vpc); 1407 1408 CASE (sem, INSN_WCSR) : /* wcsr $csr,$r1 */ 1409 { 1410 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1411 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1412 #define FLD(f) abuf->fields.sfmt_wcsr.f 1413 int UNUSED written = 0; 1414 IADDR UNUSED pc = abuf->addr; 1415 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1416 1417 lm32bf_wcsr_insn (current_cpu, FLD (f_csr), CPU (h_gr[FLD (f_r1)])); 1418 1419 #undef FLD 1420 } 1421 NEXT (vpc); 1422 1423 CASE (sem, INSN_XOR) : /* xor $r2,$r0,$r1 */ 1424 { 1425 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1426 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1427 #define FLD(f) abuf->fields.sfmt_user.f 1428 int UNUSED written = 0; 1429 IADDR UNUSED pc = abuf->addr; 1430 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1431 1432 { 1433 SI opval = XORSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])); 1434 CPU (h_gr[FLD (f_r2)]) = opval; 1435 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1436 } 1437 1438 #undef FLD 1439 } 1440 NEXT (vpc); 1441 1442 CASE (sem, INSN_XORI) : /* xori $r1,$r0,$uimm */ 1443 { 1444 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1445 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1446 #define FLD(f) abuf->fields.sfmt_andi.f 1447 int UNUSED written = 0; 1448 IADDR UNUSED pc = abuf->addr; 1449 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1450 1451 { 1452 SI opval = XORSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm))); 1453 CPU (h_gr[FLD (f_r1)]) = opval; 1454 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1455 } 1456 1457 #undef FLD 1458 } 1459 NEXT (vpc); 1460 1461 CASE (sem, INSN_XNOR) : /* xnor $r2,$r0,$r1 */ 1462 { 1463 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1464 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1465 #define FLD(f) abuf->fields.sfmt_user.f 1466 int UNUSED written = 0; 1467 IADDR UNUSED pc = abuf->addr; 1468 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1469 1470 { 1471 SI opval = INVSI (XORSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))); 1472 CPU (h_gr[FLD (f_r2)]) = opval; 1473 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1474 } 1475 1476 #undef FLD 1477 } 1478 NEXT (vpc); 1479 1480 CASE (sem, INSN_XNORI) : /* xnori $r1,$r0,$uimm */ 1481 { 1482 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1483 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1484 #define FLD(f) abuf->fields.sfmt_andi.f 1485 int UNUSED written = 0; 1486 IADDR UNUSED pc = abuf->addr; 1487 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1488 1489 { 1490 SI opval = INVSI (XORSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)))); 1491 CPU (h_gr[FLD (f_r1)]) = opval; 1492 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1493 } 1494 1495 #undef FLD 1496 } 1497 NEXT (vpc); 1498 1499 CASE (sem, INSN_BREAK) : /* break */ 1500 { 1501 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1502 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1503 #define FLD(f) abuf->fields.sfmt_empty.f 1504 int UNUSED written = 0; 1505 IADDR UNUSED pc = abuf->addr; 1506 SEM_BRANCH_INIT 1507 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1508 1509 { 1510 USI opval = lm32bf_break_insn (current_cpu, pc); 1511 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); 1512 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1513 } 1514 1515 SEM_BRANCH_FINI (vpc); 1516 #undef FLD 1517 } 1518 NEXT (vpc); 1519 1520 CASE (sem, INSN_SCALL) : /* scall */ 1521 { 1522 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1523 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1524 #define FLD(f) abuf->fields.sfmt_empty.f 1525 int UNUSED written = 0; 1526 IADDR UNUSED pc = abuf->addr; 1527 SEM_BRANCH_INIT 1528 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1529 1530 { 1531 USI opval = lm32bf_scall_insn (current_cpu, pc); 1532 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); 1533 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1534 } 1535 1536 SEM_BRANCH_FINI (vpc); 1537 #undef FLD 1538 } 1539 NEXT (vpc); 1540 1541 1542 } 1543 ENDSWITCH (sem) /* End of semantic switch. */ 1544 1545 /* At this point `vpc' contains the next insn to execute. */ 1546 } 1547 1548 #undef DEFINE_SWITCH 1549 #endif /* DEFINE_SWITCH */ 1550