1 /* Lattice Mico32 UART model. 2 Contributed by Jon Beniston <jon@beniston.com> 3 4 Copyright (C) 2009-2023 Free Software Foundation, Inc. 5 6 This file is part of GDB. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21 /* This must come before any other includes. */ 22 #include "defs.h" 23 24 #include "sim-main.h" 25 #include "hw-main.h" 26 #include "sim-assert.h" 27 28 #include <stdio.h> 29 #include <sys/select.h> 30 #include <sys/time.h> 31 32 struct lm32uart 33 { 34 unsigned base; /* Base address of this UART. */ 35 unsigned limit; /* Limit address of this UART. */ 36 unsigned char rbr; 37 unsigned char thr; 38 unsigned char ier; 39 unsigned char iir; 40 unsigned char lcr; 41 unsigned char mcr; 42 unsigned char lsr; 43 unsigned char msr; 44 unsigned char div; 45 struct hw_event *event; 46 }; 47 48 /* UART registers. */ 49 50 #define LM32_UART_RBR 0x0 51 #define LM32_UART_THR 0x0 52 #define LM32_UART_IER 0x4 53 #define LM32_UART_IIR 0x8 54 #define LM32_UART_LCR 0xc 55 #define LM32_UART_MCR 0x10 56 #define LM32_UART_LSR 0x14 57 #define LM32_UART_MSR 0x18 58 #define LM32_UART_DIV 0x1c 59 60 #define LM32_UART_IER_RX_INT 0x1 61 #define LM32_UART_IER_TX_INT 0x2 62 63 #define MICOUART_IIR_TXRDY 0x2 64 #define MICOUART_IIR_RXRDY 0x4 65 66 #define LM32_UART_LSR_RX_RDY 0x01 67 #define LM32_UART_LSR_TX_RDY 0x20 68 69 #define LM32_UART_LCR_WLS_MASK 0x3 70 #define LM32_UART_LCR_WLS_5 0x0 71 #define LM32_UART_LCR_WLS_6 0x1 72 #define LM32_UART_LCR_WLS_7 0x2 73 #define LM32_UART_LCR_WLS_8 0x3 74 75 /* UART ports. */ 76 77 enum 78 { 79 INT_PORT 80 }; 81 82 static const struct hw_port_descriptor lm32uart_ports[] = { 83 {"int", INT_PORT, 0, output_port}, 84 {} 85 }; 86 87 static void 88 do_uart_tx_event (struct hw *me, void *data) 89 { 90 struct lm32uart *uart = hw_data (me); 91 char c; 92 93 /* Generate interrupt when transmission is complete. */ 94 if (uart->ier & LM32_UART_IER_TX_INT) 95 { 96 /* Generate interrupt */ 97 hw_port_event (me, INT_PORT, 1); 98 } 99 100 /* Indicate which interrupt has occured. */ 101 uart->iir = MICOUART_IIR_TXRDY; 102 103 /* Indicate THR is empty. */ 104 uart->lsr |= LM32_UART_LSR_TX_RDY; 105 106 /* Output the character in the THR. */ 107 c = (char) uart->thr; 108 109 /* WLS field in LCR register specifies the number of bits to output. */ 110 switch (uart->lcr & LM32_UART_LCR_WLS_MASK) 111 { 112 case LM32_UART_LCR_WLS_5: 113 c &= 0x1f; 114 break; 115 case LM32_UART_LCR_WLS_6: 116 c &= 0x3f; 117 break; 118 case LM32_UART_LCR_WLS_7: 119 c &= 0x7f; 120 break; 121 } 122 printf ("%c", c); 123 } 124 125 static unsigned 126 lm32uart_io_write_buffer (struct hw *me, 127 const void *source, 128 int space, unsigned_word base, unsigned nr_bytes) 129 { 130 struct lm32uart *uart = hw_data (me); 131 int uart_reg; 132 const unsigned char *source_bytes = source; 133 int value = 0; 134 135 HW_TRACE ((me, "write to 0x%08lx length %d with 0x%x", (long) base, 136 (int) nr_bytes, value)); 137 138 if (nr_bytes == 4) 139 value = (source_bytes[0] << 24) 140 | (source_bytes[1] << 16) | (source_bytes[2] << 8) | (source_bytes[3]); 141 else 142 hw_abort (me, "write of unsupported number of bytes: %d.", nr_bytes); 143 144 uart_reg = base - uart->base; 145 146 switch (uart_reg) 147 { 148 case LM32_UART_THR: 149 /* Buffer the character to output. */ 150 uart->thr = value; 151 152 /* Indicate the THR is full. */ 153 uart->lsr &= ~LM32_UART_LSR_TX_RDY; 154 155 /* deassert interrupt when IER is loaded. */ 156 uart->iir &= ~MICOUART_IIR_TXRDY; 157 158 /* schedule an event to output the character. */ 159 hw_event_queue_schedule (me, 1, do_uart_tx_event, 0); 160 161 break; 162 case LM32_UART_IER: 163 uart->ier = value; 164 if ((value & LM32_UART_IER_TX_INT) 165 && (uart->lsr & LM32_UART_LSR_TX_RDY)) 166 { 167 /* hw_event_queue_schedule (me, 1, do_uart_tx_event, 0); */ 168 uart->lsr |= LM32_UART_LSR_TX_RDY; 169 uart->iir |= MICOUART_IIR_TXRDY; 170 hw_port_event (me, INT_PORT, 1); 171 } 172 else if ((value & LM32_UART_IER_TX_INT) == 0) 173 { 174 hw_port_event (me, INT_PORT, 0); 175 } 176 break; 177 case LM32_UART_IIR: 178 uart->iir = value; 179 break; 180 case LM32_UART_LCR: 181 uart->lcr = value; 182 break; 183 case LM32_UART_MCR: 184 uart->mcr = value; 185 break; 186 case LM32_UART_LSR: 187 uart->lsr = value; 188 break; 189 case LM32_UART_MSR: 190 uart->msr = value; 191 break; 192 case LM32_UART_DIV: 193 uart->div = value; 194 break; 195 default: 196 hw_abort (me, "write to invalid register address: 0x%x.", uart_reg); 197 } 198 199 return nr_bytes; 200 } 201 202 static unsigned 203 lm32uart_io_read_buffer (struct hw *me, 204 void *dest, 205 int space, unsigned_word base, unsigned nr_bytes) 206 { 207 struct lm32uart *uart = hw_data (me); 208 int uart_reg; 209 int value; 210 unsigned char *dest_bytes = dest; 211 fd_set fd; 212 struct timeval tv; 213 214 HW_TRACE ((me, "read 0x%08lx length %d", (long) base, (int) nr_bytes)); 215 216 uart_reg = base - uart->base; 217 218 switch (uart_reg) 219 { 220 case LM32_UART_RBR: 221 value = getchar (); 222 uart->lsr &= ~LM32_UART_LSR_RX_RDY; 223 break; 224 case LM32_UART_IER: 225 value = uart->ier; 226 break; 227 case LM32_UART_IIR: 228 value = uart->iir; 229 break; 230 case LM32_UART_LCR: 231 value = uart->lcr; 232 break; 233 case LM32_UART_MCR: 234 value = uart->mcr; 235 break; 236 case LM32_UART_LSR: 237 /* Check to see if any data waiting in stdin. */ 238 FD_ZERO (&fd); 239 FD_SET (fileno (stdin), &fd); 240 tv.tv_sec = 0; 241 tv.tv_usec = 1; 242 if (select (fileno (stdin) + 1, &fd, NULL, NULL, &tv)) 243 uart->lsr |= LM32_UART_LSR_RX_RDY; 244 value = uart->lsr; 245 break; 246 case LM32_UART_MSR: 247 value = uart->msr; 248 break; 249 case LM32_UART_DIV: 250 value = uart->div; 251 break; 252 default: 253 hw_abort (me, "read from invalid register address: 0x%x.", uart_reg); 254 } 255 256 if (nr_bytes == 4) 257 { 258 dest_bytes[0] = value >> 24; 259 dest_bytes[1] = value >> 16; 260 dest_bytes[2] = value >> 8; 261 dest_bytes[3] = value; 262 } 263 else 264 hw_abort (me, "read of unsupported number of bytes: %d", nr_bytes); 265 266 return nr_bytes; 267 } 268 269 static void 270 attach_lm32uart_regs (struct hw *me, struct lm32uart *uart) 271 { 272 unsigned_word attach_address; 273 int attach_space; 274 unsigned attach_size; 275 reg_property_spec reg; 276 277 if (hw_find_property (me, "reg") == NULL) 278 hw_abort (me, "Missing \"reg\" property"); 279 if (!hw_find_reg_array_property (me, "reg", 0, ®)) 280 hw_abort (me, "\"reg\" property must contain three addr/size entries"); 281 hw_unit_address_to_attach_address (hw_parent (me), 282 ®.address, 283 &attach_space, &attach_address, me); 284 uart->base = attach_address; 285 hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); 286 uart->limit = attach_address + (attach_size - 1); 287 hw_attach_address (hw_parent (me), 288 0, attach_space, attach_address, attach_size, me); 289 } 290 291 static void 292 lm32uart_finish (struct hw *me) 293 { 294 struct lm32uart *uart; 295 int i; 296 297 uart = HW_ZALLOC (me, struct lm32uart); 298 set_hw_data (me, uart); 299 set_hw_io_read_buffer (me, lm32uart_io_read_buffer); 300 set_hw_io_write_buffer (me, lm32uart_io_write_buffer); 301 set_hw_ports (me, lm32uart_ports); 302 303 /* Attach ourself to our parent bus. */ 304 attach_lm32uart_regs (me, uart); 305 306 /* Initialize the UART. */ 307 uart->rbr = 0; 308 uart->thr = 0; 309 uart->ier = 0; 310 uart->iir = 0; 311 uart->lcr = 0; 312 uart->mcr = 0; 313 uart->lsr = LM32_UART_LSR_TX_RDY; 314 uart->msr = 0; 315 uart->div = 0; /* By setting to zero, characters are output immediately. */ 316 } 317 318 const struct hw_descriptor dv_lm32uart_descriptor[] = { 319 {"lm32uart", lm32uart_finish,}, 320 {NULL}, 321 }; 322