1 /* Simulator instruction decoder for lm32bf. 2 3 THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5 Copyright 1996-2010 Free Software Foundation, Inc. 6 7 This file is part of the GNU simulators. 8 9 This file is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License along 20 with this program; if not, write to the Free Software Foundation, Inc., 21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 22 23 */ 24 25 #define WANT_CPU lm32bf 26 #define WANT_CPU_LM32BF 27 28 #include "sim-main.h" 29 #include "sim-assert.h" 30 31 /* The instruction descriptor array. 32 This is computed at runtime. Space for it is not malloc'd to save a 33 teensy bit of cpu in the decoder. Moving it to malloc space is trivial 34 but won't be done until necessary (we don't currently support the runtime 35 addition of instructions nor an SMP machine with different cpus). */ 36 static IDESC lm32bf_insn_data[LM32BF_INSN__MAX]; 37 38 /* Commas between elements are contained in the macros. 39 Some of these are conditionally compiled out. */ 40 41 static const struct insn_sem lm32bf_insn_sem[] = 42 { 43 { VIRTUAL_INSN_X_INVALID, LM32BF_INSN_X_INVALID, LM32BF_SFMT_EMPTY }, 44 { VIRTUAL_INSN_X_AFTER, LM32BF_INSN_X_AFTER, LM32BF_SFMT_EMPTY }, 45 { VIRTUAL_INSN_X_BEFORE, LM32BF_INSN_X_BEFORE, LM32BF_SFMT_EMPTY }, 46 { VIRTUAL_INSN_X_CTI_CHAIN, LM32BF_INSN_X_CTI_CHAIN, LM32BF_SFMT_EMPTY }, 47 { VIRTUAL_INSN_X_CHAIN, LM32BF_INSN_X_CHAIN, LM32BF_SFMT_EMPTY }, 48 { VIRTUAL_INSN_X_BEGIN, LM32BF_INSN_X_BEGIN, LM32BF_SFMT_EMPTY }, 49 { LM32_INSN_ADD, LM32BF_INSN_ADD, LM32BF_SFMT_ADD }, 50 { LM32_INSN_ADDI, LM32BF_INSN_ADDI, LM32BF_SFMT_ADDI }, 51 { LM32_INSN_AND, LM32BF_INSN_AND, LM32BF_SFMT_ADD }, 52 { LM32_INSN_ANDI, LM32BF_INSN_ANDI, LM32BF_SFMT_ANDI }, 53 { LM32_INSN_ANDHII, LM32BF_INSN_ANDHII, LM32BF_SFMT_ANDHII }, 54 { LM32_INSN_B, LM32BF_INSN_B, LM32BF_SFMT_B }, 55 { LM32_INSN_BI, LM32BF_INSN_BI, LM32BF_SFMT_BI }, 56 { LM32_INSN_BE, LM32BF_INSN_BE, LM32BF_SFMT_BE }, 57 { LM32_INSN_BG, LM32BF_INSN_BG, LM32BF_SFMT_BE }, 58 { LM32_INSN_BGE, LM32BF_INSN_BGE, LM32BF_SFMT_BE }, 59 { LM32_INSN_BGEU, LM32BF_INSN_BGEU, LM32BF_SFMT_BE }, 60 { LM32_INSN_BGU, LM32BF_INSN_BGU, LM32BF_SFMT_BE }, 61 { LM32_INSN_BNE, LM32BF_INSN_BNE, LM32BF_SFMT_BE }, 62 { LM32_INSN_CALL, LM32BF_INSN_CALL, LM32BF_SFMT_CALL }, 63 { LM32_INSN_CALLI, LM32BF_INSN_CALLI, LM32BF_SFMT_CALLI }, 64 { LM32_INSN_CMPE, LM32BF_INSN_CMPE, LM32BF_SFMT_ADD }, 65 { LM32_INSN_CMPEI, LM32BF_INSN_CMPEI, LM32BF_SFMT_ADDI }, 66 { LM32_INSN_CMPG, LM32BF_INSN_CMPG, LM32BF_SFMT_ADD }, 67 { LM32_INSN_CMPGI, LM32BF_INSN_CMPGI, LM32BF_SFMT_ADDI }, 68 { LM32_INSN_CMPGE, LM32BF_INSN_CMPGE, LM32BF_SFMT_ADD }, 69 { LM32_INSN_CMPGEI, LM32BF_INSN_CMPGEI, LM32BF_SFMT_ADDI }, 70 { LM32_INSN_CMPGEU, LM32BF_INSN_CMPGEU, LM32BF_SFMT_ADD }, 71 { LM32_INSN_CMPGEUI, LM32BF_INSN_CMPGEUI, LM32BF_SFMT_ANDI }, 72 { LM32_INSN_CMPGU, LM32BF_INSN_CMPGU, LM32BF_SFMT_ADD }, 73 { LM32_INSN_CMPGUI, LM32BF_INSN_CMPGUI, LM32BF_SFMT_ANDI }, 74 { LM32_INSN_CMPNE, LM32BF_INSN_CMPNE, LM32BF_SFMT_ADD }, 75 { LM32_INSN_CMPNEI, LM32BF_INSN_CMPNEI, LM32BF_SFMT_ADDI }, 76 { LM32_INSN_DIVU, LM32BF_INSN_DIVU, LM32BF_SFMT_DIVU }, 77 { LM32_INSN_LB, LM32BF_INSN_LB, LM32BF_SFMT_LB }, 78 { LM32_INSN_LBU, LM32BF_INSN_LBU, LM32BF_SFMT_LB }, 79 { LM32_INSN_LH, LM32BF_INSN_LH, LM32BF_SFMT_LH }, 80 { LM32_INSN_LHU, LM32BF_INSN_LHU, LM32BF_SFMT_LH }, 81 { LM32_INSN_LW, LM32BF_INSN_LW, LM32BF_SFMT_LW }, 82 { LM32_INSN_MODU, LM32BF_INSN_MODU, LM32BF_SFMT_DIVU }, 83 { LM32_INSN_MUL, LM32BF_INSN_MUL, LM32BF_SFMT_ADD }, 84 { LM32_INSN_MULI, LM32BF_INSN_MULI, LM32BF_SFMT_ADDI }, 85 { LM32_INSN_NOR, LM32BF_INSN_NOR, LM32BF_SFMT_ADD }, 86 { LM32_INSN_NORI, LM32BF_INSN_NORI, LM32BF_SFMT_ANDI }, 87 { LM32_INSN_OR, LM32BF_INSN_OR, LM32BF_SFMT_ADD }, 88 { LM32_INSN_ORI, LM32BF_INSN_ORI, LM32BF_SFMT_ORI }, 89 { LM32_INSN_ORHII, LM32BF_INSN_ORHII, LM32BF_SFMT_ANDHII }, 90 { LM32_INSN_RCSR, LM32BF_INSN_RCSR, LM32BF_SFMT_RCSR }, 91 { LM32_INSN_SB, LM32BF_INSN_SB, LM32BF_SFMT_SB }, 92 { LM32_INSN_SEXTB, LM32BF_INSN_SEXTB, LM32BF_SFMT_SEXTB }, 93 { LM32_INSN_SEXTH, LM32BF_INSN_SEXTH, LM32BF_SFMT_SEXTB }, 94 { LM32_INSN_SH, LM32BF_INSN_SH, LM32BF_SFMT_SH }, 95 { LM32_INSN_SL, LM32BF_INSN_SL, LM32BF_SFMT_ADD }, 96 { LM32_INSN_SLI, LM32BF_INSN_SLI, LM32BF_SFMT_ADDI }, 97 { LM32_INSN_SR, LM32BF_INSN_SR, LM32BF_SFMT_ADD }, 98 { LM32_INSN_SRI, LM32BF_INSN_SRI, LM32BF_SFMT_ADDI }, 99 { LM32_INSN_SRU, LM32BF_INSN_SRU, LM32BF_SFMT_ADD }, 100 { LM32_INSN_SRUI, LM32BF_INSN_SRUI, LM32BF_SFMT_ADDI }, 101 { LM32_INSN_SUB, LM32BF_INSN_SUB, LM32BF_SFMT_ADD }, 102 { LM32_INSN_SW, LM32BF_INSN_SW, LM32BF_SFMT_SW }, 103 { LM32_INSN_USER, LM32BF_INSN_USER, LM32BF_SFMT_USER }, 104 { LM32_INSN_WCSR, LM32BF_INSN_WCSR, LM32BF_SFMT_WCSR }, 105 { LM32_INSN_XOR, LM32BF_INSN_XOR, LM32BF_SFMT_ADD }, 106 { LM32_INSN_XORI, LM32BF_INSN_XORI, LM32BF_SFMT_ANDI }, 107 { LM32_INSN_XNOR, LM32BF_INSN_XNOR, LM32BF_SFMT_ADD }, 108 { LM32_INSN_XNORI, LM32BF_INSN_XNORI, LM32BF_SFMT_ANDI }, 109 { LM32_INSN_BREAK, LM32BF_INSN_BREAK, LM32BF_SFMT_BREAK }, 110 { LM32_INSN_SCALL, LM32BF_INSN_SCALL, LM32BF_SFMT_BREAK }, 111 }; 112 113 static const struct insn_sem lm32bf_insn_sem_invalid = 114 { 115 VIRTUAL_INSN_X_INVALID, LM32BF_INSN_X_INVALID, LM32BF_SFMT_EMPTY 116 }; 117 118 /* Initialize an IDESC from the compile-time computable parts. */ 119 120 static INLINE void 121 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) 122 { 123 const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries; 124 125 id->num = t->index; 126 id->sfmt = t->sfmt; 127 if ((int) t->type <= 0) 128 id->idata = & cgen_virtual_insn_table[- (int) t->type]; 129 else 130 id->idata = & insn_table[t->type]; 131 id->attrs = CGEN_INSN_ATTRS (id->idata); 132 /* Oh my god, a magic number. */ 133 id->length = CGEN_INSN_BITSIZE (id->idata) / 8; 134 135 #if WITH_PROFILE_MODEL_P 136 id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index]; 137 { 138 SIM_DESC sd = CPU_STATE (cpu); 139 SIM_ASSERT (t->index == id->timing->num); 140 } 141 #endif 142 143 /* Semantic pointers are initialized elsewhere. */ 144 } 145 146 /* Initialize the instruction descriptor table. */ 147 148 void 149 lm32bf_init_idesc_table (SIM_CPU *cpu) 150 { 151 IDESC *id,*tabend; 152 const struct insn_sem *t,*tend; 153 int tabsize = LM32BF_INSN__MAX; 154 IDESC *table = lm32bf_insn_data; 155 156 memset (table, 0, tabsize * sizeof (IDESC)); 157 158 /* First set all entries to the `invalid insn'. */ 159 t = & lm32bf_insn_sem_invalid; 160 for (id = table, tabend = table + tabsize; id < tabend; ++id) 161 init_idesc (cpu, id, t); 162 163 /* Now fill in the values for the chosen cpu. */ 164 for (t = lm32bf_insn_sem, tend = t + sizeof (lm32bf_insn_sem) / sizeof (*t); 165 t != tend; ++t) 166 { 167 init_idesc (cpu, & table[t->index], t); 168 } 169 170 /* Link the IDESC table into the cpu. */ 171 CPU_IDESC (cpu) = table; 172 } 173 174 /* Given an instruction, return a pointer to its IDESC entry. */ 175 176 const IDESC * 177 lm32bf_decode (SIM_CPU *current_cpu, IADDR pc, 178 CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn, 179 ARGBUF *abuf) 180 { 181 /* Result of decoder. */ 182 LM32BF_INSN_TYPE itype; 183 184 { 185 CGEN_INSN_WORD insn = base_insn; 186 187 { 188 unsigned int val = (((insn >> 26) & (63 << 0))); 189 switch (val) 190 { 191 case 0 : itype = LM32BF_INSN_SRUI; goto extract_sfmt_addi; 192 case 1 : itype = LM32BF_INSN_NORI; goto extract_sfmt_andi; 193 case 2 : itype = LM32BF_INSN_MULI; goto extract_sfmt_addi; 194 case 3 : itype = LM32BF_INSN_SH; goto extract_sfmt_sh; 195 case 4 : itype = LM32BF_INSN_LB; goto extract_sfmt_lb; 196 case 5 : itype = LM32BF_INSN_SRI; goto extract_sfmt_addi; 197 case 6 : itype = LM32BF_INSN_XORI; goto extract_sfmt_andi; 198 case 7 : itype = LM32BF_INSN_LH; goto extract_sfmt_lh; 199 case 8 : itype = LM32BF_INSN_ANDI; goto extract_sfmt_andi; 200 case 9 : itype = LM32BF_INSN_XNORI; goto extract_sfmt_andi; 201 case 10 : itype = LM32BF_INSN_LW; goto extract_sfmt_lw; 202 case 11 : itype = LM32BF_INSN_LHU; goto extract_sfmt_lh; 203 case 12 : itype = LM32BF_INSN_SB; goto extract_sfmt_sb; 204 case 13 : itype = LM32BF_INSN_ADDI; goto extract_sfmt_addi; 205 case 14 : itype = LM32BF_INSN_ORI; goto extract_sfmt_ori; 206 case 15 : itype = LM32BF_INSN_SLI; goto extract_sfmt_addi; 207 case 16 : itype = LM32BF_INSN_LBU; goto extract_sfmt_lb; 208 case 17 : itype = LM32BF_INSN_BE; goto extract_sfmt_be; 209 case 18 : itype = LM32BF_INSN_BG; goto extract_sfmt_be; 210 case 19 : itype = LM32BF_INSN_BGE; goto extract_sfmt_be; 211 case 20 : itype = LM32BF_INSN_BGEU; goto extract_sfmt_be; 212 case 21 : itype = LM32BF_INSN_BGU; goto extract_sfmt_be; 213 case 22 : itype = LM32BF_INSN_SW; goto extract_sfmt_sw; 214 case 23 : itype = LM32BF_INSN_BNE; goto extract_sfmt_be; 215 case 24 : itype = LM32BF_INSN_ANDHII; goto extract_sfmt_andhii; 216 case 25 : itype = LM32BF_INSN_CMPEI; goto extract_sfmt_addi; 217 case 26 : itype = LM32BF_INSN_CMPGI; goto extract_sfmt_addi; 218 case 27 : itype = LM32BF_INSN_CMPGEI; goto extract_sfmt_addi; 219 case 28 : itype = LM32BF_INSN_CMPGEUI; goto extract_sfmt_andi; 220 case 29 : itype = LM32BF_INSN_CMPGUI; goto extract_sfmt_andi; 221 case 30 : itype = LM32BF_INSN_ORHII; goto extract_sfmt_andhii; 222 case 31 : itype = LM32BF_INSN_CMPNEI; goto extract_sfmt_addi; 223 case 32 : 224 if ((entire_insn & 0xfc0007ff) == 0x80000000) 225 { itype = LM32BF_INSN_SRU; goto extract_sfmt_add; } 226 itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; 227 case 33 : 228 if ((entire_insn & 0xfc0007ff) == 0x84000000) 229 { itype = LM32BF_INSN_NOR; goto extract_sfmt_add; } 230 itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; 231 case 34 : 232 if ((entire_insn & 0xfc0007ff) == 0x88000000) 233 { itype = LM32BF_INSN_MUL; goto extract_sfmt_add; } 234 itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; 235 case 35 : 236 if ((entire_insn & 0xfc0007ff) == 0x8c000000) 237 { itype = LM32BF_INSN_DIVU; goto extract_sfmt_divu; } 238 itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; 239 case 36 : 240 if ((entire_insn & 0xfc1f07ff) == 0x90000000) 241 { itype = LM32BF_INSN_RCSR; goto extract_sfmt_rcsr; } 242 itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; 243 case 37 : 244 if ((entire_insn & 0xfc0007ff) == 0x94000000) 245 { itype = LM32BF_INSN_SR; goto extract_sfmt_add; } 246 itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; 247 case 38 : 248 if ((entire_insn & 0xfc0007ff) == 0x98000000) 249 { itype = LM32BF_INSN_XOR; goto extract_sfmt_add; } 250 itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; 251 case 40 : 252 if ((entire_insn & 0xfc0007ff) == 0xa0000000) 253 { itype = LM32BF_INSN_AND; goto extract_sfmt_add; } 254 itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; 255 case 41 : 256 if ((entire_insn & 0xfc0007ff) == 0xa4000000) 257 { itype = LM32BF_INSN_XNOR; goto extract_sfmt_add; } 258 itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; 259 case 43 : 260 { 261 unsigned int val = (((insn >> 1) & (1 << 1)) | ((insn >> 0) & (1 << 0))); 262 switch (val) 263 { 264 case 0 : 265 if ((entire_insn & 0xffffffff) == 0xac000002) 266 { itype = LM32BF_INSN_BREAK; goto extract_sfmt_break; } 267 itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; 268 case 3 : 269 if ((entire_insn & 0xffffffff) == 0xac000007) 270 { itype = LM32BF_INSN_SCALL; goto extract_sfmt_break; } 271 itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; 272 default : itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; 273 } 274 } 275 case 44 : 276 if ((entire_insn & 0xfc1f07ff) == 0xb0000000) 277 { itype = LM32BF_INSN_SEXTB; goto extract_sfmt_sextb; } 278 itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; 279 case 45 : 280 if ((entire_insn & 0xfc0007ff) == 0xb4000000) 281 { itype = LM32BF_INSN_ADD; goto extract_sfmt_add; } 282 itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; 283 case 46 : 284 if ((entire_insn & 0xfc0007ff) == 0xb8000000) 285 { itype = LM32BF_INSN_OR; goto extract_sfmt_add; } 286 itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; 287 case 47 : 288 if ((entire_insn & 0xfc0007ff) == 0xbc000000) 289 { itype = LM32BF_INSN_SL; goto extract_sfmt_add; } 290 itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; 291 case 48 : 292 if ((entire_insn & 0xfc1fffff) == 0xc0000000) 293 { itype = LM32BF_INSN_B; goto extract_sfmt_b; } 294 itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; 295 case 49 : 296 if ((entire_insn & 0xfc0007ff) == 0xc4000000) 297 { itype = LM32BF_INSN_MODU; goto extract_sfmt_divu; } 298 itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; 299 case 50 : 300 if ((entire_insn & 0xfc0007ff) == 0xc8000000) 301 { itype = LM32BF_INSN_SUB; goto extract_sfmt_add; } 302 itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; 303 case 51 : itype = LM32BF_INSN_USER; goto extract_sfmt_user; 304 case 52 : 305 if ((entire_insn & 0xfc00ffff) == 0xd0000000) 306 { itype = LM32BF_INSN_WCSR; goto extract_sfmt_wcsr; } 307 itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; 308 case 54 : 309 if ((entire_insn & 0xfc1fffff) == 0xd8000000) 310 { itype = LM32BF_INSN_CALL; goto extract_sfmt_call; } 311 itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; 312 case 55 : 313 if ((entire_insn & 0xfc1f07ff) == 0xdc000000) 314 { itype = LM32BF_INSN_SEXTH; goto extract_sfmt_sextb; } 315 itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; 316 case 56 : itype = LM32BF_INSN_BI; goto extract_sfmt_bi; 317 case 57 : 318 if ((entire_insn & 0xfc0007ff) == 0xe4000000) 319 { itype = LM32BF_INSN_CMPE; goto extract_sfmt_add; } 320 itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; 321 case 58 : 322 if ((entire_insn & 0xfc0007ff) == 0xe8000000) 323 { itype = LM32BF_INSN_CMPG; goto extract_sfmt_add; } 324 itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; 325 case 59 : 326 if ((entire_insn & 0xfc0007ff) == 0xec000000) 327 { itype = LM32BF_INSN_CMPGE; goto extract_sfmt_add; } 328 itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; 329 case 60 : 330 if ((entire_insn & 0xfc0007ff) == 0xf0000000) 331 { itype = LM32BF_INSN_CMPGEU; goto extract_sfmt_add; } 332 itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; 333 case 61 : 334 if ((entire_insn & 0xfc0007ff) == 0xf4000000) 335 { itype = LM32BF_INSN_CMPGU; goto extract_sfmt_add; } 336 itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; 337 case 62 : itype = LM32BF_INSN_CALLI; goto extract_sfmt_calli; 338 case 63 : 339 if ((entire_insn & 0xfc0007ff) == 0xfc000000) 340 { itype = LM32BF_INSN_CMPNE; goto extract_sfmt_add; } 341 itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; 342 default : itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; 343 } 344 } 345 } 346 347 /* The instruction has been decoded, now extract the fields. */ 348 349 extract_sfmt_empty: 350 { 351 const IDESC *idesc = &lm32bf_insn_data[itype]; 352 #define FLD(f) abuf->fields.sfmt_empty.f 353 354 355 /* Record the fields for the semantic handler. */ 356 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0)); 357 358 #undef FLD 359 return idesc; 360 } 361 362 extract_sfmt_add: 363 { 364 const IDESC *idesc = &lm32bf_insn_data[itype]; 365 CGEN_INSN_WORD insn = entire_insn; 366 #define FLD(f) abuf->fields.sfmt_user.f 367 UINT f_r0; 368 UINT f_r1; 369 UINT f_r2; 370 371 f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); 372 f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); 373 f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); 374 375 /* Record the fields for the semantic handler. */ 376 FLD (f_r0) = f_r0; 377 FLD (f_r1) = f_r1; 378 FLD (f_r2) = f_r2; 379 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, (char *) 0)); 380 381 #undef FLD 382 return idesc; 383 } 384 385 extract_sfmt_addi: 386 { 387 const IDESC *idesc = &lm32bf_insn_data[itype]; 388 CGEN_INSN_WORD insn = entire_insn; 389 #define FLD(f) abuf->fields.sfmt_addi.f 390 UINT f_r0; 391 UINT f_r1; 392 INT f_imm; 393 394 f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); 395 f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); 396 f_imm = EXTRACT_LSB0_SINT (insn, 32, 15, 16); 397 398 /* Record the fields for the semantic handler. */ 399 FLD (f_imm) = f_imm; 400 FLD (f_r0) = f_r0; 401 FLD (f_r1) = f_r1; 402 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_imm 0x%x", 'x', f_imm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) 0)); 403 404 #undef FLD 405 return idesc; 406 } 407 408 extract_sfmt_andi: 409 { 410 const IDESC *idesc = &lm32bf_insn_data[itype]; 411 CGEN_INSN_WORD insn = entire_insn; 412 #define FLD(f) abuf->fields.sfmt_andi.f 413 UINT f_r0; 414 UINT f_r1; 415 UINT f_uimm; 416 417 f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); 418 f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); 419 f_uimm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); 420 421 /* Record the fields for the semantic handler. */ 422 FLD (f_r0) = f_r0; 423 FLD (f_uimm) = f_uimm; 424 FLD (f_r1) = f_r1; 425 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andi", "f_r0 0x%x", 'x', f_r0, "f_uimm 0x%x", 'x', f_uimm, "f_r1 0x%x", 'x', f_r1, (char *) 0)); 426 427 #undef FLD 428 return idesc; 429 } 430 431 extract_sfmt_andhii: 432 { 433 const IDESC *idesc = &lm32bf_insn_data[itype]; 434 CGEN_INSN_WORD insn = entire_insn; 435 #define FLD(f) abuf->fields.sfmt_andi.f 436 UINT f_r0; 437 UINT f_r1; 438 UINT f_uimm; 439 440 f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); 441 f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); 442 f_uimm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); 443 444 /* Record the fields for the semantic handler. */ 445 FLD (f_uimm) = f_uimm; 446 FLD (f_r0) = f_r0; 447 FLD (f_r1) = f_r1; 448 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andhii", "f_uimm 0x%x", 'x', f_uimm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) 0)); 449 450 #undef FLD 451 return idesc; 452 } 453 454 extract_sfmt_b: 455 { 456 const IDESC *idesc = &lm32bf_insn_data[itype]; 457 CGEN_INSN_WORD insn = entire_insn; 458 #define FLD(f) abuf->fields.sfmt_be.f 459 UINT f_r0; 460 461 f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); 462 463 /* Record the fields for the semantic handler. */ 464 FLD (f_r0) = f_r0; 465 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_b", "f_r0 0x%x", 'x', f_r0, (char *) 0)); 466 467 #undef FLD 468 return idesc; 469 } 470 471 extract_sfmt_bi: 472 { 473 const IDESC *idesc = &lm32bf_insn_data[itype]; 474 CGEN_INSN_WORD insn = entire_insn; 475 #define FLD(f) abuf->fields.sfmt_bi.f 476 SI f_call; 477 478 f_call = ((pc) + (((SI) (((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) << (6))) >> (4)))); 479 480 /* Record the fields for the semantic handler. */ 481 FLD (i_call) = f_call; 482 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bi", "call 0x%x", 'x', f_call, (char *) 0)); 483 484 #undef FLD 485 return idesc; 486 } 487 488 extract_sfmt_be: 489 { 490 const IDESC *idesc = &lm32bf_insn_data[itype]; 491 CGEN_INSN_WORD insn = entire_insn; 492 #define FLD(f) abuf->fields.sfmt_be.f 493 UINT f_r0; 494 UINT f_r1; 495 SI f_branch; 496 497 f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); 498 f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); 499 f_branch = ((pc) + (((SI) (((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (16))) >> (14)))); 500 501 /* Record the fields for the semantic handler. */ 502 FLD (f_r0) = f_r0; 503 FLD (f_r1) = f_r1; 504 FLD (i_branch) = f_branch; 505 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_be", "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, "branch 0x%x", 'x', f_branch, (char *) 0)); 506 507 #undef FLD 508 return idesc; 509 } 510 511 extract_sfmt_call: 512 { 513 const IDESC *idesc = &lm32bf_insn_data[itype]; 514 CGEN_INSN_WORD insn = entire_insn; 515 #define FLD(f) abuf->fields.sfmt_be.f 516 UINT f_r0; 517 518 f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); 519 520 /* Record the fields for the semantic handler. */ 521 FLD (f_r0) = f_r0; 522 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_call", "f_r0 0x%x", 'x', f_r0, (char *) 0)); 523 524 #undef FLD 525 return idesc; 526 } 527 528 extract_sfmt_calli: 529 { 530 const IDESC *idesc = &lm32bf_insn_data[itype]; 531 CGEN_INSN_WORD insn = entire_insn; 532 #define FLD(f) abuf->fields.sfmt_bi.f 533 SI f_call; 534 535 f_call = ((pc) + (((SI) (((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) << (6))) >> (4)))); 536 537 /* Record the fields for the semantic handler. */ 538 FLD (i_call) = f_call; 539 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_calli", "call 0x%x", 'x', f_call, (char *) 0)); 540 541 #undef FLD 542 return idesc; 543 } 544 545 extract_sfmt_divu: 546 { 547 const IDESC *idesc = &lm32bf_insn_data[itype]; 548 CGEN_INSN_WORD insn = entire_insn; 549 #define FLD(f) abuf->fields.sfmt_user.f 550 UINT f_r0; 551 UINT f_r1; 552 UINT f_r2; 553 554 f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); 555 f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); 556 f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); 557 558 /* Record the fields for the semantic handler. */ 559 FLD (f_r0) = f_r0; 560 FLD (f_r1) = f_r1; 561 FLD (f_r2) = f_r2; 562 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_divu", "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, (char *) 0)); 563 564 #undef FLD 565 return idesc; 566 } 567 568 extract_sfmt_lb: 569 { 570 const IDESC *idesc = &lm32bf_insn_data[itype]; 571 CGEN_INSN_WORD insn = entire_insn; 572 #define FLD(f) abuf->fields.sfmt_addi.f 573 UINT f_r0; 574 UINT f_r1; 575 INT f_imm; 576 577 f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); 578 f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); 579 f_imm = EXTRACT_LSB0_SINT (insn, 32, 15, 16); 580 581 /* Record the fields for the semantic handler. */ 582 FLD (f_imm) = f_imm; 583 FLD (f_r0) = f_r0; 584 FLD (f_r1) = f_r1; 585 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lb", "f_imm 0x%x", 'x', f_imm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) 0)); 586 587 #undef FLD 588 return idesc; 589 } 590 591 extract_sfmt_lh: 592 { 593 const IDESC *idesc = &lm32bf_insn_data[itype]; 594 CGEN_INSN_WORD insn = entire_insn; 595 #define FLD(f) abuf->fields.sfmt_addi.f 596 UINT f_r0; 597 UINT f_r1; 598 INT f_imm; 599 600 f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); 601 f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); 602 f_imm = EXTRACT_LSB0_SINT (insn, 32, 15, 16); 603 604 /* Record the fields for the semantic handler. */ 605 FLD (f_imm) = f_imm; 606 FLD (f_r0) = f_r0; 607 FLD (f_r1) = f_r1; 608 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lh", "f_imm 0x%x", 'x', f_imm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) 0)); 609 610 #undef FLD 611 return idesc; 612 } 613 614 extract_sfmt_lw: 615 { 616 const IDESC *idesc = &lm32bf_insn_data[itype]; 617 CGEN_INSN_WORD insn = entire_insn; 618 #define FLD(f) abuf->fields.sfmt_addi.f 619 UINT f_r0; 620 UINT f_r1; 621 INT f_imm; 622 623 f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); 624 f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); 625 f_imm = EXTRACT_LSB0_SINT (insn, 32, 15, 16); 626 627 /* Record the fields for the semantic handler. */ 628 FLD (f_imm) = f_imm; 629 FLD (f_r0) = f_r0; 630 FLD (f_r1) = f_r1; 631 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lw", "f_imm 0x%x", 'x', f_imm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) 0)); 632 633 #undef FLD 634 return idesc; 635 } 636 637 extract_sfmt_ori: 638 { 639 const IDESC *idesc = &lm32bf_insn_data[itype]; 640 CGEN_INSN_WORD insn = entire_insn; 641 #define FLD(f) abuf->fields.sfmt_andi.f 642 UINT f_r0; 643 UINT f_r1; 644 UINT f_uimm; 645 646 f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); 647 f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); 648 f_uimm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); 649 650 /* Record the fields for the semantic handler. */ 651 FLD (f_uimm) = f_uimm; 652 FLD (f_r0) = f_r0; 653 FLD (f_r1) = f_r1; 654 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ori", "f_uimm 0x%x", 'x', f_uimm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) 0)); 655 656 #undef FLD 657 return idesc; 658 } 659 660 extract_sfmt_rcsr: 661 { 662 const IDESC *idesc = &lm32bf_insn_data[itype]; 663 CGEN_INSN_WORD insn = entire_insn; 664 #define FLD(f) abuf->fields.sfmt_rcsr.f 665 UINT f_csr; 666 UINT f_r2; 667 668 f_csr = EXTRACT_LSB0_UINT (insn, 32, 25, 5); 669 f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); 670 671 /* Record the fields for the semantic handler. */ 672 FLD (f_csr) = f_csr; 673 FLD (f_r2) = f_r2; 674 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rcsr", "f_csr 0x%x", 'x', f_csr, "f_r2 0x%x", 'x', f_r2, (char *) 0)); 675 676 #undef FLD 677 return idesc; 678 } 679 680 extract_sfmt_sb: 681 { 682 const IDESC *idesc = &lm32bf_insn_data[itype]; 683 CGEN_INSN_WORD insn = entire_insn; 684 #define FLD(f) abuf->fields.sfmt_addi.f 685 UINT f_r0; 686 UINT f_r1; 687 INT f_imm; 688 689 f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); 690 f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); 691 f_imm = EXTRACT_LSB0_SINT (insn, 32, 15, 16); 692 693 /* Record the fields for the semantic handler. */ 694 FLD (f_imm) = f_imm; 695 FLD (f_r0) = f_r0; 696 FLD (f_r1) = f_r1; 697 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sb", "f_imm 0x%x", 'x', f_imm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) 0)); 698 699 #undef FLD 700 return idesc; 701 } 702 703 extract_sfmt_sextb: 704 { 705 const IDESC *idesc = &lm32bf_insn_data[itype]; 706 CGEN_INSN_WORD insn = entire_insn; 707 #define FLD(f) abuf->fields.sfmt_user.f 708 UINT f_r0; 709 UINT f_r2; 710 711 f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); 712 f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); 713 714 /* Record the fields for the semantic handler. */ 715 FLD (f_r0) = f_r0; 716 FLD (f_r2) = f_r2; 717 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sextb", "f_r0 0x%x", 'x', f_r0, "f_r2 0x%x", 'x', f_r2, (char *) 0)); 718 719 #undef FLD 720 return idesc; 721 } 722 723 extract_sfmt_sh: 724 { 725 const IDESC *idesc = &lm32bf_insn_data[itype]; 726 CGEN_INSN_WORD insn = entire_insn; 727 #define FLD(f) abuf->fields.sfmt_addi.f 728 UINT f_r0; 729 UINT f_r1; 730 INT f_imm; 731 732 f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); 733 f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); 734 f_imm = EXTRACT_LSB0_SINT (insn, 32, 15, 16); 735 736 /* Record the fields for the semantic handler. */ 737 FLD (f_imm) = f_imm; 738 FLD (f_r0) = f_r0; 739 FLD (f_r1) = f_r1; 740 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sh", "f_imm 0x%x", 'x', f_imm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) 0)); 741 742 #undef FLD 743 return idesc; 744 } 745 746 extract_sfmt_sw: 747 { 748 const IDESC *idesc = &lm32bf_insn_data[itype]; 749 CGEN_INSN_WORD insn = entire_insn; 750 #define FLD(f) abuf->fields.sfmt_addi.f 751 UINT f_r0; 752 UINT f_r1; 753 INT f_imm; 754 755 f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); 756 f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); 757 f_imm = EXTRACT_LSB0_SINT (insn, 32, 15, 16); 758 759 /* Record the fields for the semantic handler. */ 760 FLD (f_imm) = f_imm; 761 FLD (f_r0) = f_r0; 762 FLD (f_r1) = f_r1; 763 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sw", "f_imm 0x%x", 'x', f_imm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) 0)); 764 765 #undef FLD 766 return idesc; 767 } 768 769 extract_sfmt_user: 770 { 771 const IDESC *idesc = &lm32bf_insn_data[itype]; 772 CGEN_INSN_WORD insn = entire_insn; 773 #define FLD(f) abuf->fields.sfmt_user.f 774 UINT f_r0; 775 UINT f_r1; 776 UINT f_r2; 777 UINT f_user; 778 779 f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); 780 f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); 781 f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); 782 f_user = EXTRACT_LSB0_UINT (insn, 32, 10, 11); 783 784 /* Record the fields for the semantic handler. */ 785 FLD (f_r0) = f_r0; 786 FLD (f_r1) = f_r1; 787 FLD (f_user) = f_user; 788 FLD (f_r2) = f_r2; 789 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_user", "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, "f_user 0x%x", 'x', f_user, "f_r2 0x%x", 'x', f_r2, (char *) 0)); 790 791 #undef FLD 792 return idesc; 793 } 794 795 extract_sfmt_wcsr: 796 { 797 const IDESC *idesc = &lm32bf_insn_data[itype]; 798 CGEN_INSN_WORD insn = entire_insn; 799 #define FLD(f) abuf->fields.sfmt_wcsr.f 800 UINT f_csr; 801 UINT f_r1; 802 803 f_csr = EXTRACT_LSB0_UINT (insn, 32, 25, 5); 804 f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); 805 806 /* Record the fields for the semantic handler. */ 807 FLD (f_csr) = f_csr; 808 FLD (f_r1) = f_r1; 809 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_wcsr", "f_csr 0x%x", 'x', f_csr, "f_r1 0x%x", 'x', f_r1, (char *) 0)); 810 811 #undef FLD 812 return idesc; 813 } 814 815 extract_sfmt_break: 816 { 817 const IDESC *idesc = &lm32bf_insn_data[itype]; 818 #define FLD(f) abuf->fields.sfmt_empty.f 819 820 821 /* Record the fields for the semantic handler. */ 822 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_break", (char *) 0)); 823 824 #undef FLD 825 return idesc; 826 } 827 828 } 829