xref: /netbsd-src/external/gpl3/gdb/dist/sim/lm32/cpu.c (revision 946379e7b37692fc43f68eb0d1c10daa0a7f3b6c)
1 /* Misc. support for CPU family lm32bf.
2 
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
4 
5 Copyright 1996-2015 Free Software Foundation, Inc.
6 
7 This file is part of the GNU simulators.
8 
9    This file is free software; you can redistribute it and/or modify
10    it under the terms of the GNU General Public License as published by
11    the Free Software Foundation; either version 3, or (at your option)
12    any later version.
13 
14    It is distributed in the hope that it will be useful, but WITHOUT
15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
17    License for more details.
18 
19    You should have received a copy of the GNU General Public License along
20    with this program; if not, see <http://www.gnu.org/licenses/>.
21 
22 */
23 
24 #define WANT_CPU lm32bf
25 #define WANT_CPU_LM32BF
26 
27 #include "sim-main.h"
28 #include "cgen-ops.h"
29 
30 /* Get the value of h-pc.  */
31 
32 USI
33 lm32bf_h_pc_get (SIM_CPU *current_cpu)
34 {
35   return CPU (h_pc);
36 }
37 
38 /* Set a value for h-pc.  */
39 
40 void
41 lm32bf_h_pc_set (SIM_CPU *current_cpu, USI newval)
42 {
43   CPU (h_pc) = newval;
44 }
45 
46 /* Get the value of h-gr.  */
47 
48 SI
49 lm32bf_h_gr_get (SIM_CPU *current_cpu, UINT regno)
50 {
51   return CPU (h_gr[regno]);
52 }
53 
54 /* Set a value for h-gr.  */
55 
56 void
57 lm32bf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
58 {
59   CPU (h_gr[regno]) = newval;
60 }
61 
62 /* Get the value of h-csr.  */
63 
64 SI
65 lm32bf_h_csr_get (SIM_CPU *current_cpu, UINT regno)
66 {
67   return CPU (h_csr[regno]);
68 }
69 
70 /* Set a value for h-csr.  */
71 
72 void
73 lm32bf_h_csr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
74 {
75   CPU (h_csr[regno]) = newval;
76 }
77 
78 /* Record trace results for INSN.  */
79 
80 void
81 lm32bf_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
82 			    int *indices, TRACE_RECORD *tr)
83 {
84 }
85