1 /* Simulator for the FT32 processor 2 3 Copyright (C) 2008-2017 Free Software Foundation, Inc. 4 Contributed by FTDI <support@ftdichip.com> 5 6 This file is part of simulators. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21 #include "config.h" 22 #include <fcntl.h> 23 #include <signal.h> 24 #include <stdlib.h> 25 #include <stdint.h> 26 27 #include "bfd.h" 28 #include "gdb/callback.h" 29 #include "libiberty.h" 30 #include "gdb/remote-sim.h" 31 32 #include "sim-main.h" 33 #include "sim-options.h" 34 35 #include "opcode/ft32.h" 36 37 /* 38 * FT32 is a Harvard architecture: RAM and code occupy 39 * different address spaces. 40 * 41 * sim and gdb model FT32 memory by adding 0x800000 to RAM 42 * addresses. This means that sim/gdb can treat all addresses 43 * similarly. 44 * 45 * The address space looks like: 46 * 47 * 00000 start of code memory 48 * 3ffff end of code memory 49 * 800000 start of RAM 50 * 80ffff end of RAM 51 */ 52 53 #define RAM_BIAS 0x800000 /* Bias added to RAM addresses. */ 54 55 static unsigned long 56 ft32_extract_unsigned_integer (unsigned char *addr, int len) 57 { 58 unsigned long retval; 59 unsigned char *p; 60 unsigned char *startaddr = (unsigned char *) addr; 61 unsigned char *endaddr = startaddr + len; 62 63 /* Start at the most significant end of the integer, and work towards 64 the least significant. */ 65 retval = 0; 66 67 for (p = endaddr; p > startaddr;) 68 retval = (retval << 8) | * -- p; 69 70 return retval; 71 } 72 73 static void 74 ft32_store_unsigned_integer (unsigned char *addr, int len, unsigned long val) 75 { 76 unsigned char *p; 77 unsigned char *startaddr = (unsigned char *)addr; 78 unsigned char *endaddr = startaddr + len; 79 80 for (p = startaddr; p < endaddr; p++) 81 { 82 *p = val & 0xff; 83 val >>= 8; 84 } 85 } 86 87 /* 88 * Align EA according to its size DW. 89 * The FT32 ignores the low bit of a 16-bit addresss, 90 * and the low two bits of a 32-bit address. 91 */ 92 static uint32_t ft32_align (uint32_t dw, uint32_t ea) 93 { 94 switch (dw) 95 { 96 case 1: 97 ea &= ~1; 98 break; 99 case 2: 100 ea &= ~3; 101 break; 102 default: 103 break; 104 } 105 return ea; 106 } 107 108 /* Read an item from memory address EA, sized DW. */ 109 static uint32_t 110 ft32_read_item (SIM_DESC sd, int dw, uint32_t ea) 111 { 112 sim_cpu *cpu = STATE_CPU (sd, 0); 113 address_word cia = CPU_PC_GET (cpu); 114 uint8_t byte[4]; 115 uint32_t r; 116 117 ea = ft32_align (dw, ea); 118 119 switch (dw) { 120 case 0: 121 return sim_core_read_aligned_1 (cpu, cia, read_map, ea); 122 case 1: 123 return sim_core_read_aligned_2 (cpu, cia, read_map, ea); 124 case 2: 125 return sim_core_read_aligned_4 (cpu, cia, read_map, ea); 126 default: 127 abort (); 128 } 129 } 130 131 /* Write item V to memory address EA, sized DW. */ 132 static void 133 ft32_write_item (SIM_DESC sd, int dw, uint32_t ea, uint32_t v) 134 { 135 sim_cpu *cpu = STATE_CPU (sd, 0); 136 address_word cia = CPU_PC_GET (cpu); 137 uint8_t byte[4]; 138 139 ea = ft32_align (dw, ea); 140 141 switch (dw) { 142 case 0: 143 sim_core_write_aligned_1 (cpu, cia, write_map, ea, v); 144 break; 145 case 1: 146 sim_core_write_aligned_2 (cpu, cia, write_map, ea, v); 147 break; 148 case 2: 149 sim_core_write_aligned_4 (cpu, cia, write_map, ea, v); 150 break; 151 default: 152 abort (); 153 } 154 } 155 156 #define ILLEGAL() \ 157 sim_engine_halt (sd, cpu, NULL, insnpc, sim_signalled, SIM_SIGILL) 158 159 static uint32_t cpu_mem_read (SIM_DESC sd, uint32_t dw, uint32_t ea) 160 { 161 sim_cpu *cpu = STATE_CPU (sd, 0); 162 uint32_t insnpc = cpu->state.pc; 163 uint32_t r; 164 uint8_t byte[4]; 165 166 ea &= 0x1ffff; 167 if (ea & ~0xffff) 168 { 169 /* Simulate some IO devices */ 170 switch (ea) 171 { 172 case 0x10000: 173 return getchar (); 174 case 0x1fff4: 175 /* Read the simulator cycle timer. */ 176 return cpu->state.cycles / 100; 177 default: 178 sim_io_eprintf (sd, "Illegal IO read address %08x, pc %#x\n", 179 ea, insnpc); 180 ILLEGAL (); 181 } 182 } 183 return ft32_read_item (sd, dw, RAM_BIAS + ea); 184 } 185 186 static void cpu_mem_write (SIM_DESC sd, uint32_t dw, uint32_t ea, uint32_t d) 187 { 188 sim_cpu *cpu = STATE_CPU (sd, 0); 189 ea &= 0x1ffff; 190 if (ea & 0x10000) 191 { 192 /* Simulate some IO devices */ 193 switch (ea) 194 { 195 case 0x10000: 196 /* Console output */ 197 putchar (d & 0xff); 198 break; 199 case 0x1fc80: 200 /* Unlock the PM write port */ 201 cpu->state.pm_unlock = (d == 0x1337f7d1); 202 break; 203 case 0x1fc84: 204 /* Set the PM write address register */ 205 cpu->state.pm_addr = d; 206 break; 207 case 0x1fc88: 208 if (cpu->state.pm_unlock) 209 { 210 /* Write to PM. */ 211 ft32_write_item (sd, dw, cpu->state.pm_addr, d); 212 cpu->state.pm_addr += 4; 213 } 214 break; 215 case 0x1fffc: 216 /* Normal exit. */ 217 sim_engine_halt (sd, cpu, NULL, cpu->state.pc, sim_exited, cpu->state.regs[0]); 218 break; 219 case 0x1fff8: 220 sim_io_printf (sd, "Debug write %08x\n", d); 221 break; 222 default: 223 sim_io_eprintf (sd, "Unknown IO write %08x to to %08x\n", d, ea); 224 } 225 } 226 else 227 ft32_write_item (sd, dw, RAM_BIAS + ea, d); 228 } 229 230 #define GET_BYTE(ea) cpu_mem_read (sd, 0, (ea)) 231 #define PUT_BYTE(ea, d) cpu_mem_write (sd, 0, (ea), (d)) 232 233 /* LSBS (n) is a mask of the least significant N bits. */ 234 #define LSBS(n) ((1U << (n)) - 1) 235 236 static void ft32_push (SIM_DESC sd, uint32_t v) 237 { 238 sim_cpu *cpu = STATE_CPU (sd, 0); 239 cpu->state.regs[FT32_HARD_SP] -= 4; 240 cpu->state.regs[FT32_HARD_SP] &= 0xffff; 241 cpu_mem_write (sd, 2, cpu->state.regs[FT32_HARD_SP], v); 242 } 243 244 static uint32_t ft32_pop (SIM_DESC sd) 245 { 246 sim_cpu *cpu = STATE_CPU (sd, 0); 247 uint32_t r = cpu_mem_read (sd, 2, cpu->state.regs[FT32_HARD_SP]); 248 cpu->state.regs[FT32_HARD_SP] += 4; 249 cpu->state.regs[FT32_HARD_SP] &= 0xffff; 250 return r; 251 } 252 253 /* Extract the low SIZ bits of N as an unsigned number. */ 254 static int nunsigned (int siz, int n) 255 { 256 return n & LSBS (siz); 257 } 258 259 /* Extract the low SIZ bits of N as a signed number. */ 260 static int nsigned (int siz, int n) 261 { 262 int shift = (sizeof (int) * 8) - siz; 263 return (n << shift) >> shift; 264 } 265 266 /* Signed division N / D, matching hw behavior for (MIN_INT, -1). */ 267 static uint32_t ft32sdiv (uint32_t n, uint32_t d) 268 { 269 if (n == 0x80000000UL && d == 0xffffffffUL) 270 return 0x80000000UL; 271 else 272 return (uint32_t)((int)n / (int)d); 273 } 274 275 /* Signed modulus N % D, matching hw behavior for (MIN_INT, -1). */ 276 static uint32_t ft32smod (uint32_t n, uint32_t d) 277 { 278 if (n == 0x80000000UL && d == 0xffffffffUL) 279 return 0; 280 else 281 return (uint32_t)((int)n % (int)d); 282 } 283 284 /* Circular rotate right N by B bits. */ 285 static uint32_t ror (uint32_t n, uint32_t b) 286 { 287 b &= 31; 288 return (n >> b) | (n << (32 - b)); 289 } 290 291 /* Implement the BINS machine instruction. 292 See FT32 Programmer's Reference for details. */ 293 static uint32_t bins (uint32_t d, uint32_t f, uint32_t len, uint32_t pos) 294 { 295 uint32_t bitmask = LSBS (len) << pos; 296 return (d & ~bitmask) | ((f << pos) & bitmask); 297 } 298 299 /* Implement the FLIP machine instruction. 300 See FT32 Programmer's Reference for details. */ 301 static uint32_t flip (uint32_t x, uint32_t b) 302 { 303 if (b & 1) 304 x = (x & 0x55555555) << 1 | (x & 0xAAAAAAAA) >> 1; 305 if (b & 2) 306 x = (x & 0x33333333) << 2 | (x & 0xCCCCCCCC) >> 2; 307 if (b & 4) 308 x = (x & 0x0F0F0F0F) << 4 | (x & 0xF0F0F0F0) >> 4; 309 if (b & 8) 310 x = (x & 0x00FF00FF) << 8 | (x & 0xFF00FF00) >> 8; 311 if (b & 16) 312 x = (x & 0x0000FFFF) << 16 | (x & 0xFFFF0000) >> 16; 313 return x; 314 } 315 316 static void 317 step_once (SIM_DESC sd) 318 { 319 sim_cpu *cpu = STATE_CPU (sd, 0); 320 address_word cia = CPU_PC_GET (cpu); 321 uint32_t inst; 322 uint32_t dw; 323 uint32_t cb; 324 uint32_t r_d; 325 uint32_t cr; 326 uint32_t cv; 327 uint32_t bt; 328 uint32_t r_1; 329 uint32_t rimm; 330 uint32_t r_2; 331 uint32_t k20; 332 uint32_t pa; 333 uint32_t aa; 334 uint32_t k16; 335 uint32_t k8; 336 uint32_t al; 337 uint32_t r_1v; 338 uint32_t rimmv; 339 uint32_t bit_pos; 340 uint32_t bit_len; 341 uint32_t upper; 342 uint32_t insnpc; 343 344 if (cpu->state.cycles >= cpu->state.next_tick_cycle) 345 { 346 cpu->state.next_tick_cycle += 100000; 347 ft32_push (sd, cpu->state.pc); 348 cpu->state.pc = 12; /* interrupt 1. */ 349 } 350 inst = ft32_read_item (sd, 2, cpu->state.pc); 351 cpu->state.cycles += 1; 352 353 /* Handle "call 8" (which is FT32's "break" equivalent) here. */ 354 if (inst == 0x00340002) 355 { 356 sim_engine_halt (sd, cpu, NULL, 357 cpu->state.pc, 358 sim_stopped, SIM_SIGTRAP); 359 goto escape; 360 } 361 362 dw = (inst >> FT32_FLD_DW_BIT) & LSBS (FT32_FLD_DW_SIZ); 363 cb = (inst >> FT32_FLD_CB_BIT) & LSBS (FT32_FLD_CB_SIZ); 364 r_d = (inst >> FT32_FLD_R_D_BIT) & LSBS (FT32_FLD_R_D_SIZ); 365 cr = (inst >> FT32_FLD_CR_BIT) & LSBS (FT32_FLD_CR_SIZ); 366 cv = (inst >> FT32_FLD_CV_BIT) & LSBS (FT32_FLD_CV_SIZ); 367 bt = (inst >> FT32_FLD_BT_BIT) & LSBS (FT32_FLD_BT_SIZ); 368 r_1 = (inst >> FT32_FLD_R_1_BIT) & LSBS (FT32_FLD_R_1_SIZ); 369 rimm = (inst >> FT32_FLD_RIMM_BIT) & LSBS (FT32_FLD_RIMM_SIZ); 370 r_2 = (inst >> FT32_FLD_R_2_BIT) & LSBS (FT32_FLD_R_2_SIZ); 371 k20 = nsigned (20, (inst >> FT32_FLD_K20_BIT) & LSBS (FT32_FLD_K20_SIZ)); 372 pa = (inst >> FT32_FLD_PA_BIT) & LSBS (FT32_FLD_PA_SIZ); 373 aa = (inst >> FT32_FLD_AA_BIT) & LSBS (FT32_FLD_AA_SIZ); 374 k16 = (inst >> FT32_FLD_K16_BIT) & LSBS (FT32_FLD_K16_SIZ); 375 k8 = nsigned (8, (inst >> FT32_FLD_K8_BIT) & LSBS (FT32_FLD_K8_SIZ)); 376 al = (inst >> FT32_FLD_AL_BIT) & LSBS (FT32_FLD_AL_SIZ); 377 378 r_1v = cpu->state.regs[r_1]; 379 rimmv = (rimm & 0x400) ? nsigned (10, rimm) : cpu->state.regs[rimm & 0x1f]; 380 381 bit_pos = rimmv & 31; 382 bit_len = 0xf & (rimmv >> 5); 383 if (bit_len == 0) 384 bit_len = 16; 385 386 upper = (inst >> 27); 387 388 insnpc = cpu->state.pc; 389 cpu->state.pc += 4; 390 switch (upper) 391 { 392 case FT32_PAT_TOC: 393 case FT32_PAT_TOCI: 394 { 395 int take = (cr == 3) || ((1 & (cpu->state.regs[28 + cr] >> cb)) == cv); 396 if (take) 397 { 398 cpu->state.cycles += 1; 399 if (bt) 400 ft32_push (sd, cpu->state.pc); /* this is a call. */ 401 if (upper == FT32_PAT_TOC) 402 cpu->state.pc = pa << 2; 403 else 404 cpu->state.pc = cpu->state.regs[r_2]; 405 if (cpu->state.pc == 0x8) 406 goto escape; 407 } 408 } 409 break; 410 411 case FT32_PAT_ALUOP: 412 case FT32_PAT_CMPOP: 413 { 414 uint32_t result; 415 switch (al) 416 { 417 case 0x0: result = r_1v + rimmv; break; 418 case 0x1: result = ror (r_1v, rimmv); break; 419 case 0x2: result = r_1v - rimmv; break; 420 case 0x3: result = (r_1v << 10) | (1023 & rimmv); break; 421 case 0x4: result = r_1v & rimmv; break; 422 case 0x5: result = r_1v | rimmv; break; 423 case 0x6: result = r_1v ^ rimmv; break; 424 case 0x7: result = ~(r_1v ^ rimmv); break; 425 case 0x8: result = r_1v << rimmv; break; 426 case 0x9: result = r_1v >> rimmv; break; 427 case 0xa: result = (int32_t)r_1v >> rimmv; break; 428 case 0xb: result = bins (r_1v, rimmv >> 10, bit_len, bit_pos); break; 429 case 0xc: result = nsigned (bit_len, r_1v >> bit_pos); break; 430 case 0xd: result = nunsigned (bit_len, r_1v >> bit_pos); break; 431 case 0xe: result = flip (r_1v, rimmv); break; 432 default: 433 sim_io_eprintf (sd, "Unhandled alu %#x\n", al); 434 ILLEGAL (); 435 } 436 if (upper == FT32_PAT_ALUOP) 437 cpu->state.regs[r_d] = result; 438 else 439 { 440 uint32_t dwmask = 0; 441 int dwsiz = 0; 442 int zero; 443 int sign; 444 int ahi; 445 int bhi; 446 int overflow; 447 int carry; 448 int bit; 449 uint64_t ra; 450 uint64_t rb; 451 int above; 452 int greater; 453 int greatereq; 454 455 switch (dw) 456 { 457 case 0: dwsiz = 7; dwmask = 0xffU; break; 458 case 1: dwsiz = 15; dwmask = 0xffffU; break; 459 case 2: dwsiz = 31; dwmask = 0xffffffffU; break; 460 } 461 462 zero = (0 == (result & dwmask)); 463 sign = 1 & (result >> dwsiz); 464 ahi = 1 & (r_1v >> dwsiz); 465 bhi = 1 & (rimmv >> dwsiz); 466 overflow = (sign != ahi) & (ahi == !bhi); 467 bit = (dwsiz + 1); 468 ra = r_1v & dwmask; 469 rb = rimmv & dwmask; 470 switch (al) 471 { 472 case 0x0: carry = 1 & ((ra + rb) >> bit); break; 473 case 0x2: carry = 1 & ((ra - rb) >> bit); break; 474 default: carry = 0; break; 475 } 476 above = (!carry & !zero); 477 greater = (sign == overflow) & !zero; 478 greatereq = (sign == overflow); 479 480 cpu->state.regs[r_d] = ( 481 (above << 6) | 482 (greater << 5) | 483 (greatereq << 4) | 484 (sign << 3) | 485 (overflow << 2) | 486 (carry << 1) | 487 (zero << 0)); 488 } 489 } 490 break; 491 492 case FT32_PAT_LDK: 493 cpu->state.regs[r_d] = k20; 494 break; 495 496 case FT32_PAT_LPM: 497 cpu->state.regs[r_d] = ft32_read_item (sd, dw, pa << 2); 498 cpu->state.cycles += 1; 499 break; 500 501 case FT32_PAT_LPMI: 502 cpu->state.regs[r_d] = ft32_read_item (sd, dw, cpu->state.regs[r_1] + k8); 503 cpu->state.cycles += 1; 504 break; 505 506 case FT32_PAT_STA: 507 cpu_mem_write (sd, dw, aa, cpu->state.regs[r_d]); 508 break; 509 510 case FT32_PAT_STI: 511 cpu_mem_write (sd, dw, cpu->state.regs[r_d] + k8, cpu->state.regs[r_1]); 512 break; 513 514 case FT32_PAT_LDA: 515 cpu->state.regs[r_d] = cpu_mem_read (sd, dw, aa); 516 cpu->state.cycles += 1; 517 break; 518 519 case FT32_PAT_LDI: 520 cpu->state.regs[r_d] = cpu_mem_read (sd, dw, cpu->state.regs[r_1] + k8); 521 cpu->state.cycles += 1; 522 break; 523 524 case FT32_PAT_EXA: 525 { 526 uint32_t tmp; 527 tmp = cpu_mem_read (sd, dw, aa); 528 cpu_mem_write (sd, dw, aa, cpu->state.regs[r_d]); 529 cpu->state.regs[r_d] = tmp; 530 cpu->state.cycles += 1; 531 } 532 break; 533 534 case FT32_PAT_EXI: 535 { 536 uint32_t tmp; 537 tmp = cpu_mem_read (sd, dw, cpu->state.regs[r_1] + k8); 538 cpu_mem_write (sd, dw, cpu->state.regs[r_1] + k8, cpu->state.regs[r_d]); 539 cpu->state.regs[r_d] = tmp; 540 cpu->state.cycles += 1; 541 } 542 break; 543 544 case FT32_PAT_PUSH: 545 ft32_push (sd, r_1v); 546 break; 547 548 case FT32_PAT_LINK: 549 ft32_push (sd, cpu->state.regs[r_d]); 550 cpu->state.regs[r_d] = cpu->state.regs[FT32_HARD_SP]; 551 cpu->state.regs[FT32_HARD_SP] -= k16; 552 cpu->state.regs[FT32_HARD_SP] &= 0xffff; 553 break; 554 555 case FT32_PAT_UNLINK: 556 cpu->state.regs[FT32_HARD_SP] = cpu->state.regs[r_d]; 557 cpu->state.regs[FT32_HARD_SP] &= 0xffff; 558 cpu->state.regs[r_d] = ft32_pop (sd); 559 break; 560 561 case FT32_PAT_POP: 562 cpu->state.cycles += 1; 563 cpu->state.regs[r_d] = ft32_pop (sd); 564 break; 565 566 case FT32_PAT_RETURN: 567 cpu->state.pc = ft32_pop (sd); 568 break; 569 570 case FT32_PAT_FFUOP: 571 switch (al) 572 { 573 case 0x0: 574 cpu->state.regs[r_d] = r_1v / rimmv; 575 break; 576 case 0x1: 577 cpu->state.regs[r_d] = r_1v % rimmv; 578 break; 579 case 0x2: 580 cpu->state.regs[r_d] = ft32sdiv (r_1v, rimmv); 581 break; 582 case 0x3: 583 cpu->state.regs[r_d] = ft32smod (r_1v, rimmv); 584 break; 585 586 case 0x4: 587 { 588 /* strcmp instruction. */ 589 uint32_t a = r_1v; 590 uint32_t b = rimmv; 591 uint32_t i = 0; 592 while ((GET_BYTE (a + i) != 0) && 593 (GET_BYTE (a + i) == GET_BYTE (b + i))) 594 i++; 595 cpu->state.regs[r_d] = GET_BYTE (a + i) - GET_BYTE (b + i); 596 } 597 break; 598 599 case 0x5: 600 { 601 /* memcpy instruction. */ 602 uint32_t src = r_1v; 603 uint32_t dst = cpu->state.regs[r_d]; 604 uint32_t i; 605 for (i = 0; i < (rimmv & 0x7fff); i++) 606 PUT_BYTE (dst + i, GET_BYTE (src + i)); 607 } 608 break; 609 case 0x6: 610 { 611 /* strlen instruction. */ 612 uint32_t src = r_1v; 613 uint32_t i; 614 for (i = 0; GET_BYTE (src + i) != 0; i++) 615 ; 616 cpu->state.regs[r_d] = i; 617 } 618 break; 619 case 0x7: 620 { 621 /* memset instruction. */ 622 uint32_t dst = cpu->state.regs[r_d]; 623 uint32_t i; 624 for (i = 0; i < (rimmv & 0x7fff); i++) 625 PUT_BYTE (dst + i, r_1v); 626 } 627 break; 628 case 0x8: 629 cpu->state.regs[r_d] = r_1v * rimmv; 630 break; 631 case 0x9: 632 cpu->state.regs[r_d] = ((uint64_t)r_1v * (uint64_t)rimmv) >> 32; 633 break; 634 case 0xa: 635 { 636 /* stpcpy instruction. */ 637 uint32_t src = r_1v; 638 uint32_t dst = cpu->state.regs[r_d]; 639 uint32_t i; 640 for (i = 0; GET_BYTE (src + i) != 0; i++) 641 PUT_BYTE (dst + i, GET_BYTE (src + i)); 642 PUT_BYTE (dst + i, 0); 643 cpu->state.regs[r_d] = dst + i; 644 } 645 break; 646 case 0xe: 647 { 648 /* streamout instruction. */ 649 uint32_t i; 650 uint32_t src = cpu->state.regs[r_1]; 651 for (i = 0; i < rimmv; i += (1 << dw)) 652 { 653 cpu_mem_write (sd, 654 dw, 655 cpu->state.regs[r_d], 656 cpu_mem_read (sd, dw, src)); 657 src += (1 << dw); 658 } 659 } 660 break; 661 default: 662 sim_io_eprintf (sd, "Unhandled ffu %#x at %08x\n", al, insnpc); 663 ILLEGAL (); 664 } 665 break; 666 667 default: 668 sim_io_eprintf (sd, "Unhandled pattern %d at %08x\n", upper, insnpc); 669 ILLEGAL (); 670 } 671 cpu->state.num_i++; 672 673 escape: 674 ; 675 } 676 677 void 678 sim_engine_run (SIM_DESC sd, 679 int next_cpu_nr, /* ignore */ 680 int nr_cpus, /* ignore */ 681 int siggnal) /* ignore */ 682 { 683 sim_cpu *cpu; 684 685 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); 686 687 cpu = STATE_CPU (sd, 0); 688 689 while (1) 690 { 691 step_once (sd); 692 if (sim_events_tick (sd)) 693 sim_events_process (sd); 694 } 695 } 696 697 static uint32_t * 698 ft32_lookup_register (SIM_CPU *cpu, int nr) 699 { 700 /* Handle the register number translation here. 701 * Sim registers are 0-31. 702 * Other tools (gcc, gdb) use: 703 * 0 - fp 704 * 1 - sp 705 * 2 - r0 706 * 31 - cc 707 */ 708 709 if ((nr < 0) || (nr > 32)) 710 { 711 sim_io_eprintf (CPU_STATE (cpu), "unknown register %i\n", nr); 712 abort (); 713 } 714 715 switch (nr) 716 { 717 case FT32_FP_REGNUM: 718 return &cpu->state.regs[FT32_HARD_FP]; 719 case FT32_SP_REGNUM: 720 return &cpu->state.regs[FT32_HARD_SP]; 721 case FT32_CC_REGNUM: 722 return &cpu->state.regs[FT32_HARD_CC]; 723 case FT32_PC_REGNUM: 724 return &cpu->state.pc; 725 default: 726 return &cpu->state.regs[nr - 2]; 727 } 728 } 729 730 static int 731 ft32_reg_store (SIM_CPU *cpu, 732 int rn, 733 unsigned char *memory, 734 int length) 735 { 736 if (0 <= rn && rn <= 32) 737 { 738 if (length == 4) 739 *ft32_lookup_register (cpu, rn) = ft32_extract_unsigned_integer (memory, 4); 740 741 return 4; 742 } 743 else 744 return 0; 745 } 746 747 static int 748 ft32_reg_fetch (SIM_CPU *cpu, 749 int rn, 750 unsigned char *memory, 751 int length) 752 { 753 if (0 <= rn && rn <= 32) 754 { 755 if (length == 4) 756 ft32_store_unsigned_integer (memory, 4, *ft32_lookup_register (cpu, rn)); 757 758 return 4; 759 } 760 else 761 return 0; 762 } 763 764 static sim_cia 765 ft32_pc_get (SIM_CPU *cpu) 766 { 767 return cpu->state.pc; 768 } 769 770 static void 771 ft32_pc_set (SIM_CPU *cpu, sim_cia newpc) 772 { 773 cpu->state.pc = newpc; 774 } 775 776 /* Cover function of sim_state_free to free the cpu buffers as well. */ 777 778 static void 779 free_state (SIM_DESC sd) 780 { 781 if (STATE_MODULES (sd) != NULL) 782 sim_module_uninstall (sd); 783 sim_cpu_free_all (sd); 784 sim_state_free (sd); 785 } 786 787 SIM_DESC 788 sim_open (SIM_OPEN_KIND kind, 789 host_callback *cb, 790 struct bfd *abfd, 791 char * const *argv) 792 { 793 char c; 794 size_t i; 795 SIM_DESC sd = sim_state_alloc (kind, cb); 796 797 /* The cpu data is kept in a separately allocated chunk of memory. */ 798 if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK) 799 { 800 free_state (sd); 801 return 0; 802 } 803 804 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) 805 { 806 free_state (sd); 807 return 0; 808 } 809 810 /* The parser will print an error message for us, so we silently return. */ 811 if (sim_parse_args (sd, argv) != SIM_RC_OK) 812 { 813 free_state (sd); 814 return 0; 815 } 816 817 /* Allocate external memory if none specified by user. 818 Use address 4 here in case the user wanted address 0 unmapped. */ 819 if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0) 820 { 821 sim_do_command (sd, "memory region 0x00000000,0x40000"); 822 sim_do_command (sd, "memory region 0x800000,0x10000"); 823 } 824 825 /* Check for/establish the reference program image. */ 826 if (sim_analyze_program (sd, 827 (STATE_PROG_ARGV (sd) != NULL 828 ? *STATE_PROG_ARGV (sd) 829 : NULL), abfd) != SIM_RC_OK) 830 { 831 free_state (sd); 832 return 0; 833 } 834 835 /* Configure/verify the target byte order and other runtime 836 configuration options. */ 837 if (sim_config (sd) != SIM_RC_OK) 838 { 839 free_state (sd); 840 return 0; 841 } 842 843 if (sim_post_argv_init (sd) != SIM_RC_OK) 844 { 845 free_state (sd); 846 return 0; 847 } 848 849 /* CPU specific initialization. */ 850 for (i = 0; i < MAX_NR_PROCESSORS; ++i) 851 { 852 SIM_CPU *cpu = STATE_CPU (sd, i); 853 854 CPU_REG_FETCH (cpu) = ft32_reg_fetch; 855 CPU_REG_STORE (cpu) = ft32_reg_store; 856 CPU_PC_FETCH (cpu) = ft32_pc_get; 857 CPU_PC_STORE (cpu) = ft32_pc_set; 858 } 859 860 return sd; 861 } 862 863 SIM_RC 864 sim_create_inferior (SIM_DESC sd, 865 struct bfd *abfd, 866 char * const *argv, 867 char * const *env) 868 { 869 uint32_t addr; 870 sim_cpu *cpu = STATE_CPU (sd, 0); 871 872 /* Set the PC. */ 873 if (abfd != NULL) 874 addr = bfd_get_start_address (abfd); 875 else 876 addr = 0; 877 878 /* Standalone mode (i.e. `run`) will take care of the argv for us in 879 sim_open() -> sim_parse_args(). But in debug mode (i.e. 'target sim' 880 with `gdb`), we need to handle it because the user can change the 881 argv on the fly via gdb's 'run'. */ 882 if (STATE_PROG_ARGV (sd) != argv) 883 { 884 freeargv (STATE_PROG_ARGV (sd)); 885 STATE_PROG_ARGV (sd) = dupargv (argv); 886 } 887 cpu->state.regs[FT32_HARD_SP] = addr; 888 cpu->state.num_i = 0; 889 cpu->state.cycles = 0; 890 cpu->state.next_tick_cycle = 100000; 891 892 return SIM_RC_OK; 893 } 894