1 /* Misc. support for CPU family frvbf. 2 3 THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5 Copyright 1996-2014 Free Software Foundation, Inc. 6 7 This file is part of the GNU simulators. 8 9 This file is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License along 20 with this program; if not, see <http://www.gnu.org/licenses/>. 21 22 */ 23 24 #define WANT_CPU frvbf 25 #define WANT_CPU_FRVBF 26 27 #include "sim-main.h" 28 #include "cgen-ops.h" 29 30 /* Get the value of h-reloc-ann. */ 31 32 BI 33 frvbf_h_reloc_ann_get (SIM_CPU *current_cpu) 34 { 35 return CPU (h_reloc_ann); 36 } 37 38 /* Set a value for h-reloc-ann. */ 39 40 void 41 frvbf_h_reloc_ann_set (SIM_CPU *current_cpu, BI newval) 42 { 43 CPU (h_reloc_ann) = newval; 44 } 45 46 /* Get the value of h-pc. */ 47 48 USI 49 frvbf_h_pc_get (SIM_CPU *current_cpu) 50 { 51 return CPU (h_pc); 52 } 53 54 /* Set a value for h-pc. */ 55 56 void 57 frvbf_h_pc_set (SIM_CPU *current_cpu, USI newval) 58 { 59 CPU (h_pc) = newval; 60 } 61 62 /* Get the value of h-psr_imple. */ 63 64 UQI 65 frvbf_h_psr_imple_get (SIM_CPU *current_cpu) 66 { 67 return CPU (h_psr_imple); 68 } 69 70 /* Set a value for h-psr_imple. */ 71 72 void 73 frvbf_h_psr_imple_set (SIM_CPU *current_cpu, UQI newval) 74 { 75 CPU (h_psr_imple) = newval; 76 } 77 78 /* Get the value of h-psr_ver. */ 79 80 UQI 81 frvbf_h_psr_ver_get (SIM_CPU *current_cpu) 82 { 83 return CPU (h_psr_ver); 84 } 85 86 /* Set a value for h-psr_ver. */ 87 88 void 89 frvbf_h_psr_ver_set (SIM_CPU *current_cpu, UQI newval) 90 { 91 CPU (h_psr_ver) = newval; 92 } 93 94 /* Get the value of h-psr_ice. */ 95 96 BI 97 frvbf_h_psr_ice_get (SIM_CPU *current_cpu) 98 { 99 return CPU (h_psr_ice); 100 } 101 102 /* Set a value for h-psr_ice. */ 103 104 void 105 frvbf_h_psr_ice_set (SIM_CPU *current_cpu, BI newval) 106 { 107 CPU (h_psr_ice) = newval; 108 } 109 110 /* Get the value of h-psr_nem. */ 111 112 BI 113 frvbf_h_psr_nem_get (SIM_CPU *current_cpu) 114 { 115 return CPU (h_psr_nem); 116 } 117 118 /* Set a value for h-psr_nem. */ 119 120 void 121 frvbf_h_psr_nem_set (SIM_CPU *current_cpu, BI newval) 122 { 123 CPU (h_psr_nem) = newval; 124 } 125 126 /* Get the value of h-psr_cm. */ 127 128 BI 129 frvbf_h_psr_cm_get (SIM_CPU *current_cpu) 130 { 131 return CPU (h_psr_cm); 132 } 133 134 /* Set a value for h-psr_cm. */ 135 136 void 137 frvbf_h_psr_cm_set (SIM_CPU *current_cpu, BI newval) 138 { 139 CPU (h_psr_cm) = newval; 140 } 141 142 /* Get the value of h-psr_be. */ 143 144 BI 145 frvbf_h_psr_be_get (SIM_CPU *current_cpu) 146 { 147 return CPU (h_psr_be); 148 } 149 150 /* Set a value for h-psr_be. */ 151 152 void 153 frvbf_h_psr_be_set (SIM_CPU *current_cpu, BI newval) 154 { 155 CPU (h_psr_be) = newval; 156 } 157 158 /* Get the value of h-psr_esr. */ 159 160 BI 161 frvbf_h_psr_esr_get (SIM_CPU *current_cpu) 162 { 163 return CPU (h_psr_esr); 164 } 165 166 /* Set a value for h-psr_esr. */ 167 168 void 169 frvbf_h_psr_esr_set (SIM_CPU *current_cpu, BI newval) 170 { 171 CPU (h_psr_esr) = newval; 172 } 173 174 /* Get the value of h-psr_ef. */ 175 176 BI 177 frvbf_h_psr_ef_get (SIM_CPU *current_cpu) 178 { 179 return CPU (h_psr_ef); 180 } 181 182 /* Set a value for h-psr_ef. */ 183 184 void 185 frvbf_h_psr_ef_set (SIM_CPU *current_cpu, BI newval) 186 { 187 CPU (h_psr_ef) = newval; 188 } 189 190 /* Get the value of h-psr_em. */ 191 192 BI 193 frvbf_h_psr_em_get (SIM_CPU *current_cpu) 194 { 195 return CPU (h_psr_em); 196 } 197 198 /* Set a value for h-psr_em. */ 199 200 void 201 frvbf_h_psr_em_set (SIM_CPU *current_cpu, BI newval) 202 { 203 CPU (h_psr_em) = newval; 204 } 205 206 /* Get the value of h-psr_pil. */ 207 208 UQI 209 frvbf_h_psr_pil_get (SIM_CPU *current_cpu) 210 { 211 return CPU (h_psr_pil); 212 } 213 214 /* Set a value for h-psr_pil. */ 215 216 void 217 frvbf_h_psr_pil_set (SIM_CPU *current_cpu, UQI newval) 218 { 219 CPU (h_psr_pil) = newval; 220 } 221 222 /* Get the value of h-psr_ps. */ 223 224 BI 225 frvbf_h_psr_ps_get (SIM_CPU *current_cpu) 226 { 227 return CPU (h_psr_ps); 228 } 229 230 /* Set a value for h-psr_ps. */ 231 232 void 233 frvbf_h_psr_ps_set (SIM_CPU *current_cpu, BI newval) 234 { 235 CPU (h_psr_ps) = newval; 236 } 237 238 /* Get the value of h-psr_et. */ 239 240 BI 241 frvbf_h_psr_et_get (SIM_CPU *current_cpu) 242 { 243 return CPU (h_psr_et); 244 } 245 246 /* Set a value for h-psr_et. */ 247 248 void 249 frvbf_h_psr_et_set (SIM_CPU *current_cpu, BI newval) 250 { 251 CPU (h_psr_et) = newval; 252 } 253 254 /* Get the value of h-psr_s. */ 255 256 BI 257 frvbf_h_psr_s_get (SIM_CPU *current_cpu) 258 { 259 return CPU (h_psr_s); 260 } 261 262 /* Set a value for h-psr_s. */ 263 264 void 265 frvbf_h_psr_s_set (SIM_CPU *current_cpu, BI newval) 266 { 267 SET_H_PSR_S (newval); 268 } 269 270 /* Get the value of h-tbr_tba. */ 271 272 USI 273 frvbf_h_tbr_tba_get (SIM_CPU *current_cpu) 274 { 275 return CPU (h_tbr_tba); 276 } 277 278 /* Set a value for h-tbr_tba. */ 279 280 void 281 frvbf_h_tbr_tba_set (SIM_CPU *current_cpu, USI newval) 282 { 283 CPU (h_tbr_tba) = newval; 284 } 285 286 /* Get the value of h-tbr_tt. */ 287 288 UQI 289 frvbf_h_tbr_tt_get (SIM_CPU *current_cpu) 290 { 291 return CPU (h_tbr_tt); 292 } 293 294 /* Set a value for h-tbr_tt. */ 295 296 void 297 frvbf_h_tbr_tt_set (SIM_CPU *current_cpu, UQI newval) 298 { 299 CPU (h_tbr_tt) = newval; 300 } 301 302 /* Get the value of h-bpsr_bs. */ 303 304 BI 305 frvbf_h_bpsr_bs_get (SIM_CPU *current_cpu) 306 { 307 return CPU (h_bpsr_bs); 308 } 309 310 /* Set a value for h-bpsr_bs. */ 311 312 void 313 frvbf_h_bpsr_bs_set (SIM_CPU *current_cpu, BI newval) 314 { 315 CPU (h_bpsr_bs) = newval; 316 } 317 318 /* Get the value of h-bpsr_bet. */ 319 320 BI 321 frvbf_h_bpsr_bet_get (SIM_CPU *current_cpu) 322 { 323 return CPU (h_bpsr_bet); 324 } 325 326 /* Set a value for h-bpsr_bet. */ 327 328 void 329 frvbf_h_bpsr_bet_set (SIM_CPU *current_cpu, BI newval) 330 { 331 CPU (h_bpsr_bet) = newval; 332 } 333 334 /* Get the value of h-gr. */ 335 336 USI 337 frvbf_h_gr_get (SIM_CPU *current_cpu, UINT regno) 338 { 339 return GET_H_GR (regno); 340 } 341 342 /* Set a value for h-gr. */ 343 344 void 345 frvbf_h_gr_set (SIM_CPU *current_cpu, UINT regno, USI newval) 346 { 347 SET_H_GR (regno, newval); 348 } 349 350 /* Get the value of h-gr_double. */ 351 352 DI 353 frvbf_h_gr_double_get (SIM_CPU *current_cpu, UINT regno) 354 { 355 return GET_H_GR_DOUBLE (regno); 356 } 357 358 /* Set a value for h-gr_double. */ 359 360 void 361 frvbf_h_gr_double_set (SIM_CPU *current_cpu, UINT regno, DI newval) 362 { 363 SET_H_GR_DOUBLE (regno, newval); 364 } 365 366 /* Get the value of h-gr_hi. */ 367 368 UHI 369 frvbf_h_gr_hi_get (SIM_CPU *current_cpu, UINT regno) 370 { 371 return GET_H_GR_HI (regno); 372 } 373 374 /* Set a value for h-gr_hi. */ 375 376 void 377 frvbf_h_gr_hi_set (SIM_CPU *current_cpu, UINT regno, UHI newval) 378 { 379 SET_H_GR_HI (regno, newval); 380 } 381 382 /* Get the value of h-gr_lo. */ 383 384 UHI 385 frvbf_h_gr_lo_get (SIM_CPU *current_cpu, UINT regno) 386 { 387 return GET_H_GR_LO (regno); 388 } 389 390 /* Set a value for h-gr_lo. */ 391 392 void 393 frvbf_h_gr_lo_set (SIM_CPU *current_cpu, UINT regno, UHI newval) 394 { 395 SET_H_GR_LO (regno, newval); 396 } 397 398 /* Get the value of h-fr. */ 399 400 SF 401 frvbf_h_fr_get (SIM_CPU *current_cpu, UINT regno) 402 { 403 return GET_H_FR (regno); 404 } 405 406 /* Set a value for h-fr. */ 407 408 void 409 frvbf_h_fr_set (SIM_CPU *current_cpu, UINT regno, SF newval) 410 { 411 SET_H_FR (regno, newval); 412 } 413 414 /* Get the value of h-fr_double. */ 415 416 DF 417 frvbf_h_fr_double_get (SIM_CPU *current_cpu, UINT regno) 418 { 419 return GET_H_FR_DOUBLE (regno); 420 } 421 422 /* Set a value for h-fr_double. */ 423 424 void 425 frvbf_h_fr_double_set (SIM_CPU *current_cpu, UINT regno, DF newval) 426 { 427 SET_H_FR_DOUBLE (regno, newval); 428 } 429 430 /* Get the value of h-fr_int. */ 431 432 USI 433 frvbf_h_fr_int_get (SIM_CPU *current_cpu, UINT regno) 434 { 435 return GET_H_FR_INT (regno); 436 } 437 438 /* Set a value for h-fr_int. */ 439 440 void 441 frvbf_h_fr_int_set (SIM_CPU *current_cpu, UINT regno, USI newval) 442 { 443 SET_H_FR_INT (regno, newval); 444 } 445 446 /* Get the value of h-fr_hi. */ 447 448 UHI 449 frvbf_h_fr_hi_get (SIM_CPU *current_cpu, UINT regno) 450 { 451 return GET_H_FR_HI (regno); 452 } 453 454 /* Set a value for h-fr_hi. */ 455 456 void 457 frvbf_h_fr_hi_set (SIM_CPU *current_cpu, UINT regno, UHI newval) 458 { 459 SET_H_FR_HI (regno, newval); 460 } 461 462 /* Get the value of h-fr_lo. */ 463 464 UHI 465 frvbf_h_fr_lo_get (SIM_CPU *current_cpu, UINT regno) 466 { 467 return GET_H_FR_LO (regno); 468 } 469 470 /* Set a value for h-fr_lo. */ 471 472 void 473 frvbf_h_fr_lo_set (SIM_CPU *current_cpu, UINT regno, UHI newval) 474 { 475 SET_H_FR_LO (regno, newval); 476 } 477 478 /* Get the value of h-fr_0. */ 479 480 UHI 481 frvbf_h_fr_0_get (SIM_CPU *current_cpu, UINT regno) 482 { 483 return GET_H_FR_0 (regno); 484 } 485 486 /* Set a value for h-fr_0. */ 487 488 void 489 frvbf_h_fr_0_set (SIM_CPU *current_cpu, UINT regno, UHI newval) 490 { 491 SET_H_FR_0 (regno, newval); 492 } 493 494 /* Get the value of h-fr_1. */ 495 496 UHI 497 frvbf_h_fr_1_get (SIM_CPU *current_cpu, UINT regno) 498 { 499 return GET_H_FR_1 (regno); 500 } 501 502 /* Set a value for h-fr_1. */ 503 504 void 505 frvbf_h_fr_1_set (SIM_CPU *current_cpu, UINT regno, UHI newval) 506 { 507 SET_H_FR_1 (regno, newval); 508 } 509 510 /* Get the value of h-fr_2. */ 511 512 UHI 513 frvbf_h_fr_2_get (SIM_CPU *current_cpu, UINT regno) 514 { 515 return GET_H_FR_2 (regno); 516 } 517 518 /* Set a value for h-fr_2. */ 519 520 void 521 frvbf_h_fr_2_set (SIM_CPU *current_cpu, UINT regno, UHI newval) 522 { 523 SET_H_FR_2 (regno, newval); 524 } 525 526 /* Get the value of h-fr_3. */ 527 528 UHI 529 frvbf_h_fr_3_get (SIM_CPU *current_cpu, UINT regno) 530 { 531 return GET_H_FR_3 (regno); 532 } 533 534 /* Set a value for h-fr_3. */ 535 536 void 537 frvbf_h_fr_3_set (SIM_CPU *current_cpu, UINT regno, UHI newval) 538 { 539 SET_H_FR_3 (regno, newval); 540 } 541 542 /* Get the value of h-cpr. */ 543 544 SI 545 frvbf_h_cpr_get (SIM_CPU *current_cpu, UINT regno) 546 { 547 return CPU (h_cpr[regno]); 548 } 549 550 /* Set a value for h-cpr. */ 551 552 void 553 frvbf_h_cpr_set (SIM_CPU *current_cpu, UINT regno, SI newval) 554 { 555 CPU (h_cpr[regno]) = newval; 556 } 557 558 /* Get the value of h-cpr_double. */ 559 560 DI 561 frvbf_h_cpr_double_get (SIM_CPU *current_cpu, UINT regno) 562 { 563 return GET_H_CPR_DOUBLE (regno); 564 } 565 566 /* Set a value for h-cpr_double. */ 567 568 void 569 frvbf_h_cpr_double_set (SIM_CPU *current_cpu, UINT regno, DI newval) 570 { 571 SET_H_CPR_DOUBLE (regno, newval); 572 } 573 574 /* Get the value of h-spr. */ 575 576 USI 577 frvbf_h_spr_get (SIM_CPU *current_cpu, UINT regno) 578 { 579 return GET_H_SPR (regno); 580 } 581 582 /* Set a value for h-spr. */ 583 584 void 585 frvbf_h_spr_set (SIM_CPU *current_cpu, UINT regno, USI newval) 586 { 587 SET_H_SPR (regno, newval); 588 } 589 590 /* Get the value of h-accg. */ 591 592 USI 593 frvbf_h_accg_get (SIM_CPU *current_cpu, UINT regno) 594 { 595 return GET_H_ACCG (regno); 596 } 597 598 /* Set a value for h-accg. */ 599 600 void 601 frvbf_h_accg_set (SIM_CPU *current_cpu, UINT regno, USI newval) 602 { 603 SET_H_ACCG (regno, newval); 604 } 605 606 /* Get the value of h-acc40S. */ 607 608 DI 609 frvbf_h_acc40S_get (SIM_CPU *current_cpu, UINT regno) 610 { 611 return GET_H_ACC40S (regno); 612 } 613 614 /* Set a value for h-acc40S. */ 615 616 void 617 frvbf_h_acc40S_set (SIM_CPU *current_cpu, UINT regno, DI newval) 618 { 619 SET_H_ACC40S (regno, newval); 620 } 621 622 /* Get the value of h-acc40U. */ 623 624 UDI 625 frvbf_h_acc40U_get (SIM_CPU *current_cpu, UINT regno) 626 { 627 return GET_H_ACC40U (regno); 628 } 629 630 /* Set a value for h-acc40U. */ 631 632 void 633 frvbf_h_acc40U_set (SIM_CPU *current_cpu, UINT regno, UDI newval) 634 { 635 SET_H_ACC40U (regno, newval); 636 } 637 638 /* Get the value of h-iacc0. */ 639 640 DI 641 frvbf_h_iacc0_get (SIM_CPU *current_cpu, UINT regno) 642 { 643 return GET_H_IACC0 (regno); 644 } 645 646 /* Set a value for h-iacc0. */ 647 648 void 649 frvbf_h_iacc0_set (SIM_CPU *current_cpu, UINT regno, DI newval) 650 { 651 SET_H_IACC0 (regno, newval); 652 } 653 654 /* Get the value of h-iccr. */ 655 656 UQI 657 frvbf_h_iccr_get (SIM_CPU *current_cpu, UINT regno) 658 { 659 return CPU (h_iccr[regno]); 660 } 661 662 /* Set a value for h-iccr. */ 663 664 void 665 frvbf_h_iccr_set (SIM_CPU *current_cpu, UINT regno, UQI newval) 666 { 667 CPU (h_iccr[regno]) = newval; 668 } 669 670 /* Get the value of h-fccr. */ 671 672 UQI 673 frvbf_h_fccr_get (SIM_CPU *current_cpu, UINT regno) 674 { 675 return CPU (h_fccr[regno]); 676 } 677 678 /* Set a value for h-fccr. */ 679 680 void 681 frvbf_h_fccr_set (SIM_CPU *current_cpu, UINT regno, UQI newval) 682 { 683 CPU (h_fccr[regno]) = newval; 684 } 685 686 /* Get the value of h-cccr. */ 687 688 UQI 689 frvbf_h_cccr_get (SIM_CPU *current_cpu, UINT regno) 690 { 691 return CPU (h_cccr[regno]); 692 } 693 694 /* Set a value for h-cccr. */ 695 696 void 697 frvbf_h_cccr_set (SIM_CPU *current_cpu, UINT regno, UQI newval) 698 { 699 CPU (h_cccr[regno]) = newval; 700 } 701 702 /* Record trace results for INSN. */ 703 704 void 705 frvbf_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn, 706 int *indices, TRACE_RECORD *tr) 707 { 708 } 709