1 #include "config.h" 2 #include <signal.h> 3 #include "bfd.h" 4 #include "gdb/callback.h" 5 #include "gdb/remote-sim.h" 6 7 #include "d10v_sim.h" 8 #include "gdb/sim-d10v.h" 9 #include "gdb/signals.h" 10 11 #ifdef HAVE_STRING_H 12 #include <string.h> 13 #else 14 #ifdef HAVE_STRINGS_H 15 #include <strings.h> 16 #endif /* HAVE_STRING_H */ 17 #endif /* HAVE_STRINGS_H */ 18 19 #ifdef HAVE_STDLIB_H 20 #include <stdlib.h> 21 #endif 22 23 enum _leftright { LEFT_FIRST, RIGHT_FIRST }; 24 25 static char *myname; 26 static SIM_OPEN_KIND sim_kind; 27 int d10v_debug; 28 29 /* Set this to true to get the previous segment layout. */ 30 31 int old_segment_mapping; 32 33 host_callback *d10v_callback; 34 unsigned long ins_type_counters[ (int)INS_MAX ]; 35 36 uint16 OP[4]; 37 38 static int init_text_p = 0; 39 /* non-zero if we opened prog_bfd */ 40 static int prog_bfd_was_opened_p; 41 bfd *prog_bfd; 42 asection *text; 43 bfd_vma text_start; 44 bfd_vma text_end; 45 46 static long hash (long insn, int format); 47 static struct hash_entry *lookup_hash (uint32 ins, int size); 48 static void get_operands (struct simops *s, uint32 ins); 49 static void do_long (uint32 ins); 50 static void do_2_short (uint16 ins1, uint16 ins2, enum _leftright leftright); 51 static void do_parallel (uint16 ins1, uint16 ins2); 52 static char *add_commas (char *buf, int sizeof_buf, unsigned long value); 53 extern void sim_set_profile (int n); 54 extern void sim_set_profile_size (int n); 55 static INLINE uint8 *map_memory (unsigned phys_addr); 56 57 #ifdef NEED_UI_LOOP_HOOK 58 /* How often to run the ui_loop update, when in use */ 59 #define UI_LOOP_POLL_INTERVAL 0x14000 60 61 /* Counter for the ui_loop_hook update */ 62 static long ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL; 63 64 /* Actual hook to call to run through gdb's gui event loop */ 65 extern int (*deprecated_ui_loop_hook) (int signo); 66 #endif /* NEED_UI_LOOP_HOOK */ 67 68 #ifndef INLINE 69 #if defined(__GNUC__) && defined(__OPTIMIZE__) 70 #define INLINE __inline__ 71 #else 72 #define INLINE 73 #endif 74 #endif 75 76 #define MAX_HASH 63 77 struct hash_entry 78 { 79 struct hash_entry *next; 80 uint32 opcode; 81 uint32 mask; 82 int size; 83 struct simops *ops; 84 }; 85 86 struct hash_entry hash_table[MAX_HASH+1]; 87 88 INLINE static long 89 hash(insn, format) 90 long insn; 91 int format; 92 { 93 if (format & LONG_OPCODE) 94 return ((insn & 0x3F000000) >> 24); 95 else 96 return((insn & 0x7E00) >> 9); 97 } 98 99 INLINE static struct hash_entry * 100 lookup_hash (ins, size) 101 uint32 ins; 102 int size; 103 { 104 struct hash_entry *h; 105 106 if (size) 107 h = &hash_table[(ins & 0x3F000000) >> 24]; 108 else 109 h = &hash_table[(ins & 0x7E00) >> 9]; 110 111 while ((ins & h->mask) != h->opcode || h->size != size) 112 { 113 if (h->next == NULL) 114 { 115 State.exception = SIGILL; 116 State.pc_changed = 1; /* Don't increment the PC. */ 117 return NULL; 118 } 119 h = h->next; 120 } 121 return (h); 122 } 123 124 INLINE static void 125 get_operands (struct simops *s, uint32 ins) 126 { 127 int i, shift, bits, flags; 128 uint32 mask; 129 for (i=0; i < s->numops; i++) 130 { 131 shift = s->operands[3*i]; 132 bits = s->operands[3*i+1]; 133 flags = s->operands[3*i+2]; 134 mask = 0x7FFFFFFF >> (31 - bits); 135 OP[i] = (ins >> shift) & mask; 136 } 137 /* FIXME: for tracing, update values that need to be updated each 138 instruction decode cycle */ 139 State.trace.psw = PSW; 140 } 141 142 bfd_vma 143 decode_pc () 144 { 145 asection *s; 146 if (!init_text_p && prog_bfd != NULL) 147 { 148 init_text_p = 1; 149 for (s = prog_bfd->sections; s; s = s->next) 150 if (strcmp (bfd_get_section_name (prog_bfd, s), ".text") == 0) 151 { 152 text = s; 153 text_start = bfd_get_section_vma (prog_bfd, s); 154 text_end = text_start + bfd_section_size (prog_bfd, s); 155 break; 156 } 157 } 158 159 return (PC << 2) + text_start; 160 } 161 162 static void 163 do_long (ins) 164 uint32 ins; 165 { 166 struct hash_entry *h; 167 #ifdef DEBUG 168 if ((d10v_debug & DEBUG_INSTRUCTION) != 0) 169 (*d10v_callback->printf_filtered) (d10v_callback, "do_long 0x%x\n", ins); 170 #endif 171 h = lookup_hash (ins, 1); 172 if (h == NULL) 173 return; 174 get_operands (h->ops, ins); 175 State.ins_type = INS_LONG; 176 ins_type_counters[ (int)State.ins_type ]++; 177 (h->ops->func)(); 178 } 179 180 static void 181 do_2_short (ins1, ins2, leftright) 182 uint16 ins1, ins2; 183 enum _leftright leftright; 184 { 185 struct hash_entry *h; 186 enum _ins_type first, second; 187 188 #ifdef DEBUG 189 if ((d10v_debug & DEBUG_INSTRUCTION) != 0) 190 (*d10v_callback->printf_filtered) (d10v_callback, "do_2_short 0x%x (%s) -> 0x%x\n", 191 ins1, (leftright) ? "left" : "right", ins2); 192 #endif 193 194 if (leftright == LEFT_FIRST) 195 { 196 first = INS_LEFT; 197 second = INS_RIGHT; 198 ins_type_counters[ (int)INS_LEFTRIGHT ]++; 199 } 200 else 201 { 202 first = INS_RIGHT; 203 second = INS_LEFT; 204 ins_type_counters[ (int)INS_RIGHTLEFT ]++; 205 } 206 207 /* Issue the first instruction */ 208 h = lookup_hash (ins1, 0); 209 if (h == NULL) 210 return; 211 get_operands (h->ops, ins1); 212 State.ins_type = first; 213 ins_type_counters[ (int)State.ins_type ]++; 214 (h->ops->func)(); 215 216 /* Issue the second instruction (if the PC hasn't changed) */ 217 if (!State.pc_changed && !State.exception) 218 { 219 /* finish any existing instructions */ 220 SLOT_FLUSH (); 221 h = lookup_hash (ins2, 0); 222 if (h == NULL) 223 return; 224 get_operands (h->ops, ins2); 225 State.ins_type = second; 226 ins_type_counters[ (int)State.ins_type ]++; 227 ins_type_counters[ (int)INS_CYCLES ]++; 228 (h->ops->func)(); 229 } 230 else if (!State.exception) 231 ins_type_counters[ (int)INS_COND_JUMP ]++; 232 } 233 234 static void 235 do_parallel (ins1, ins2) 236 uint16 ins1, ins2; 237 { 238 struct hash_entry *h1, *h2; 239 #ifdef DEBUG 240 if ((d10v_debug & DEBUG_INSTRUCTION) != 0) 241 (*d10v_callback->printf_filtered) (d10v_callback, "do_parallel 0x%x || 0x%x\n", ins1, ins2); 242 #endif 243 ins_type_counters[ (int)INS_PARALLEL ]++; 244 h1 = lookup_hash (ins1, 0); 245 if (h1 == NULL) 246 return; 247 h2 = lookup_hash (ins2, 0); 248 if (h2 == NULL) 249 return; 250 251 if (h1->ops->exec_type == PARONLY) 252 { 253 get_operands (h1->ops, ins1); 254 State.ins_type = INS_LEFT_COND_TEST; 255 ins_type_counters[ (int)State.ins_type ]++; 256 (h1->ops->func)(); 257 if (State.exe) 258 { 259 ins_type_counters[ (int)INS_COND_TRUE ]++; 260 get_operands (h2->ops, ins2); 261 State.ins_type = INS_RIGHT_COND_EXE; 262 ins_type_counters[ (int)State.ins_type ]++; 263 (h2->ops->func)(); 264 } 265 else 266 ins_type_counters[ (int)INS_COND_FALSE ]++; 267 } 268 else if (h2->ops->exec_type == PARONLY) 269 { 270 get_operands (h2->ops, ins2); 271 State.ins_type = INS_RIGHT_COND_TEST; 272 ins_type_counters[ (int)State.ins_type ]++; 273 (h2->ops->func)(); 274 if (State.exe) 275 { 276 ins_type_counters[ (int)INS_COND_TRUE ]++; 277 get_operands (h1->ops, ins1); 278 State.ins_type = INS_LEFT_COND_EXE; 279 ins_type_counters[ (int)State.ins_type ]++; 280 (h1->ops->func)(); 281 } 282 else 283 ins_type_counters[ (int)INS_COND_FALSE ]++; 284 } 285 else 286 { 287 get_operands (h1->ops, ins1); 288 State.ins_type = INS_LEFT_PARALLEL; 289 ins_type_counters[ (int)State.ins_type ]++; 290 (h1->ops->func)(); 291 if (!State.exception) 292 { 293 get_operands (h2->ops, ins2); 294 State.ins_type = INS_RIGHT_PARALLEL; 295 ins_type_counters[ (int)State.ins_type ]++; 296 (h2->ops->func)(); 297 } 298 } 299 } 300 301 static char * 302 add_commas(buf, sizeof_buf, value) 303 char *buf; 304 int sizeof_buf; 305 unsigned long value; 306 { 307 int comma = 3; 308 char *endbuf = buf + sizeof_buf - 1; 309 310 *--endbuf = '\0'; 311 do { 312 if (comma-- == 0) 313 { 314 *--endbuf = ','; 315 comma = 2; 316 } 317 318 *--endbuf = (value % 10) + '0'; 319 } while ((value /= 10) != 0); 320 321 return endbuf; 322 } 323 324 void 325 sim_size (power) 326 int power; 327 328 { 329 int i; 330 for (i = 0; i < IMEM_SEGMENTS; i++) 331 { 332 if (State.mem.insn[i]) 333 free (State.mem.insn[i]); 334 } 335 for (i = 0; i < DMEM_SEGMENTS; i++) 336 { 337 if (State.mem.data[i]) 338 free (State.mem.data[i]); 339 } 340 for (i = 0; i < UMEM_SEGMENTS; i++) 341 { 342 if (State.mem.unif[i]) 343 free (State.mem.unif[i]); 344 } 345 /* Always allocate dmem segment 0. This contains the IMAP and DMAP 346 registers. */ 347 State.mem.data[0] = calloc (1, SEGMENT_SIZE); 348 } 349 350 /* For tracing - leave info on last access around. */ 351 static char *last_segname = "invalid"; 352 static char *last_from = "invalid"; 353 static char *last_to = "invalid"; 354 355 enum 356 { 357 IMAP0_OFFSET = 0xff00, 358 DMAP0_OFFSET = 0xff08, 359 DMAP2_SHADDOW = 0xff04, 360 DMAP2_OFFSET = 0xff0c 361 }; 362 363 static void 364 set_dmap_register (int reg_nr, unsigned long value) 365 { 366 uint8 *raw = map_memory (SIM_D10V_MEMORY_DATA 367 + DMAP0_OFFSET + 2 * reg_nr); 368 WRITE_16 (raw, value); 369 #ifdef DEBUG 370 if ((d10v_debug & DEBUG_MEMORY)) 371 { 372 (*d10v_callback->printf_filtered) 373 (d10v_callback, "mem: dmap%d=0x%04lx\n", reg_nr, value); 374 } 375 #endif 376 } 377 378 static unsigned long 379 dmap_register (void *regcache, int reg_nr) 380 { 381 uint8 *raw = map_memory (SIM_D10V_MEMORY_DATA 382 + DMAP0_OFFSET + 2 * reg_nr); 383 return READ_16 (raw); 384 } 385 386 static void 387 set_imap_register (int reg_nr, unsigned long value) 388 { 389 uint8 *raw = map_memory (SIM_D10V_MEMORY_DATA 390 + IMAP0_OFFSET + 2 * reg_nr); 391 WRITE_16 (raw, value); 392 #ifdef DEBUG 393 if ((d10v_debug & DEBUG_MEMORY)) 394 { 395 (*d10v_callback->printf_filtered) 396 (d10v_callback, "mem: imap%d=0x%04lx\n", reg_nr, value); 397 } 398 #endif 399 } 400 401 static unsigned long 402 imap_register (void *regcache, int reg_nr) 403 { 404 uint8 *raw = map_memory (SIM_D10V_MEMORY_DATA 405 + IMAP0_OFFSET + 2 * reg_nr); 406 return READ_16 (raw); 407 } 408 409 enum 410 { 411 HELD_SPI_IDX = 0, 412 HELD_SPU_IDX = 1 413 }; 414 415 static unsigned long 416 spu_register (void) 417 { 418 if (PSW_SM) 419 return GPR (SP_IDX); 420 else 421 return HELD_SP (HELD_SPU_IDX); 422 } 423 424 static unsigned long 425 spi_register (void) 426 { 427 if (!PSW_SM) 428 return GPR (SP_IDX); 429 else 430 return HELD_SP (HELD_SPI_IDX); 431 } 432 433 static void 434 set_spi_register (unsigned long value) 435 { 436 if (!PSW_SM) 437 SET_GPR (SP_IDX, value); 438 SET_HELD_SP (HELD_SPI_IDX, value); 439 } 440 441 static void 442 set_spu_register (unsigned long value) 443 { 444 if (PSW_SM) 445 SET_GPR (SP_IDX, value); 446 SET_HELD_SP (HELD_SPU_IDX, value); 447 } 448 449 /* Given a virtual address in the DMAP address space, translate it 450 into a physical address. */ 451 452 unsigned long 453 sim_d10v_translate_dmap_addr (unsigned long offset, 454 int nr_bytes, 455 unsigned long *phys, 456 void *regcache, 457 unsigned long (*dmap_register) (void *regcache, 458 int reg_nr)) 459 { 460 short map; 461 int regno; 462 last_from = "logical-data"; 463 if (offset >= DMAP_BLOCK_SIZE * SIM_D10V_NR_DMAP_REGS) 464 { 465 /* Logical address out side of data segments, not supported */ 466 return 0; 467 } 468 regno = (offset / DMAP_BLOCK_SIZE); 469 offset = (offset % DMAP_BLOCK_SIZE); 470 if ((offset % DMAP_BLOCK_SIZE) + nr_bytes > DMAP_BLOCK_SIZE) 471 { 472 /* Don't cross a BLOCK boundary */ 473 nr_bytes = DMAP_BLOCK_SIZE - (offset % DMAP_BLOCK_SIZE); 474 } 475 map = dmap_register (regcache, regno); 476 if (regno == 3) 477 { 478 /* Always maps to data memory */ 479 int iospi = (offset / 0x1000) % 4; 480 int iosp = (map >> (4 * (3 - iospi))) % 0x10; 481 last_to = "io-space"; 482 *phys = (SIM_D10V_MEMORY_DATA + (iosp * 0x10000) + 0xc000 + offset); 483 } 484 else 485 { 486 int sp = ((map & 0x3000) >> 12); 487 int segno = (map & 0x3ff); 488 switch (sp) 489 { 490 case 0: /* 00: Unified memory */ 491 *phys = SIM_D10V_MEMORY_UNIFIED + (segno * DMAP_BLOCK_SIZE) + offset; 492 last_to = "unified"; 493 break; 494 case 1: /* 01: Instruction Memory */ 495 *phys = SIM_D10V_MEMORY_INSN + (segno * DMAP_BLOCK_SIZE) + offset; 496 last_to = "chip-insn"; 497 break; 498 case 2: /* 10: Internal data memory */ 499 *phys = SIM_D10V_MEMORY_DATA + (segno << 16) + (regno * DMAP_BLOCK_SIZE) + offset; 500 last_to = "chip-data"; 501 break; 502 case 3: /* 11: Reserved */ 503 return 0; 504 } 505 } 506 return nr_bytes; 507 } 508 509 /* Given a virtual address in the IMAP address space, translate it 510 into a physical address. */ 511 512 unsigned long 513 sim_d10v_translate_imap_addr (unsigned long offset, 514 int nr_bytes, 515 unsigned long *phys, 516 void *regcache, 517 unsigned long (*imap_register) (void *regcache, 518 int reg_nr)) 519 { 520 short map; 521 int regno; 522 int sp; 523 int segno; 524 last_from = "logical-insn"; 525 if (offset >= (IMAP_BLOCK_SIZE * SIM_D10V_NR_IMAP_REGS)) 526 { 527 /* Logical address outside of IMAP segments, not supported */ 528 return 0; 529 } 530 regno = (offset / IMAP_BLOCK_SIZE); 531 offset = (offset % IMAP_BLOCK_SIZE); 532 if (offset + nr_bytes > IMAP_BLOCK_SIZE) 533 { 534 /* Don't cross a BLOCK boundary */ 535 nr_bytes = IMAP_BLOCK_SIZE - offset; 536 } 537 map = imap_register (regcache, regno); 538 sp = (map & 0x3000) >> 12; 539 segno = (map & 0x007f); 540 switch (sp) 541 { 542 case 0: /* 00: unified memory */ 543 *phys = SIM_D10V_MEMORY_UNIFIED + (segno << 17) + offset; 544 last_to = "unified"; 545 break; 546 case 1: /* 01: instruction memory */ 547 *phys = SIM_D10V_MEMORY_INSN + (IMAP_BLOCK_SIZE * regno) + offset; 548 last_to = "chip-insn"; 549 break; 550 case 2: /*10*/ 551 /* Reserved. */ 552 return 0; 553 case 3: /* 11: for testing - instruction memory */ 554 offset = (offset % 0x800); 555 *phys = SIM_D10V_MEMORY_INSN + offset; 556 if (offset + nr_bytes > 0x800) 557 /* don't cross VM boundary */ 558 nr_bytes = 0x800 - offset; 559 last_to = "test-insn"; 560 break; 561 } 562 return nr_bytes; 563 } 564 565 unsigned long 566 sim_d10v_translate_addr (unsigned long memaddr, 567 int nr_bytes, 568 unsigned long *targ_addr, 569 void *regcache, 570 unsigned long (*dmap_register) (void *regcache, 571 int reg_nr), 572 unsigned long (*imap_register) (void *regcache, 573 int reg_nr)) 574 { 575 unsigned long phys; 576 unsigned long seg; 577 unsigned long off; 578 579 last_from = "unknown"; 580 last_to = "unknown"; 581 582 seg = (memaddr >> 24); 583 off = (memaddr & 0xffffffL); 584 585 /* However, if we've asked to use the previous generation of segment 586 mapping, rearrange the segments as follows. */ 587 588 if (old_segment_mapping) 589 { 590 switch (seg) 591 { 592 case 0x00: /* DMAP translated memory */ 593 seg = 0x10; 594 break; 595 case 0x01: /* IMAP translated memory */ 596 seg = 0x11; 597 break; 598 case 0x10: /* On-chip data memory */ 599 seg = 0x02; 600 break; 601 case 0x11: /* On-chip insn memory */ 602 seg = 0x01; 603 break; 604 case 0x12: /* Unified memory */ 605 seg = 0x00; 606 break; 607 } 608 } 609 610 switch (seg) 611 { 612 case 0x00: /* Physical unified memory */ 613 last_from = "phys-unified"; 614 last_to = "unified"; 615 phys = SIM_D10V_MEMORY_UNIFIED + off; 616 if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE) 617 nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE); 618 break; 619 620 case 0x01: /* Physical instruction memory */ 621 last_from = "phys-insn"; 622 last_to = "chip-insn"; 623 phys = SIM_D10V_MEMORY_INSN + off; 624 if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE) 625 nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE); 626 break; 627 628 case 0x02: /* Physical data memory segment */ 629 last_from = "phys-data"; 630 last_to = "chip-data"; 631 phys = SIM_D10V_MEMORY_DATA + off; 632 if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE) 633 nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE); 634 break; 635 636 case 0x10: /* in logical data address segment */ 637 nr_bytes = sim_d10v_translate_dmap_addr (off, nr_bytes, &phys, regcache, 638 dmap_register); 639 break; 640 641 case 0x11: /* in logical instruction address segment */ 642 nr_bytes = sim_d10v_translate_imap_addr (off, nr_bytes, &phys, regcache, 643 imap_register); 644 break; 645 646 default: 647 return 0; 648 } 649 650 *targ_addr = phys; 651 return nr_bytes; 652 } 653 654 /* Return a pointer into the raw buffer designated by phys_addr. It 655 is assumed that the client has already ensured that the access 656 isn't going to cross a segment boundary. */ 657 658 uint8 * 659 map_memory (unsigned phys_addr) 660 { 661 uint8 **memory; 662 uint8 *raw; 663 unsigned offset; 664 int segment = ((phys_addr >> 24) & 0xff); 665 666 switch (segment) 667 { 668 669 case 0x00: /* Unified memory */ 670 { 671 memory = &State.mem.unif[(phys_addr / SEGMENT_SIZE) % UMEM_SEGMENTS]; 672 last_segname = "umem"; 673 break; 674 } 675 676 case 0x01: /* On-chip insn memory */ 677 { 678 memory = &State.mem.insn[(phys_addr / SEGMENT_SIZE) % IMEM_SEGMENTS]; 679 last_segname = "imem"; 680 break; 681 } 682 683 case 0x02: /* On-chip data memory */ 684 { 685 if ((phys_addr & 0xff00) == 0xff00) 686 { 687 phys_addr = (phys_addr & 0xffff); 688 if (phys_addr == DMAP2_SHADDOW) 689 { 690 phys_addr = DMAP2_OFFSET; 691 last_segname = "dmap"; 692 } 693 else 694 last_segname = "reg"; 695 } 696 else 697 last_segname = "dmem"; 698 memory = &State.mem.data[(phys_addr / SEGMENT_SIZE) % DMEM_SEGMENTS]; 699 break; 700 } 701 702 default: 703 /* OOPS! */ 704 last_segname = "scrap"; 705 return State.mem.fault; 706 } 707 708 if (*memory == NULL) 709 { 710 *memory = calloc (1, SEGMENT_SIZE); 711 if (*memory == NULL) 712 { 713 (*d10v_callback->printf_filtered) (d10v_callback, "Malloc failed.\n"); 714 return State.mem.fault; 715 } 716 } 717 718 offset = (phys_addr % SEGMENT_SIZE); 719 raw = *memory + offset; 720 return raw; 721 } 722 723 /* Transfer data to/from simulated memory. Since a bug in either the 724 simulated program or in gdb or the simulator itself may cause a 725 bogus address to be passed in, we need to do some sanity checking 726 on addresses to make sure they are within bounds. When an address 727 fails the bounds check, treat it as a zero length read/write rather 728 than aborting the entire run. */ 729 730 static int 731 xfer_mem (SIM_ADDR virt, 732 unsigned char *buffer, 733 int size, 734 int write_p) 735 { 736 uint8 *memory; 737 unsigned long phys; 738 int phys_size; 739 phys_size = sim_d10v_translate_addr (virt, size, &phys, NULL, 740 dmap_register, imap_register); 741 if (phys_size == 0) 742 return 0; 743 744 memory = map_memory (phys); 745 746 #ifdef DEBUG 747 if ((d10v_debug & DEBUG_INSTRUCTION) != 0) 748 { 749 (*d10v_callback->printf_filtered) 750 (d10v_callback, 751 "sim_%s %d bytes: 0x%08lx (%s) -> 0x%08lx (%s) -> 0x%08lx (%s)\n", 752 (write_p ? "write" : "read"), 753 phys_size, virt, last_from, 754 phys, last_to, 755 (long) memory, last_segname); 756 } 757 #endif 758 759 if (write_p) 760 { 761 memcpy (memory, buffer, phys_size); 762 } 763 else 764 { 765 memcpy (buffer, memory, phys_size); 766 } 767 768 return phys_size; 769 } 770 771 772 int 773 sim_write (sd, addr, buffer, size) 774 SIM_DESC sd; 775 SIM_ADDR addr; 776 const unsigned char *buffer; 777 int size; 778 { 779 /* FIXME: this should be performing a virtual transfer */ 780 return xfer_mem( addr, buffer, size, 1); 781 } 782 783 int 784 sim_read (sd, addr, buffer, size) 785 SIM_DESC sd; 786 SIM_ADDR addr; 787 unsigned char *buffer; 788 int size; 789 { 790 /* FIXME: this should be performing a virtual transfer */ 791 return xfer_mem( addr, buffer, size, 0); 792 } 793 794 795 SIM_DESC 796 sim_open (kind, callback, abfd, argv) 797 SIM_OPEN_KIND kind; 798 host_callback *callback; 799 struct bfd *abfd; 800 char **argv; 801 { 802 struct simops *s; 803 struct hash_entry *h; 804 static int init_p = 0; 805 char **p; 806 807 sim_kind = kind; 808 d10v_callback = callback; 809 myname = argv[0]; 810 old_segment_mapping = 0; 811 812 /* NOTE: This argument parsing is only effective when this function 813 is called by GDB. Standalone argument parsing is handled by 814 sim/common/run.c. */ 815 for (p = argv + 1; *p; ++p) 816 { 817 if (strcmp (*p, "-oldseg") == 0) 818 old_segment_mapping = 1; 819 #ifdef DEBUG 820 else if (strcmp (*p, "-t") == 0) 821 d10v_debug = DEBUG; 822 else if (strncmp (*p, "-t", 2) == 0) 823 d10v_debug = atoi (*p + 2); 824 #endif 825 else 826 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: unsupported option(s): %s\n",*p); 827 } 828 829 /* put all the opcodes in the hash table */ 830 if (!init_p++) 831 { 832 for (s = Simops; s->func; s++) 833 { 834 h = &hash_table[hash(s->opcode,s->format)]; 835 836 /* go to the last entry in the chain */ 837 while (h->next) 838 h = h->next; 839 840 if (h->ops) 841 { 842 h->next = (struct hash_entry *) calloc(1,sizeof(struct hash_entry)); 843 if (!h->next) 844 perror ("malloc failure"); 845 846 h = h->next; 847 } 848 h->ops = s; 849 h->mask = s->mask; 850 h->opcode = s->opcode; 851 h->size = s->is_long; 852 } 853 } 854 855 /* reset the processor state */ 856 if (!State.mem.data[0]) 857 sim_size (1); 858 sim_create_inferior ((SIM_DESC) 1, NULL, NULL, NULL); 859 860 /* Fudge our descriptor. */ 861 return (SIM_DESC) 1; 862 } 863 864 865 void 866 sim_close (sd, quitting) 867 SIM_DESC sd; 868 int quitting; 869 { 870 if (prog_bfd != NULL && prog_bfd_was_opened_p) 871 { 872 bfd_close (prog_bfd); 873 prog_bfd = NULL; 874 prog_bfd_was_opened_p = 0; 875 } 876 } 877 878 void 879 sim_set_profile (n) 880 int n; 881 { 882 (*d10v_callback->printf_filtered) (d10v_callback, "sim_set_profile %d\n",n); 883 } 884 885 void 886 sim_set_profile_size (n) 887 int n; 888 { 889 (*d10v_callback->printf_filtered) (d10v_callback, "sim_set_profile_size %d\n",n); 890 } 891 892 uint8 * 893 dmem_addr (uint16 offset) 894 { 895 unsigned long phys; 896 uint8 *mem; 897 int phys_size; 898 899 /* Note: DMEM address range is 0..0x10000. Calling code can compute 900 things like ``0xfffe + 0x0e60 == 0x10e5d''. Since offset's type 901 is uint16 this is modulo'ed onto 0x0e5d. */ 902 903 phys_size = sim_d10v_translate_dmap_addr (offset, 1, &phys, NULL, 904 dmap_register); 905 if (phys_size == 0) 906 { 907 mem = State.mem.fault; 908 } 909 else 910 mem = map_memory (phys); 911 #ifdef DEBUG 912 if ((d10v_debug & DEBUG_MEMORY)) 913 { 914 (*d10v_callback->printf_filtered) 915 (d10v_callback, 916 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n", 917 offset, last_from, 918 phys, phys_size, last_to, 919 (long) mem, last_segname); 920 } 921 #endif 922 return mem; 923 } 924 925 uint8 * 926 imem_addr (uint32 offset) 927 { 928 unsigned long phys; 929 uint8 *mem; 930 int phys_size = sim_d10v_translate_imap_addr (offset, 1, &phys, NULL, 931 imap_register); 932 if (phys_size == 0) 933 { 934 return State.mem.fault; 935 } 936 mem = map_memory (phys); 937 #ifdef DEBUG 938 if ((d10v_debug & DEBUG_MEMORY)) 939 { 940 (*d10v_callback->printf_filtered) 941 (d10v_callback, 942 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n", 943 offset, last_from, 944 phys, phys_size, last_to, 945 (long) mem, last_segname); 946 } 947 #endif 948 return mem; 949 } 950 951 static int stop_simulator = 0; 952 953 int 954 sim_stop (sd) 955 SIM_DESC sd; 956 { 957 stop_simulator = 1; 958 return 1; 959 } 960 961 962 /* Run (or resume) the program. */ 963 void 964 sim_resume (sd, step, siggnal) 965 SIM_DESC sd; 966 int step, siggnal; 967 { 968 uint32 inst; 969 uint8 *iaddr; 970 971 /* (*d10v_callback->printf_filtered) (d10v_callback, "sim_resume (%d,%d) PC=0x%x\n",step,siggnal,PC); */ 972 State.exception = 0; 973 if (step) 974 sim_stop (sd); 975 976 switch (siggnal) 977 { 978 case 0: 979 break; 980 #ifdef SIGBUS 981 case SIGBUS: 982 #endif 983 case SIGSEGV: 984 SET_BPC (PC); 985 SET_BPSW (PSW); 986 SET_HW_PSW ((PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT))); 987 JMP (AE_VECTOR_START); 988 SLOT_FLUSH (); 989 break; 990 case SIGILL: 991 SET_BPC (PC); 992 SET_BPSW (PSW); 993 SET_HW_PSW ((PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT))); 994 JMP (RIE_VECTOR_START); 995 SLOT_FLUSH (); 996 break; 997 default: 998 /* just ignore it */ 999 break; 1000 } 1001 1002 do 1003 { 1004 iaddr = imem_addr ((uint32)PC << 2); 1005 if (iaddr == State.mem.fault) 1006 { 1007 State.exception = SIGBUS; 1008 break; 1009 } 1010 1011 inst = get_longword( iaddr ); 1012 1013 State.pc_changed = 0; 1014 ins_type_counters[ (int)INS_CYCLES ]++; 1015 1016 switch (inst & 0xC0000000) 1017 { 1018 case 0xC0000000: 1019 /* long instruction */ 1020 do_long (inst & 0x3FFFFFFF); 1021 break; 1022 case 0x80000000: 1023 /* R -> L */ 1024 do_2_short ( inst & 0x7FFF, (inst & 0x3FFF8000) >> 15, RIGHT_FIRST); 1025 break; 1026 case 0x40000000: 1027 /* L -> R */ 1028 do_2_short ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF, LEFT_FIRST); 1029 break; 1030 case 0: 1031 do_parallel ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF); 1032 break; 1033 } 1034 1035 /* If the PC of the current instruction matches RPT_E then 1036 schedule a branch to the loop start. If one of those 1037 instructions happens to be a branch, than that instruction 1038 will be ignored */ 1039 if (!State.pc_changed) 1040 { 1041 if (PSW_RP && PC == RPT_E) 1042 { 1043 /* Note: The behavour of a branch instruction at RPT_E 1044 is implementation dependant, this simulator takes the 1045 branch. Branching to RPT_E is valid, the instruction 1046 must be executed before the loop is taken. */ 1047 if (RPT_C == 1) 1048 { 1049 SET_PSW_RP (0); 1050 SET_RPT_C (0); 1051 SET_PC (PC + 1); 1052 } 1053 else 1054 { 1055 SET_RPT_C (RPT_C - 1); 1056 SET_PC (RPT_S); 1057 } 1058 } 1059 else 1060 SET_PC (PC + 1); 1061 } 1062 1063 /* Check for a breakpoint trap on this instruction. This 1064 overrides any pending branches or loops */ 1065 if (PSW_DB && PC == IBA) 1066 { 1067 SET_BPC (PC); 1068 SET_BPSW (PSW); 1069 SET_PSW (PSW & PSW_SM_BIT); 1070 SET_PC (SDBT_VECTOR_START); 1071 } 1072 1073 /* Writeback all the DATA / PC changes */ 1074 SLOT_FLUSH (); 1075 1076 #ifdef NEED_UI_LOOP_HOOK 1077 if (deprecated_ui_loop_hook != NULL && ui_loop_hook_counter-- < 0) 1078 { 1079 ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL; 1080 deprecated_ui_loop_hook (0); 1081 } 1082 #endif /* NEED_UI_LOOP_HOOK */ 1083 } 1084 while ( !State.exception && !stop_simulator); 1085 1086 if (step && !State.exception) 1087 State.exception = SIGTRAP; 1088 } 1089 1090 void 1091 sim_set_trace (void) 1092 { 1093 #ifdef DEBUG 1094 d10v_debug = DEBUG; 1095 #endif 1096 } 1097 1098 void 1099 sim_info (sd, verbose) 1100 SIM_DESC sd; 1101 int verbose; 1102 { 1103 char buf1[40]; 1104 char buf2[40]; 1105 char buf3[40]; 1106 char buf4[40]; 1107 char buf5[40]; 1108 unsigned long left = ins_type_counters[ (int)INS_LEFT ] + ins_type_counters[ (int)INS_LEFT_COND_EXE ]; 1109 unsigned long left_nops = ins_type_counters[ (int)INS_LEFT_NOPS ]; 1110 unsigned long left_parallel = ins_type_counters[ (int)INS_LEFT_PARALLEL ]; 1111 unsigned long left_cond = ins_type_counters[ (int)INS_LEFT_COND_TEST ]; 1112 unsigned long left_total = left + left_parallel + left_cond + left_nops; 1113 1114 unsigned long right = ins_type_counters[ (int)INS_RIGHT ] + ins_type_counters[ (int)INS_RIGHT_COND_EXE ]; 1115 unsigned long right_nops = ins_type_counters[ (int)INS_RIGHT_NOPS ]; 1116 unsigned long right_parallel = ins_type_counters[ (int)INS_RIGHT_PARALLEL ]; 1117 unsigned long right_cond = ins_type_counters[ (int)INS_RIGHT_COND_TEST ]; 1118 unsigned long right_total = right + right_parallel + right_cond + right_nops; 1119 1120 unsigned long unknown = ins_type_counters[ (int)INS_UNKNOWN ]; 1121 unsigned long ins_long = ins_type_counters[ (int)INS_LONG ]; 1122 unsigned long parallel = ins_type_counters[ (int)INS_PARALLEL ]; 1123 unsigned long leftright = ins_type_counters[ (int)INS_LEFTRIGHT ]; 1124 unsigned long rightleft = ins_type_counters[ (int)INS_RIGHTLEFT ]; 1125 unsigned long cond_true = ins_type_counters[ (int)INS_COND_TRUE ]; 1126 unsigned long cond_false = ins_type_counters[ (int)INS_COND_FALSE ]; 1127 unsigned long cond_jump = ins_type_counters[ (int)INS_COND_JUMP ]; 1128 unsigned long cycles = ins_type_counters[ (int)INS_CYCLES ]; 1129 unsigned long total = (unknown + left_total + right_total + ins_long); 1130 1131 int size = strlen (add_commas (buf1, sizeof (buf1), total)); 1132 int parallel_size = strlen (add_commas (buf1, sizeof (buf1), 1133 (left_parallel > right_parallel) ? left_parallel : right_parallel)); 1134 int cond_size = strlen (add_commas (buf1, sizeof (buf1), (left_cond > right_cond) ? left_cond : right_cond)); 1135 int nop_size = strlen (add_commas (buf1, sizeof (buf1), (left_nops > right_nops) ? left_nops : right_nops)); 1136 int normal_size = strlen (add_commas (buf1, sizeof (buf1), (left > right) ? left : right)); 1137 1138 (*d10v_callback->printf_filtered) (d10v_callback, 1139 "executed %*s left instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n", 1140 size, add_commas (buf1, sizeof (buf1), left_total), 1141 normal_size, add_commas (buf2, sizeof (buf2), left), 1142 parallel_size, add_commas (buf3, sizeof (buf3), left_parallel), 1143 cond_size, add_commas (buf4, sizeof (buf4), left_cond), 1144 nop_size, add_commas (buf5, sizeof (buf5), left_nops)); 1145 1146 (*d10v_callback->printf_filtered) (d10v_callback, 1147 "executed %*s right instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n", 1148 size, add_commas (buf1, sizeof (buf1), right_total), 1149 normal_size, add_commas (buf2, sizeof (buf2), right), 1150 parallel_size, add_commas (buf3, sizeof (buf3), right_parallel), 1151 cond_size, add_commas (buf4, sizeof (buf4), right_cond), 1152 nop_size, add_commas (buf5, sizeof (buf5), right_nops)); 1153 1154 if (ins_long) 1155 (*d10v_callback->printf_filtered) (d10v_callback, 1156 "executed %*s long instruction(s)\n", 1157 size, add_commas (buf1, sizeof (buf1), ins_long)); 1158 1159 if (parallel) 1160 (*d10v_callback->printf_filtered) (d10v_callback, 1161 "executed %*s parallel instruction(s)\n", 1162 size, add_commas (buf1, sizeof (buf1), parallel)); 1163 1164 if (leftright) 1165 (*d10v_callback->printf_filtered) (d10v_callback, 1166 "executed %*s instruction(s) encoded L->R\n", 1167 size, add_commas (buf1, sizeof (buf1), leftright)); 1168 1169 if (rightleft) 1170 (*d10v_callback->printf_filtered) (d10v_callback, 1171 "executed %*s instruction(s) encoded R->L\n", 1172 size, add_commas (buf1, sizeof (buf1), rightleft)); 1173 1174 if (unknown) 1175 (*d10v_callback->printf_filtered) (d10v_callback, 1176 "executed %*s unknown instruction(s)\n", 1177 size, add_commas (buf1, sizeof (buf1), unknown)); 1178 1179 if (cond_true) 1180 (*d10v_callback->printf_filtered) (d10v_callback, 1181 "executed %*s instruction(s) due to EXExxx condition being true\n", 1182 size, add_commas (buf1, sizeof (buf1), cond_true)); 1183 1184 if (cond_false) 1185 (*d10v_callback->printf_filtered) (d10v_callback, 1186 "skipped %*s instruction(s) due to EXExxx condition being false\n", 1187 size, add_commas (buf1, sizeof (buf1), cond_false)); 1188 1189 if (cond_jump) 1190 (*d10v_callback->printf_filtered) (d10v_callback, 1191 "skipped %*s instruction(s) due to conditional branch succeeding\n", 1192 size, add_commas (buf1, sizeof (buf1), cond_jump)); 1193 1194 (*d10v_callback->printf_filtered) (d10v_callback, 1195 "executed %*s cycle(s)\n", 1196 size, add_commas (buf1, sizeof (buf1), cycles)); 1197 1198 (*d10v_callback->printf_filtered) (d10v_callback, 1199 "executed %*s total instructions\n", 1200 size, add_commas (buf1, sizeof (buf1), total)); 1201 } 1202 1203 SIM_RC 1204 sim_create_inferior (sd, abfd, argv, env) 1205 SIM_DESC sd; 1206 struct bfd *abfd; 1207 char **argv; 1208 char **env; 1209 { 1210 bfd_vma start_address; 1211 1212 /* reset all state information */ 1213 memset (&State.regs, 0, (int)&State.mem - (int)&State.regs); 1214 1215 /* There was a hack here to copy the values of argc and argv into r0 1216 and r1. The values were also saved into some high memory that 1217 won't be overwritten by the stack (0x7C00). The reason for doing 1218 this was to allow the 'run' program to accept arguments. Without 1219 the hack, this is not possible anymore. If the simulator is run 1220 from the debugger, arguments cannot be passed in, so this makes 1221 no difference. */ 1222 1223 /* set PC */ 1224 if (abfd != NULL) 1225 start_address = bfd_get_start_address (abfd); 1226 else 1227 start_address = 0xffc0 << 2; 1228 #ifdef DEBUG 1229 if (d10v_debug) 1230 (*d10v_callback->printf_filtered) (d10v_callback, "sim_create_inferior: PC=0x%lx\n", (long) start_address); 1231 #endif 1232 SET_CREG (PC_CR, start_address >> 2); 1233 1234 /* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board 1235 initializes imap0 and imap1 to 0x1000 as part of its ROM 1236 initialization. */ 1237 if (old_segment_mapping) 1238 { 1239 /* External memory startup. This is the HARD reset state. */ 1240 set_imap_register (0, 0x0000); 1241 set_imap_register (1, 0x007f); 1242 set_dmap_register (0, 0x2000); 1243 set_dmap_register (1, 0x2000); 1244 set_dmap_register (2, 0x0000); /* Old DMAP */ 1245 set_dmap_register (3, 0x0000); 1246 } 1247 else 1248 { 1249 /* Internal memory startup. This is the ROM intialized state. */ 1250 set_imap_register (0, 0x1000); 1251 set_imap_register (1, 0x1000); 1252 set_dmap_register (0, 0x2000); 1253 set_dmap_register (1, 0x2000); 1254 set_dmap_register (2, 0x2000); /* DMAP2 initial internal value is 1255 0x2000 on the new board. */ 1256 set_dmap_register (3, 0x0000); 1257 } 1258 1259 SLOT_FLUSH (); 1260 return SIM_RC_OK; 1261 } 1262 1263 1264 void 1265 sim_set_callbacks (p) 1266 host_callback *p; 1267 { 1268 d10v_callback = p; 1269 } 1270 1271 void 1272 sim_stop_reason (sd, reason, sigrc) 1273 SIM_DESC sd; 1274 enum sim_stop *reason; 1275 int *sigrc; 1276 { 1277 /* (*d10v_callback->printf_filtered) (d10v_callback, "sim_stop_reason: PC=0x%x\n",PC<<2); */ 1278 1279 switch (State.exception) 1280 { 1281 case SIG_D10V_STOP: /* stop instruction */ 1282 *reason = sim_exited; 1283 *sigrc = 0; 1284 break; 1285 1286 case SIG_D10V_EXIT: /* exit trap */ 1287 *reason = sim_exited; 1288 *sigrc = GPR (0); 1289 break; 1290 1291 case SIG_D10V_BUS: 1292 *reason = sim_stopped; 1293 *sigrc = GDB_SIGNAL_BUS; 1294 break; 1295 1296 default: /* some signal */ 1297 *reason = sim_stopped; 1298 if (stop_simulator && !State.exception) 1299 *sigrc = GDB_SIGNAL_INT; 1300 else 1301 *sigrc = State.exception; 1302 break; 1303 } 1304 1305 stop_simulator = 0; 1306 } 1307 1308 int 1309 sim_fetch_register (sd, rn, memory, length) 1310 SIM_DESC sd; 1311 int rn; 1312 unsigned char *memory; 1313 int length; 1314 { 1315 int size; 1316 switch ((enum sim_d10v_regs) rn) 1317 { 1318 case SIM_D10V_R0_REGNUM: 1319 case SIM_D10V_R1_REGNUM: 1320 case SIM_D10V_R2_REGNUM: 1321 case SIM_D10V_R3_REGNUM: 1322 case SIM_D10V_R4_REGNUM: 1323 case SIM_D10V_R5_REGNUM: 1324 case SIM_D10V_R6_REGNUM: 1325 case SIM_D10V_R7_REGNUM: 1326 case SIM_D10V_R8_REGNUM: 1327 case SIM_D10V_R9_REGNUM: 1328 case SIM_D10V_R10_REGNUM: 1329 case SIM_D10V_R11_REGNUM: 1330 case SIM_D10V_R12_REGNUM: 1331 case SIM_D10V_R13_REGNUM: 1332 case SIM_D10V_R14_REGNUM: 1333 case SIM_D10V_R15_REGNUM: 1334 WRITE_16 (memory, GPR (rn - SIM_D10V_R0_REGNUM)); 1335 size = 2; 1336 break; 1337 case SIM_D10V_CR0_REGNUM: 1338 case SIM_D10V_CR1_REGNUM: 1339 case SIM_D10V_CR2_REGNUM: 1340 case SIM_D10V_CR3_REGNUM: 1341 case SIM_D10V_CR4_REGNUM: 1342 case SIM_D10V_CR5_REGNUM: 1343 case SIM_D10V_CR6_REGNUM: 1344 case SIM_D10V_CR7_REGNUM: 1345 case SIM_D10V_CR8_REGNUM: 1346 case SIM_D10V_CR9_REGNUM: 1347 case SIM_D10V_CR10_REGNUM: 1348 case SIM_D10V_CR11_REGNUM: 1349 case SIM_D10V_CR12_REGNUM: 1350 case SIM_D10V_CR13_REGNUM: 1351 case SIM_D10V_CR14_REGNUM: 1352 case SIM_D10V_CR15_REGNUM: 1353 WRITE_16 (memory, CREG (rn - SIM_D10V_CR0_REGNUM)); 1354 size = 2; 1355 break; 1356 case SIM_D10V_A0_REGNUM: 1357 case SIM_D10V_A1_REGNUM: 1358 WRITE_64 (memory, ACC (rn - SIM_D10V_A0_REGNUM)); 1359 size = 8; 1360 break; 1361 case SIM_D10V_SPI_REGNUM: 1362 /* PSW_SM indicates that the current SP is the USER 1363 stack-pointer. */ 1364 WRITE_16 (memory, spi_register ()); 1365 size = 2; 1366 break; 1367 case SIM_D10V_SPU_REGNUM: 1368 /* PSW_SM indicates that the current SP is the USER 1369 stack-pointer. */ 1370 WRITE_16 (memory, spu_register ()); 1371 size = 2; 1372 break; 1373 case SIM_D10V_IMAP0_REGNUM: 1374 case SIM_D10V_IMAP1_REGNUM: 1375 WRITE_16 (memory, imap_register (NULL, rn - SIM_D10V_IMAP0_REGNUM)); 1376 size = 2; 1377 break; 1378 case SIM_D10V_DMAP0_REGNUM: 1379 case SIM_D10V_DMAP1_REGNUM: 1380 case SIM_D10V_DMAP2_REGNUM: 1381 case SIM_D10V_DMAP3_REGNUM: 1382 WRITE_16 (memory, dmap_register (NULL, rn - SIM_D10V_DMAP0_REGNUM)); 1383 size = 2; 1384 break; 1385 case SIM_D10V_TS2_DMAP_REGNUM: 1386 size = 0; 1387 break; 1388 default: 1389 size = 0; 1390 break; 1391 } 1392 return size; 1393 } 1394 1395 int 1396 sim_store_register (sd, rn, memory, length) 1397 SIM_DESC sd; 1398 int rn; 1399 unsigned char *memory; 1400 int length; 1401 { 1402 int size; 1403 switch ((enum sim_d10v_regs) rn) 1404 { 1405 case SIM_D10V_R0_REGNUM: 1406 case SIM_D10V_R1_REGNUM: 1407 case SIM_D10V_R2_REGNUM: 1408 case SIM_D10V_R3_REGNUM: 1409 case SIM_D10V_R4_REGNUM: 1410 case SIM_D10V_R5_REGNUM: 1411 case SIM_D10V_R6_REGNUM: 1412 case SIM_D10V_R7_REGNUM: 1413 case SIM_D10V_R8_REGNUM: 1414 case SIM_D10V_R9_REGNUM: 1415 case SIM_D10V_R10_REGNUM: 1416 case SIM_D10V_R11_REGNUM: 1417 case SIM_D10V_R12_REGNUM: 1418 case SIM_D10V_R13_REGNUM: 1419 case SIM_D10V_R14_REGNUM: 1420 case SIM_D10V_R15_REGNUM: 1421 SET_GPR (rn - SIM_D10V_R0_REGNUM, READ_16 (memory)); 1422 size = 2; 1423 break; 1424 case SIM_D10V_CR0_REGNUM: 1425 case SIM_D10V_CR1_REGNUM: 1426 case SIM_D10V_CR2_REGNUM: 1427 case SIM_D10V_CR3_REGNUM: 1428 case SIM_D10V_CR4_REGNUM: 1429 case SIM_D10V_CR5_REGNUM: 1430 case SIM_D10V_CR6_REGNUM: 1431 case SIM_D10V_CR7_REGNUM: 1432 case SIM_D10V_CR8_REGNUM: 1433 case SIM_D10V_CR9_REGNUM: 1434 case SIM_D10V_CR10_REGNUM: 1435 case SIM_D10V_CR11_REGNUM: 1436 case SIM_D10V_CR12_REGNUM: 1437 case SIM_D10V_CR13_REGNUM: 1438 case SIM_D10V_CR14_REGNUM: 1439 case SIM_D10V_CR15_REGNUM: 1440 SET_CREG (rn - SIM_D10V_CR0_REGNUM, READ_16 (memory)); 1441 size = 2; 1442 break; 1443 case SIM_D10V_A0_REGNUM: 1444 case SIM_D10V_A1_REGNUM: 1445 SET_ACC (rn - SIM_D10V_A0_REGNUM, READ_64 (memory) & MASK40); 1446 size = 8; 1447 break; 1448 case SIM_D10V_SPI_REGNUM: 1449 /* PSW_SM indicates that the current SP is the USER 1450 stack-pointer. */ 1451 set_spi_register (READ_16 (memory)); 1452 size = 2; 1453 break; 1454 case SIM_D10V_SPU_REGNUM: 1455 set_spu_register (READ_16 (memory)); 1456 size = 2; 1457 break; 1458 case SIM_D10V_IMAP0_REGNUM: 1459 case SIM_D10V_IMAP1_REGNUM: 1460 set_imap_register (rn - SIM_D10V_IMAP0_REGNUM, READ_16(memory)); 1461 size = 2; 1462 break; 1463 case SIM_D10V_DMAP0_REGNUM: 1464 case SIM_D10V_DMAP1_REGNUM: 1465 case SIM_D10V_DMAP2_REGNUM: 1466 case SIM_D10V_DMAP3_REGNUM: 1467 set_dmap_register (rn - SIM_D10V_DMAP0_REGNUM, READ_16(memory)); 1468 size = 2; 1469 break; 1470 case SIM_D10V_TS2_DMAP_REGNUM: 1471 size = 0; 1472 break; 1473 default: 1474 size = 0; 1475 break; 1476 } 1477 SLOT_FLUSH (); 1478 return size; 1479 } 1480 1481 1482 void 1483 sim_do_command (sd, cmd) 1484 SIM_DESC sd; 1485 char *cmd; 1486 { 1487 (*d10v_callback->printf_filtered) (d10v_callback, "sim_do_command: %s\n",cmd); 1488 } 1489 1490 SIM_RC 1491 sim_load (sd, prog, abfd, from_tty) 1492 SIM_DESC sd; 1493 char *prog; 1494 bfd *abfd; 1495 int from_tty; 1496 { 1497 extern bfd *sim_load_file (); /* ??? Don't know where this should live. */ 1498 1499 if (prog_bfd != NULL && prog_bfd_was_opened_p) 1500 { 1501 bfd_close (prog_bfd); 1502 prog_bfd_was_opened_p = 0; 1503 } 1504 prog_bfd = sim_load_file (sd, myname, d10v_callback, prog, abfd, 1505 sim_kind == SIM_OPEN_DEBUG, 1506 1/*LMA*/, sim_write); 1507 if (prog_bfd == NULL) 1508 return SIM_RC_FAIL; 1509 prog_bfd_was_opened_p = abfd == NULL; 1510 return SIM_RC_OK; 1511 } 1512