1 /* Tracing support for CGEN-based simulators. 2 Copyright (C) 1996-2015 Free Software Foundation, Inc. 3 Contributed by Cygnus Support. 4 5 This file is part of GDB, the GNU debugger. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #include "config.h" 21 #include <errno.h> 22 #include "dis-asm.h" 23 #include "bfd.h" 24 #include "sim-main.h" 25 #include "sim-fpu.h" 26 27 #undef min 28 #define min(a,b) ((a) < (b) ? (a) : (b)) 29 30 #ifndef SIZE_INSTRUCTION 31 #define SIZE_INSTRUCTION 16 32 #endif 33 34 #ifndef SIZE_LOCATION 35 #define SIZE_LOCATION 20 36 #endif 37 38 #ifndef SIZE_PC 39 #define SIZE_PC 6 40 #endif 41 42 #ifndef SIZE_LINE_NUMBER 43 #define SIZE_LINE_NUMBER 4 44 #endif 45 46 #ifndef SIZE_CYCLE_COUNT 47 #define SIZE_CYCLE_COUNT 2 48 #endif 49 50 #ifndef SIZE_TOTAL_CYCLE_COUNT 51 #define SIZE_TOTAL_CYCLE_COUNT 9 52 #endif 53 54 #ifndef SIZE_TRACE_BUF 55 #define SIZE_TRACE_BUF 1024 56 #endif 57 58 /* Text is queued in TRACE_BUF because we want to output the insn's cycle 59 count first but that isn't known until after the insn has executed. 60 This also handles the queueing of trace results, TRACE_RESULT may be 61 called multiple times for one insn. */ 62 static char trace_buf[SIZE_TRACE_BUF]; 63 /* If NULL, output to stdout directly. */ 64 static char *bufptr; 65 66 /* Non-zero if this is the first insn in a set of parallel insns. */ 67 static int first_insn_p; 68 69 /* For communication between cgen_trace_insn and cgen_trace_result. */ 70 static int printed_result_p; 71 72 /* Insn and its extracted fields. 73 Set by cgen_trace_insn, used by cgen_trace_insn_fini. 74 ??? Move to SIM_CPU to support heterogeneous multi-cpu case. */ 75 static const struct cgen_insn *current_insn; 76 static const struct argbuf *current_abuf; 77 78 void 79 cgen_trace_insn_init (SIM_CPU *cpu, int first_p) 80 { 81 bufptr = trace_buf; 82 *bufptr = 0; 83 first_insn_p = first_p; 84 85 /* Set to NULL so cgen_trace_insn_fini can know if cgen_trace_insn was 86 called. */ 87 current_insn = NULL; 88 current_abuf = NULL; 89 } 90 91 void 92 cgen_trace_insn_fini (SIM_CPU *cpu, const struct argbuf *abuf, int last_p) 93 { 94 SIM_DESC sd = CPU_STATE (cpu); 95 96 /* Was insn traced? It might not be if trace ranges are in effect. */ 97 if (current_insn == NULL) 98 return; 99 100 /* The first thing printed is current and total cycle counts. */ 101 102 if (PROFILE_MODEL_P (cpu) 103 && ARGBUF_PROFILE_P (current_abuf)) 104 { 105 unsigned long total = PROFILE_MODEL_TOTAL_CYCLES (CPU_PROFILE_DATA (cpu)); 106 unsigned long this_insn = PROFILE_MODEL_CUR_INSN_CYCLES (CPU_PROFILE_DATA (cpu)); 107 108 if (last_p) 109 { 110 trace_printf (sd, cpu, "%-*ld %-*ld ", 111 SIZE_CYCLE_COUNT, this_insn, 112 SIZE_TOTAL_CYCLE_COUNT, total); 113 } 114 else 115 { 116 trace_printf (sd, cpu, "%-*ld %-*s ", 117 SIZE_CYCLE_COUNT, this_insn, 118 SIZE_TOTAL_CYCLE_COUNT, "---"); 119 } 120 } 121 122 /* Print the disassembled insn. */ 123 124 trace_printf (sd, cpu, "%s", TRACE_PREFIX (CPU_TRACE_DATA (cpu))); 125 126 #if 0 127 /* Print insn results. */ 128 { 129 const CGEN_OPINST *opinst = CGEN_INSN_OPERANDS (current_insn); 130 131 if (opinst) 132 { 133 int i; 134 int indices[MAX_OPERAND_INSTANCES]; 135 136 /* Fetch the operands used by the insn. */ 137 /* FIXME: Add fn ptr to CGEN_CPU_DESC. */ 138 CGEN_SYM (get_insn_operands) (CPU_CPU_DESC (cpu), current_insn, 139 0, CGEN_FIELDS_BITSIZE (&insn_fields), 140 indices); 141 142 for (i = 0; 143 CGEN_OPINST_TYPE (opinst) != CGEN_OPINST_END; 144 ++i, ++opinst) 145 { 146 if (CGEN_OPINST_TYPE (opinst) == CGEN_OPINST_OUTPUT) 147 cgen_trace_result (cpu, current_insn, opinst, indices[i]); 148 } 149 } 150 } 151 #endif 152 153 /* Print anything else requested. */ 154 155 if (*trace_buf) 156 trace_printf (sd, cpu, " %s\n", trace_buf); 157 else 158 trace_printf (sd, cpu, "\n"); 159 } 160 161 void 162 cgen_trace_insn (SIM_CPU *cpu, const struct cgen_insn *opcode, 163 const struct argbuf *abuf, IADDR pc) 164 { 165 char disasm_buf[50]; 166 167 printed_result_p = 0; 168 current_insn = opcode; 169 current_abuf = abuf; 170 171 if (CGEN_INSN_VIRTUAL_P (opcode)) 172 { 173 trace_prefix (CPU_STATE (cpu), cpu, NULL_CIA, pc, 0, 174 NULL, 0, CGEN_INSN_NAME (opcode)); 175 return; 176 } 177 178 CPU_DISASSEMBLER (cpu) (cpu, opcode, abuf, pc, disasm_buf); 179 trace_prefix (CPU_STATE (cpu), cpu, NULL_CIA, pc, TRACE_LINENUM_P (cpu), 180 NULL, 0, 181 "%s%-*s", 182 first_insn_p ? " " : "|", 183 SIZE_INSTRUCTION, disasm_buf); 184 } 185 186 void 187 cgen_trace_extract (SIM_CPU *cpu, IADDR pc, char *name, ...) 188 { 189 va_list args; 190 int printed_one_p = 0; 191 char *fmt; 192 193 va_start (args, name); 194 195 trace_printf (CPU_STATE (cpu), cpu, "Extract: 0x%.*lx: %s ", 196 SIZE_PC, (unsigned long) pc, name); 197 198 do { 199 int type,ival; 200 201 fmt = va_arg (args, char *); 202 203 if (fmt) 204 { 205 if (printed_one_p) 206 trace_printf (CPU_STATE (cpu), cpu, ", "); 207 printed_one_p = 1; 208 type = va_arg (args, int); 209 switch (type) 210 { 211 case 'x' : 212 ival = va_arg (args, int); 213 trace_printf (CPU_STATE (cpu), cpu, fmt, ival); 214 break; 215 default : 216 abort (); 217 } 218 } 219 } while (fmt); 220 221 va_end (args); 222 trace_printf (CPU_STATE (cpu), cpu, "\n"); 223 } 224 225 void 226 cgen_trace_result (SIM_CPU *cpu, char *name, int type, ...) 227 { 228 va_list args; 229 230 va_start (args, type); 231 if (printed_result_p) 232 cgen_trace_printf (cpu, ", "); 233 234 switch (type) 235 { 236 case 'x' : 237 default : 238 cgen_trace_printf (cpu, "%s <- 0x%x", name, va_arg (args, int)); 239 break; 240 case 'f': 241 { 242 DI di; 243 sim_fpu f; 244 245 /* this is separated from previous line for sunos cc */ 246 di = va_arg (args, DI); 247 sim_fpu_64to (&f, di); 248 249 cgen_trace_printf (cpu, "%s <- ", name); 250 sim_fpu_printn_fpu (&f, (sim_fpu_print_func *) cgen_trace_printf, 4, cpu); 251 break; 252 } 253 case 'D' : 254 { 255 DI di; 256 /* this is separated from previous line for sunos cc */ 257 di = va_arg (args, DI); 258 cgen_trace_printf (cpu, "%s <- 0x%x%08x", name, 259 GETHIDI(di), GETLODI (di)); 260 break; 261 } 262 } 263 264 printed_result_p = 1; 265 va_end (args); 266 } 267 268 /* Print trace output to BUFPTR if active, otherwise print normally. 269 This is only for tracing semantic code. */ 270 271 void 272 cgen_trace_printf (SIM_CPU *cpu, char *fmt, ...) 273 { 274 va_list args; 275 276 va_start (args, fmt); 277 278 if (bufptr == NULL) 279 { 280 if (TRACE_FILE (CPU_TRACE_DATA (cpu)) == NULL) 281 (* STATE_CALLBACK (CPU_STATE (cpu))->evprintf_filtered) 282 (STATE_CALLBACK (CPU_STATE (cpu)), fmt, args); 283 else 284 vfprintf (TRACE_FILE (CPU_TRACE_DATA (cpu)), fmt, args); 285 } 286 else 287 { 288 vsprintf (bufptr, fmt, args); 289 bufptr += strlen (bufptr); 290 /* ??? Need version of SIM_ASSERT that is always enabled. */ 291 if (bufptr - trace_buf > SIZE_TRACE_BUF) 292 abort (); 293 } 294 295 va_end (args); 296 } 297 298 /* Disassembly support. */ 299 300 /* sprintf to a "stream" */ 301 302 int 303 sim_disasm_sprintf (SFILE *f, const char *format, ...) 304 { 305 int n; 306 va_list args; 307 308 va_start (args, format); 309 vsprintf (f->current, format, args); 310 f->current += n = strlen (f->current); 311 va_end (args); 312 return n; 313 } 314 315 /* Memory read support for an opcodes disassembler. */ 316 317 int 318 sim_disasm_read_memory (bfd_vma memaddr, bfd_byte *myaddr, unsigned int length, 319 struct disassemble_info *info) 320 { 321 SIM_CPU *cpu = (SIM_CPU *) info->application_data; 322 SIM_DESC sd = CPU_STATE (cpu); 323 unsigned length_read; 324 325 length_read = sim_core_read_buffer (sd, cpu, read_map, myaddr, memaddr, 326 length); 327 if (length_read != length) 328 return EIO; 329 return 0; 330 } 331 332 /* Memory error support for an opcodes disassembler. */ 333 334 void 335 sim_disasm_perror_memory (int status, bfd_vma memaddr, 336 struct disassemble_info *info) 337 { 338 if (status != EIO) 339 /* Can't happen. */ 340 info->fprintf_func (info->stream, "Unknown error %d.", status); 341 else 342 /* Actually, address between memaddr and memaddr + len was 343 out of bounds. */ 344 info->fprintf_func (info->stream, 345 "Address 0x%x is out of bounds.", 346 (int) memaddr); 347 } 348 349 /* Disassemble using the CGEN opcode table. 350 ??? While executing an instruction, the insn has been decoded and all its 351 fields have been extracted. It is certainly possible to do the disassembly 352 with that data. This seems simpler, but maybe in the future the already 353 extracted fields will be used. */ 354 355 void 356 sim_cgen_disassemble_insn (SIM_CPU *cpu, const CGEN_INSN *insn, 357 const ARGBUF *abuf, IADDR pc, char *buf) 358 { 359 unsigned int length; 360 unsigned int base_length; 361 unsigned long insn_value; 362 struct disassemble_info disasm_info; 363 SFILE sfile; 364 union { 365 unsigned8 bytes[CGEN_MAX_INSN_SIZE]; 366 unsigned16 shorts[8]; 367 unsigned32 words[4]; 368 } insn_buf; 369 SIM_DESC sd = CPU_STATE (cpu); 370 CGEN_CPU_DESC cd = CPU_CPU_DESC (cpu); 371 CGEN_EXTRACT_INFO ex_info; 372 CGEN_FIELDS *fields = alloca (CGEN_CPU_SIZEOF_FIELDS (cd)); 373 int insn_bit_length = CGEN_INSN_BITSIZE (insn); 374 int insn_length = insn_bit_length / 8; 375 376 sfile.buffer = sfile.current = buf; 377 INIT_DISASSEMBLE_INFO (disasm_info, (FILE *) &sfile, 378 (fprintf_ftype) sim_disasm_sprintf); 379 disasm_info.endian = 380 (bfd_big_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_BIG 381 : bfd_little_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_LITTLE 382 : BFD_ENDIAN_UNKNOWN); 383 384 length = sim_core_read_buffer (sd, cpu, read_map, &insn_buf, pc, 385 insn_length); 386 387 if (length != insn_length) 388 { 389 sim_io_error (sd, "unable to read address %x", pc); 390 } 391 392 /* If the entire insn will fit into an integer, then do it. Otherwise, just 393 use the bits of the base_insn. */ 394 if (insn_bit_length <= 32) 395 base_length = insn_bit_length; 396 else 397 base_length = min (cd->base_insn_bitsize, insn_bit_length); 398 switch (base_length) 399 { 400 case 0 : return; /* fake insn, typically "compile" (aka "invalid") */ 401 case 8 : insn_value = insn_buf.bytes[0]; break; 402 case 16 : insn_value = T2H_2 (insn_buf.shorts[0]); break; 403 case 32 : insn_value = T2H_4 (insn_buf.words[0]); break; 404 default: abort (); 405 } 406 407 disasm_info.buffer_vma = pc; 408 disasm_info.buffer = insn_buf.bytes; 409 disasm_info.buffer_length = length; 410 411 ex_info.dis_info = (PTR) &disasm_info; 412 ex_info.valid = (1 << length) - 1; 413 ex_info.insn_bytes = insn_buf.bytes; 414 415 length = (*CGEN_EXTRACT_FN (cd, insn)) (cd, insn, &ex_info, insn_value, fields, pc); 416 /* Result of extract fn is in bits. */ 417 /* ??? This assumes that each instruction has a fixed length (and thus 418 for insns with multiple versions of variable lengths they would each 419 have their own table entry). */ 420 if (length == insn_bit_length) 421 { 422 (*CGEN_PRINT_FN (cd, insn)) (cd, &disasm_info, insn, fields, pc, length); 423 } 424 else 425 { 426 /* This shouldn't happen, but aborting is too drastic. */ 427 strcpy (buf, "***unknown***"); 428 } 429 } 430