1 /* Simulator for Analog Devices Blackfin processors. 2 3 Copyright (C) 2005-2014 Free Software Foundation, Inc. 4 Contributed by Analog Devices, Inc. 5 6 This file is part of simulators. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21 #ifndef _BFIN_MACHS_H_ 22 #define _BFIN_MACHS_H_ 23 24 typedef enum model_type { 25 #define P(n) MODEL_BF##n, 26 #include "proc_list.def" 27 #undef P 28 MODEL_MAX 29 } MODEL_TYPE; 30 31 typedef enum mach_attr { 32 MACH_BASE, 33 MACH_BFIN, 34 MACH_MAX 35 } MACH_ATTR; 36 37 #define CPU_MODEL_NUM(cpu) MODEL_NUM (CPU_MODEL (cpu)) 38 39 /* XXX: Some of this probably belongs in CPU_MODEL. */ 40 struct bfin_board_data { 41 unsigned int sirev, sirev_valid; 42 const char *hw_file; 43 }; 44 45 void bfin_model_cpu_init (SIM_DESC, SIM_CPU *); 46 bu32 bfin_model_get_chipid (SIM_DESC); 47 bu32 bfin_model_get_dspid (SIM_DESC); 48 49 enum { 50 #define I(insn) BFIN_INSN_##insn, 51 #include "insn_list.def" 52 #undef I 53 BFIN_INSN_MAX 54 }; 55 56 #define BFIN_COREMMR_CEC_BASE 0xFFE02100 57 #define BFIN_COREMMR_CEC_SIZE (4 * 5) 58 #define BFIN_COREMMR_CTIMER_BASE 0xFFE03000 59 #define BFIN_COREMMR_CTIMER_SIZE (4 * 4) 60 #define BFIN_COREMMR_EVT_BASE 0xFFE02000 61 #define BFIN_COREMMR_EVT_SIZE (4 * 16) 62 #define BFIN_COREMMR_JTAG_BASE 0xFFE05000 63 #define BFIN_COREMMR_JTAG_SIZE (4 * 3) 64 #define BFIN_COREMMR_MMU_BASE 0xFFE00000 65 #define BFIN_COREMMR_MMU_SIZE 0x2000 66 #define BFIN_COREMMR_PFMON_BASE 0xFFE08000 67 #define BFIN_COREMMR_PFMON_SIZE 0x108 68 #define BFIN_COREMMR_TRACE_BASE 0xFFE06000 69 #define BFIN_COREMMR_TRACE_SIZE (4 * 65) 70 #define BFIN_COREMMR_WP_BASE 0xFFE07000 71 #define BFIN_COREMMR_WP_SIZE 0x204 72 73 #define BFIN_MMR_DMA_SIZE (4 * 16) 74 #define BFIN_MMR_DMAC0_BASE 0xFFC00C00 75 #define BFIN_MMR_DMAC1_BASE 0xFFC01C00 76 #define BFIN_MMR_EBIU_AMC_SIZE (4 * 3) 77 #define BF50X_MMR_EBIU_AMC_SIZE 0x28 78 #define BF54X_MMR_EBIU_AMC_SIZE (4 * 7) 79 #define BFIN_MMR_EBIU_DDRC_SIZE 0xb0 80 #define BFIN_MMR_EBIU_SDC_SIZE (4 * 4) 81 #define BFIN_MMR_EMAC_BASE 0xFFC03000 82 #define BFIN_MMR_EMAC_SIZE 0x200 83 #define BFIN_MMR_EPPI_SIZE 0x40 84 #define BFIN_MMR_GPIO_SIZE (17 * 4) 85 #define BFIN_MMR_GPIO2_SIZE (8 * 4) 86 #define BFIN_MMR_GPTIMER_SIZE (4 * 4) 87 #define BFIN_MMR_NFC_SIZE 0x50 88 /* XXX: Not exactly true; it's two sets of 4 regs near each other: 89 0xFFC03600 0x10 - Control 90 0xFFC03680 0x10 - Data */ 91 #define BFIN_MMR_OTP_SIZE 0xa0 92 #define BFIN_MMR_PINT_SIZE 0x28 93 #define BFIN_MMR_PLL_BASE 0xFFC00000 94 #define BFIN_MMR_PLL_SIZE (4 * 6) 95 #define BFIN_MMR_PPI_SIZE (4 * 5) 96 #define BFIN_MMR_RTC_SIZE (4 * 6) 97 #define BFIN_MMR_SIC_BASE 0xFFC00100 98 #define BFIN_MMR_SIC_SIZE 0x100 99 #define BFIN_MMR_SPI_SIZE (4 * 7) 100 #define BFIN_MMR_TWI_SIZE 0x90 101 #define BFIN_MMR_WDOG_SIZE (4 * 3) 102 #define BFIN_MMR_UART_SIZE 0x30 103 #define BFIN_MMR_UART2_SIZE 0x30 104 105 #endif 106