1 /* Blackfin device support. 2 3 Copyright (C) 2010-2017 Free Software Foundation, Inc. 4 Contributed by Analog Devices, Inc. 5 6 This file is part of simulators. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21 #include "config.h" 22 23 #include "sim-main.h" 24 #include "sim-hw.h" 25 #include "hw-device.h" 26 #include "devices.h" 27 #include "dv-bfin_cec.h" 28 #include "dv-bfin_mmu.h" 29 30 static void 31 bfin_mmr_invalid (struct hw *me, address_word addr, 32 unsigned nr_bytes, bool write, bool missing) 33 { 34 SIM_CPU *cpu = hw_system_cpu (me); 35 const char *rw = write ? "write" : "read"; 36 const char *reason = 37 missing ? "no such register" : 38 (addr & 3) ? "must be 32-bit aligned" : "invalid length"; 39 40 /* Only throw a fit if the cpu is doing the access. DMA/GDB simply 41 go unnoticed. Not exactly hardware behavior, but close enough. */ 42 if (!cpu) 43 { 44 sim_io_eprintf (hw_system (me), 45 "%s: invalid MMR %s at %#x length %u: %s\n", 46 hw_path (me), rw, addr, nr_bytes, reason); 47 return; 48 } 49 50 HW_TRACE ((me, "invalid MMR %s at %#x length %u: %s", 51 rw, addr, nr_bytes, reason)); 52 53 /* XXX: is this what hardware does ? What about priority of unaligned vs 54 wrong length vs missing register ? What about system-vs-core ? */ 55 /* XXX: We should move this addr check to a model property so we get the 56 same behavior regardless of where we map the model. */ 57 if (addr >= BFIN_CORE_MMR_BASE) 58 /* XXX: This should be setting up CPLB fault addrs ? */ 59 mmu_process_fault (cpu, addr, write, false, false, true); 60 else 61 /* XXX: Newer parts set up an interrupt from EBIU and program 62 EBIU_ERRADDR with the address. */ 63 cec_hwerr (cpu, HWERR_SYSTEM_MMR); 64 } 65 66 void 67 dv_bfin_mmr_invalid (struct hw *me, address_word addr, unsigned nr_bytes, 68 bool write) 69 { 70 bfin_mmr_invalid (me, addr, nr_bytes, write, true); 71 } 72 73 bool 74 dv_bfin_mmr_require (struct hw *me, address_word addr, unsigned nr_bytes, 75 unsigned size, bool write) 76 { 77 if ((addr & 0x3) == 0 && nr_bytes == size) 78 return true; 79 80 bfin_mmr_invalid (me, addr, nr_bytes, write, false); 81 return false; 82 } 83 84 /* For 32-bit memory mapped registers that allow 16-bit or 32-bit access. */ 85 bool 86 dv_bfin_mmr_require_16_32 (struct hw *me, address_word addr, unsigned nr_bytes, 87 bool write) 88 { 89 if ((addr & 0x3) == 0 && (nr_bytes == 2 || nr_bytes == 4)) 90 return true; 91 92 bfin_mmr_invalid (me, addr, nr_bytes, write, false); 93 return false; 94 } 95 96 unsigned int dv_get_bus_num (struct hw *me) 97 { 98 const hw_unit *unit = hw_unit_address (me); 99 return unit->cells[unit->nr_cells - 1]; 100 } 101