1 /* Simulator for Atmel's AVR core. 2 Copyright (C) 2009-2023 Free Software Foundation, Inc. 3 Written by Tristan Gingold, AdaCore. 4 5 This file is part of GDB, the GNU debugger. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 /* This must come before any other includes. */ 21 #include "defs.h" 22 23 #include <string.h> 24 25 #include "bfd.h" 26 #include "libiberty.h" 27 #include "sim/sim.h" 28 29 #include "sim-main.h" 30 #include "sim-base.h" 31 #include "sim-options.h" 32 #include "sim-signal.h" 33 34 /* As AVR is a 8/16 bits processor, define handy types. */ 35 typedef unsigned short int word; 36 typedef signed short int sword; 37 typedef unsigned char byte; 38 typedef signed char sbyte; 39 40 /* Max size of I space (which is always flash on avr). */ 41 #define MAX_AVR_FLASH (128 * 1024) 42 #define PC_MASK (MAX_AVR_FLASH - 1) 43 44 /* Mac size of D space. */ 45 #define MAX_AVR_SRAM (64 * 1024) 46 #define SRAM_MASK (MAX_AVR_SRAM - 1) 47 48 /* D space offset in ELF file. */ 49 #define SRAM_VADDR 0x800000 50 51 /* Simulator specific ports. */ 52 #define STDIO_PORT 0x52 53 #define EXIT_PORT 0x4F 54 #define ABORT_PORT 0x49 55 56 /* GDB defined register numbers. */ 57 #define AVR_SREG_REGNUM 32 58 #define AVR_SP_REGNUM 33 59 #define AVR_PC_REGNUM 34 60 61 /* Memory mapped registers. */ 62 #define SREG 0x5F 63 #define REG_SP 0x5D 64 #define EIND 0x5C 65 #define RAMPZ 0x5B 66 67 #define REGX 0x1a 68 #define REGY 0x1c 69 #define REGZ 0x1e 70 #define REGZ_LO 0x1e 71 #define REGZ_HI 0x1f 72 73 /* Sreg (status) bits. */ 74 #define SREG_I 0x80 75 #define SREG_T 0x40 76 #define SREG_H 0x20 77 #define SREG_S 0x10 78 #define SREG_V 0x08 79 #define SREG_N 0x04 80 #define SREG_Z 0x02 81 #define SREG_C 0x01 82 83 /* In order to speed up emulation we use a simple approach: 84 a code is associated with each instruction. The pre-decoding occurs 85 usually once when the instruction is first seen. 86 This works well because I&D spaces are separated. 87 88 Missing opcodes: sleep, spm, wdr (as they are mmcu dependent). 89 */ 90 enum avr_opcode 91 { 92 /* Opcode not yet decoded. */ 93 OP_unknown, 94 OP_bad, 95 96 OP_nop, 97 98 OP_rjmp, 99 OP_rcall, 100 OP_ret, 101 OP_reti, 102 103 OP_break, 104 105 OP_brbs, 106 OP_brbc, 107 108 OP_bset, 109 OP_bclr, 110 111 OP_bld, 112 OP_bst, 113 114 OP_sbrc, 115 OP_sbrs, 116 117 OP_eor, 118 OP_and, 119 OP_andi, 120 OP_or, 121 OP_ori, 122 OP_com, 123 OP_swap, 124 OP_neg, 125 126 OP_out, 127 OP_in, 128 OP_cbi, 129 OP_sbi, 130 131 OP_sbic, 132 OP_sbis, 133 134 OP_ldi, 135 OP_cpse, 136 OP_cp, 137 OP_cpi, 138 OP_cpc, 139 OP_sub, 140 OP_sbc, 141 OP_sbiw, 142 OP_adiw, 143 OP_add, 144 OP_adc, 145 OP_subi, 146 OP_sbci, 147 OP_inc, 148 OP_dec, 149 OP_lsr, 150 OP_ror, 151 OP_asr, 152 153 OP_mul, 154 OP_muls, 155 OP_mulsu, 156 OP_fmul, 157 OP_fmuls, 158 OP_fmulsu, 159 160 OP_mov, 161 OP_movw, 162 163 OP_push, 164 OP_pop, 165 166 OP_st_X, 167 OP_st_dec_X, 168 OP_st_X_inc, 169 OP_st_Y_inc, 170 OP_st_dec_Y, 171 OP_st_Z_inc, 172 OP_st_dec_Z, 173 OP_std_Y, 174 OP_std_Z, 175 OP_ldd_Y, 176 OP_ldd_Z, 177 OP_ld_Z_inc, 178 OP_ld_dec_Z, 179 OP_ld_Y_inc, 180 OP_ld_dec_Y, 181 OP_ld_X, 182 OP_ld_X_inc, 183 OP_ld_dec_X, 184 185 OP_lpm, 186 OP_lpm_Z, 187 OP_lpm_inc_Z, 188 OP_elpm, 189 OP_elpm_Z, 190 OP_elpm_inc_Z, 191 192 OP_ijmp, 193 OP_icall, 194 195 OP_eijmp, 196 OP_eicall, 197 198 /* 2 words opcodes. */ 199 #define OP_2words OP_jmp 200 OP_jmp, 201 OP_call, 202 OP_sts, 203 OP_lds 204 }; 205 206 struct avr_insn_cell 207 { 208 /* The insn (16 bits). */ 209 word op; 210 211 /* Pre-decoding code. */ 212 enum avr_opcode code : 8; 213 /* One byte of additional information. */ 214 byte r; 215 }; 216 217 /* I&D memories. */ 218 /* TODO: Should be moved to SIM_CPU. */ 219 static struct avr_insn_cell flash[MAX_AVR_FLASH]; 220 static byte sram[MAX_AVR_SRAM]; 221 222 /* Sign extend a value. */ 223 static int sign_ext (word val, int nb_bits) 224 { 225 if (val & (1 << (nb_bits - 1))) 226 return val | -(1 << nb_bits); 227 return val; 228 } 229 230 /* Insn field extractors. */ 231 232 /* Extract xxxx_xxxRx_xxxx_RRRR. */ 233 static inline byte get_r (word op) 234 { 235 return (op & 0xf) | ((op >> 5) & 0x10); 236 } 237 238 /* Extract xxxx_xxxxx_xxxx_RRRR. */ 239 static inline byte get_r16 (word op) 240 { 241 return 16 + (op & 0xf); 242 } 243 244 /* Extract xxxx_xxxxx_xxxx_xRRR. */ 245 static inline byte get_r16_23 (word op) 246 { 247 return 16 + (op & 0x7); 248 } 249 250 /* Extract xxxx_xxxD_DDDD_xxxx. */ 251 static inline byte get_d (word op) 252 { 253 return (op >> 4) & 0x1f; 254 } 255 256 /* Extract xxxx_xxxx_DDDD_xxxx. */ 257 static inline byte get_d16 (word op) 258 { 259 return 16 + ((op >> 4) & 0x0f); 260 } 261 262 /* Extract xxxx_xxxx_xDDD_xxxx. */ 263 static inline byte get_d16_23 (word op) 264 { 265 return 16 + ((op >> 4) & 0x07); 266 } 267 268 /* Extract xxxx_xAAx_xxxx_AAAA. */ 269 static inline byte get_A (word op) 270 { 271 return (op & 0x0f) | ((op & 0x600) >> 5); 272 } 273 274 /* Extract xxxx_xxxx_AAAA_Axxx. */ 275 static inline byte get_biA (word op) 276 { 277 return (op >> 3) & 0x1f; 278 } 279 280 /* Extract xxxx_KKKK_xxxx_KKKK. */ 281 static inline byte get_K (word op) 282 { 283 return (op & 0xf) | ((op & 0xf00) >> 4); 284 } 285 286 /* Extract xxxx_xxKK_KKKK_Kxxx. */ 287 static inline int get_k (word op) 288 { 289 return sign_ext ((op & 0x3f8) >> 3, 7); 290 } 291 292 /* Extract xxxx_xxxx_xxDD_xxxx. */ 293 static inline byte get_d24 (word op) 294 { 295 return 24 + ((op >> 3) & 6); 296 } 297 298 /* Extract xxxx_xxxx_KKxx_KKKK. */ 299 static inline byte get_k6 (word op) 300 { 301 return (op & 0xf) | ((op >> 2) & 0x30); 302 } 303 304 /* Extract xxQx_QQxx_xxxx_xQQQ. */ 305 static inline byte get_q (word op) 306 { 307 return (op & 7) | ((op >> 7) & 0x18)| ((op >> 8) & 0x20); 308 } 309 310 /* Extract xxxx_xxxx_xxxx_xBBB. */ 311 static inline byte get_b (word op) 312 { 313 return (op & 7); 314 } 315 316 /* AVR is little endian. */ 317 static inline word 318 read_word (unsigned int addr) 319 { 320 return sram[addr] | (sram[addr + 1] << 8); 321 } 322 323 static inline void 324 write_word (unsigned int addr, word w) 325 { 326 sram[addr] = w; 327 sram[addr + 1] = w >> 8; 328 } 329 330 static inline word 331 read_word_post_inc (unsigned int addr) 332 { 333 word v = read_word (addr); 334 write_word (addr, v + 1); 335 return v; 336 } 337 338 static inline word 339 read_word_pre_dec (unsigned int addr) 340 { 341 word v = read_word (addr) - 1; 342 write_word (addr, v); 343 return v; 344 } 345 346 static void 347 update_flags_logic (byte res) 348 { 349 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z); 350 if (res == 0) 351 sram[SREG] |= SREG_Z; 352 if (res & 0x80) 353 sram[SREG] |= SREG_N | SREG_S; 354 } 355 356 static void 357 update_flags_add (byte r, byte a, byte b) 358 { 359 byte carry; 360 361 sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C); 362 if (r & 0x80) 363 sram[SREG] |= SREG_N; 364 carry = (a & b) | (a & ~r) | (b & ~r); 365 if (carry & 0x08) 366 sram[SREG] |= SREG_H; 367 if (carry & 0x80) 368 sram[SREG] |= SREG_C; 369 if (((a & b & ~r) | (~a & ~b & r)) & 0x80) 370 sram[SREG] |= SREG_V; 371 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_V)) 372 sram[SREG] |= SREG_S; 373 if (r == 0) 374 sram[SREG] |= SREG_Z; 375 } 376 377 static void update_flags_sub (byte r, byte a, byte b) 378 { 379 byte carry; 380 381 sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C); 382 if (r & 0x80) 383 sram[SREG] |= SREG_N; 384 carry = (~a & b) | (b & r) | (r & ~a); 385 if (carry & 0x08) 386 sram[SREG] |= SREG_H; 387 if (carry & 0x80) 388 sram[SREG] |= SREG_C; 389 if (((a & ~b & ~r) | (~a & b & r)) & 0x80) 390 sram[SREG] |= SREG_V; 391 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_V)) 392 sram[SREG] |= SREG_S; 393 /* Note: Z is not set. */ 394 } 395 396 static enum avr_opcode 397 decode (unsigned int pc) 398 { 399 word op1 = flash[pc].op; 400 401 switch ((op1 >> 12) & 0x0f) 402 { 403 case 0x0: 404 switch ((op1 >> 10) & 0x3) 405 { 406 case 0x0: 407 switch ((op1 >> 8) & 0x3) 408 { 409 case 0x0: 410 if (op1 == 0) 411 return OP_nop; 412 break; 413 case 0x1: 414 return OP_movw; 415 case 0x2: 416 return OP_muls; 417 case 0x3: 418 if (op1 & 0x80) 419 { 420 if (op1 & 0x08) 421 return OP_fmulsu; 422 else 423 return OP_fmuls; 424 } 425 else 426 { 427 if (op1 & 0x08) 428 return OP_fmul; 429 else 430 return OP_mulsu; 431 } 432 } 433 break; 434 case 0x1: 435 return OP_cpc; 436 case 0x2: 437 flash[pc].r = SREG_C; 438 return OP_sbc; 439 case 0x3: 440 flash[pc].r = 0; 441 return OP_add; 442 } 443 break; 444 case 0x1: 445 switch ((op1 >> 10) & 0x3) 446 { 447 case 0x0: 448 return OP_cpse; 449 case 0x1: 450 return OP_cp; 451 case 0x2: 452 flash[pc].r = 0; 453 return OP_sub; 454 case 0x3: 455 flash[pc].r = SREG_C; 456 return OP_adc; 457 } 458 break; 459 case 0x2: 460 switch ((op1 >> 10) & 0x3) 461 { 462 case 0x0: 463 return OP_and; 464 case 0x1: 465 return OP_eor; 466 case 0x2: 467 return OP_or; 468 case 0x3: 469 return OP_mov; 470 } 471 break; 472 case 0x3: 473 return OP_cpi; 474 case 0x4: 475 return OP_sbci; 476 case 0x5: 477 return OP_subi; 478 case 0x6: 479 return OP_ori; 480 case 0x7: 481 return OP_andi; 482 case 0x8: 483 case 0xa: 484 if (op1 & 0x0200) 485 { 486 if (op1 & 0x0008) 487 { 488 flash[pc].r = get_q (op1); 489 return OP_std_Y; 490 } 491 else 492 { 493 flash[pc].r = get_q (op1); 494 return OP_std_Z; 495 } 496 } 497 else 498 { 499 if (op1 & 0x0008) 500 { 501 flash[pc].r = get_q (op1); 502 return OP_ldd_Y; 503 } 504 else 505 { 506 flash[pc].r = get_q (op1); 507 return OP_ldd_Z; 508 } 509 } 510 break; 511 case 0x9: /* 9xxx */ 512 switch ((op1 >> 8) & 0xf) 513 { 514 case 0x0: 515 case 0x1: 516 switch ((op1 >> 0) & 0xf) 517 { 518 case 0x0: 519 return OP_lds; 520 case 0x1: 521 return OP_ld_Z_inc; 522 case 0x2: 523 return OP_ld_dec_Z; 524 case 0x4: 525 return OP_lpm_Z; 526 case 0x5: 527 return OP_lpm_inc_Z; 528 case 0x6: 529 return OP_elpm_Z; 530 case 0x7: 531 return OP_elpm_inc_Z; 532 case 0x9: 533 return OP_ld_Y_inc; 534 case 0xa: 535 return OP_ld_dec_Y; 536 case 0xc: 537 return OP_ld_X; 538 case 0xd: 539 return OP_ld_X_inc; 540 case 0xe: 541 return OP_ld_dec_X; 542 case 0xf: 543 return OP_pop; 544 } 545 break; 546 case 0x2: 547 case 0x3: 548 switch ((op1 >> 0) & 0xf) 549 { 550 case 0x0: 551 return OP_sts; 552 case 0x1: 553 return OP_st_Z_inc; 554 case 0x2: 555 return OP_st_dec_Z; 556 case 0x9: 557 return OP_st_Y_inc; 558 case 0xa: 559 return OP_st_dec_Y; 560 case 0xc: 561 return OP_st_X; 562 case 0xd: 563 return OP_st_X_inc; 564 case 0xe: 565 return OP_st_dec_X; 566 case 0xf: 567 return OP_push; 568 } 569 break; 570 case 0x4: 571 case 0x5: 572 switch (op1 & 0xf) 573 { 574 case 0x0: 575 return OP_com; 576 case 0x1: 577 return OP_neg; 578 case 0x2: 579 return OP_swap; 580 case 0x3: 581 return OP_inc; 582 case 0x5: 583 flash[pc].r = 0x80; 584 return OP_asr; 585 case 0x6: 586 flash[pc].r = 0; 587 return OP_lsr; 588 case 0x7: 589 return OP_ror; 590 case 0x8: /* 9[45]x8 */ 591 switch ((op1 >> 4) & 0x1f) 592 { 593 case 0x00: 594 case 0x01: 595 case 0x02: 596 case 0x03: 597 case 0x04: 598 case 0x05: 599 case 0x06: 600 case 0x07: 601 return OP_bset; 602 case 0x08: 603 case 0x09: 604 case 0x0a: 605 case 0x0b: 606 case 0x0c: 607 case 0x0d: 608 case 0x0e: 609 case 0x0f: 610 return OP_bclr; 611 case 0x10: 612 return OP_ret; 613 case 0x11: 614 return OP_reti; 615 case 0x19: 616 return OP_break; 617 case 0x1c: 618 return OP_lpm; 619 case 0x1d: 620 return OP_elpm; 621 default: 622 break; 623 } 624 break; 625 case 0x9: /* 9[45]x9 */ 626 switch ((op1 >> 4) & 0x1f) 627 { 628 case 0x00: 629 return OP_ijmp; 630 case 0x01: 631 return OP_eijmp; 632 case 0x10: 633 return OP_icall; 634 case 0x11: 635 return OP_eicall; 636 default: 637 break; 638 } 639 break; 640 case 0xa: 641 return OP_dec; 642 case 0xc: 643 case 0xd: 644 flash[pc].r = ((op1 & 0x1f0) >> 3) | (op1 & 1); 645 return OP_jmp; 646 case 0xe: 647 case 0xf: 648 flash[pc].r = ((op1 & 0x1f0) >> 3) | (op1 & 1); 649 return OP_call; 650 } 651 break; 652 case 0x6: 653 return OP_adiw; 654 case 0x7: 655 return OP_sbiw; 656 case 0x8: 657 return OP_cbi; 658 case 0x9: 659 return OP_sbic; 660 case 0xa: 661 return OP_sbi; 662 case 0xb: 663 return OP_sbis; 664 case 0xc: 665 case 0xd: 666 case 0xe: 667 case 0xf: 668 return OP_mul; 669 } 670 break; 671 case 0xb: 672 flash[pc].r = get_A (op1); 673 if (((op1 >> 11) & 1) == 0) 674 return OP_in; 675 else 676 return OP_out; 677 case 0xc: 678 return OP_rjmp; 679 case 0xd: 680 return OP_rcall; 681 case 0xe: 682 return OP_ldi; 683 case 0xf: 684 switch ((op1 >> 9) & 7) 685 { 686 case 0: 687 case 1: 688 flash[pc].r = 1 << (op1 & 7); 689 return OP_brbs; 690 case 2: 691 case 3: 692 flash[pc].r = 1 << (op1 & 7); 693 return OP_brbc; 694 case 4: 695 if ((op1 & 8) == 0) 696 { 697 flash[pc].r = 1 << (op1 & 7); 698 return OP_bld; 699 } 700 break; 701 case 5: 702 if ((op1 & 8) == 0) 703 { 704 flash[pc].r = 1 << (op1 & 7); 705 return OP_bst; 706 } 707 break; 708 case 6: 709 if ((op1 & 8) == 0) 710 { 711 flash[pc].r = 1 << (op1 & 7); 712 return OP_sbrc; 713 } 714 break; 715 case 7: 716 if ((op1 & 8) == 0) 717 { 718 flash[pc].r = 1 << (op1 & 7); 719 return OP_sbrs; 720 } 721 break; 722 } 723 } 724 725 return OP_bad; 726 } 727 728 static void 729 do_call (SIM_CPU *cpu, unsigned int npc) 730 { 731 const struct avr_sim_state *state = AVR_SIM_STATE (CPU_STATE (cpu)); 732 unsigned int sp = read_word (REG_SP); 733 734 /* Big endian! */ 735 sram[sp--] = cpu->pc; 736 sram[sp--] = cpu->pc >> 8; 737 if (state->avr_pc22) 738 { 739 sram[sp--] = cpu->pc >> 16; 740 cpu->cycles++; 741 } 742 write_word (REG_SP, sp); 743 cpu->pc = npc & PC_MASK; 744 cpu->cycles += 3; 745 } 746 747 static int 748 get_insn_length (unsigned int p) 749 { 750 if (flash[p].code == OP_unknown) 751 flash[p].code = decode(p); 752 if (flash[p].code >= OP_2words) 753 return 2; 754 else 755 return 1; 756 } 757 758 static unsigned int 759 get_z (void) 760 { 761 return (sram[RAMPZ] << 16) | (sram[REGZ_HI] << 8) | sram[REGZ_LO]; 762 } 763 764 static unsigned char 765 get_lpm (unsigned int addr) 766 { 767 word w; 768 769 w = flash[(addr >> 1) & PC_MASK].op; 770 if (addr & 1) 771 w >>= 8; 772 return w; 773 } 774 775 static void 776 gen_mul (SIM_CPU *cpu, unsigned int res) 777 { 778 write_word (0, res); 779 sram[SREG] &= ~(SREG_Z | SREG_C); 780 if (res == 0) 781 sram[SREG] |= SREG_Z; 782 if (res & 0x8000) 783 sram[SREG] |= SREG_C; 784 cpu->cycles++; 785 } 786 787 static void 788 step_once (SIM_CPU *cpu) 789 { 790 unsigned int ipc; 791 792 int code; 793 word op; 794 byte res; 795 byte r, d, vd; 796 797 again: 798 code = flash[cpu->pc].code; 799 op = flash[cpu->pc].op; 800 801 #if 0 802 if (tracing && code != OP_unknown) 803 { 804 if (verbose > 0) { 805 int flags; 806 int i; 807 808 sim_cb_eprintf (callback, "R00-07:"); 809 for (i = 0; i < 8; i++) 810 sim_cb_eprintf (callback, " %02x", sram[i]); 811 sim_cb_eprintf (callback, " -"); 812 for (i = 8; i < 16; i++) 813 sim_cb_eprintf (callback, " %02x", sram[i]); 814 sim_cb_eprintf (callback, " SP: %02x %02x", 815 sram[REG_SP + 1], sram[REG_SP]); 816 sim_cb_eprintf (callback, "\n"); 817 sim_cb_eprintf (callback, "R16-31:"); 818 for (i = 16; i < 24; i++) 819 sim_cb_eprintf (callback, " %02x", sram[i]); 820 sim_cb_eprintf (callback, " -"); 821 for (i = 24; i < 32; i++) 822 sim_cb_eprintf (callback, " %02x", sram[i]); 823 sim_cb_eprintf (callback, " "); 824 flags = sram[SREG]; 825 for (i = 0; i < 8; i++) 826 sim_cb_eprintf (callback, "%c", 827 flags & (0x80 >> i) ? "ITHSVNZC"[i] : '-'); 828 sim_cb_eprintf (callback, "\n"); 829 } 830 831 if (!tracing) 832 sim_cb_eprintf (callback, "%06x: %04x\n", 2 * cpu->pc, flash[cpu->pc].op); 833 else 834 { 835 sim_cb_eprintf (callback, "pc=0x%06x insn=0x%04x code=%d r=%d\n", 836 2 * cpu->pc, flash[cpu->pc].op, code, flash[cpu->pc].r); 837 disassemble_insn (CPU_STATE (cpu), cpu->pc); 838 sim_cb_eprintf (callback, "\n"); 839 } 840 } 841 #endif 842 843 ipc = cpu->pc; 844 cpu->pc = (cpu->pc + 1) & PC_MASK; 845 cpu->cycles++; 846 847 switch (code) 848 { 849 case OP_unknown: 850 flash[ipc].code = decode(ipc); 851 cpu->pc = ipc; 852 cpu->cycles--; 853 goto again; 854 855 case OP_nop: 856 break; 857 858 case OP_jmp: 859 /* 2 words instruction, but we don't care about the pc. */ 860 cpu->pc = ((flash[ipc].r << 16) | flash[ipc + 1].op) & PC_MASK; 861 cpu->cycles += 2; 862 break; 863 864 case OP_eijmp: 865 cpu->pc = ((sram[EIND] << 16) | read_word (REGZ)) & PC_MASK; 866 cpu->cycles += 2; 867 break; 868 869 case OP_ijmp: 870 cpu->pc = read_word (REGZ) & PC_MASK; 871 cpu->cycles += 1; 872 break; 873 874 case OP_call: 875 /* 2 words instruction. */ 876 cpu->pc++; 877 do_call (cpu, (flash[ipc].r << 16) | flash[ipc + 1].op); 878 break; 879 880 case OP_eicall: 881 do_call (cpu, (sram[EIND] << 16) | read_word (REGZ)); 882 break; 883 884 case OP_icall: 885 do_call (cpu, read_word (REGZ)); 886 break; 887 888 case OP_rcall: 889 do_call (cpu, cpu->pc + sign_ext (op & 0xfff, 12)); 890 break; 891 892 case OP_reti: 893 sram[SREG] |= SREG_I; 894 /* Fall through */ 895 case OP_ret: 896 { 897 const struct avr_sim_state *state = AVR_SIM_STATE (CPU_STATE (cpu)); 898 unsigned int sp = read_word (REG_SP); 899 if (state->avr_pc22) 900 { 901 cpu->pc = sram[++sp] << 16; 902 cpu->cycles++; 903 } 904 else 905 cpu->pc = 0; 906 cpu->pc |= sram[++sp] << 8; 907 cpu->pc |= sram[++sp]; 908 write_word (REG_SP, sp); 909 } 910 cpu->cycles += 3; 911 break; 912 913 case OP_break: 914 /* Stop on this address. */ 915 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, ipc, sim_stopped, SIM_SIGTRAP); 916 break; 917 918 case OP_bld: 919 d = get_d (op); 920 r = flash[ipc].r; 921 if (sram[SREG] & SREG_T) 922 sram[d] |= r; 923 else 924 sram[d] &= ~r; 925 break; 926 927 case OP_bst: 928 if (sram[get_d (op)] & flash[ipc].r) 929 sram[SREG] |= SREG_T; 930 else 931 sram[SREG] &= ~SREG_T; 932 break; 933 934 case OP_sbrc: 935 case OP_sbrs: 936 if (((sram[get_d (op)] & flash[ipc].r) == 0) ^ ((op & 0x0200) != 0)) 937 { 938 int l = get_insn_length (cpu->pc); 939 cpu->pc += l; 940 cpu->cycles += l; 941 } 942 break; 943 944 case OP_push: 945 { 946 unsigned int sp = read_word (REG_SP); 947 sram[sp--] = sram[get_d (op)]; 948 write_word (REG_SP, sp); 949 } 950 cpu->cycles++; 951 break; 952 953 case OP_pop: 954 { 955 unsigned int sp = read_word (REG_SP); 956 sram[get_d (op)] = sram[++sp]; 957 write_word (REG_SP, sp); 958 } 959 cpu->cycles++; 960 break; 961 962 case OP_bclr: 963 sram[SREG] &= ~(1 << ((op >> 4) & 0x7)); 964 break; 965 966 case OP_bset: 967 sram[SREG] |= 1 << ((op >> 4) & 0x7); 968 break; 969 970 case OP_rjmp: 971 cpu->pc = (cpu->pc + sign_ext (op & 0xfff, 12)) & PC_MASK; 972 cpu->cycles++; 973 break; 974 975 case OP_eor: 976 d = get_d (op); 977 res = sram[d] ^ sram[get_r (op)]; 978 sram[d] = res; 979 update_flags_logic (res); 980 break; 981 982 case OP_and: 983 d = get_d (op); 984 res = sram[d] & sram[get_r (op)]; 985 sram[d] = res; 986 update_flags_logic (res); 987 break; 988 989 case OP_andi: 990 d = get_d16 (op); 991 res = sram[d] & get_K (op); 992 sram[d] = res; 993 update_flags_logic (res); 994 break; 995 996 case OP_or: 997 d = get_d (op); 998 res = sram[d] | sram[get_r (op)]; 999 sram[d] = res; 1000 update_flags_logic (res); 1001 break; 1002 1003 case OP_ori: 1004 d = get_d16 (op); 1005 res = sram[d] | get_K (op); 1006 sram[d] = res; 1007 update_flags_logic (res); 1008 break; 1009 1010 case OP_com: 1011 d = get_d (op); 1012 res = ~sram[d]; 1013 sram[d] = res; 1014 update_flags_logic (res); 1015 sram[SREG] |= SREG_C; 1016 break; 1017 1018 case OP_swap: 1019 d = get_d (op); 1020 vd = sram[d]; 1021 sram[d] = (vd >> 4) | (vd << 4); 1022 break; 1023 1024 case OP_neg: 1025 d = get_d (op); 1026 vd = sram[d]; 1027 res = -vd; 1028 sram[d] = res; 1029 sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C); 1030 if (res == 0) 1031 sram[SREG] |= SREG_Z; 1032 else 1033 sram[SREG] |= SREG_C; 1034 if (res == 0x80) 1035 sram[SREG] |= SREG_V | SREG_N; 1036 else if (res & 0x80) 1037 sram[SREG] |= SREG_N | SREG_S; 1038 if ((res | vd) & 0x08) 1039 sram[SREG] |= SREG_H; 1040 break; 1041 1042 case OP_inc: 1043 d = get_d (op); 1044 res = sram[d] + 1; 1045 sram[d] = res; 1046 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z); 1047 if (res == 0x80) 1048 sram[SREG] |= SREG_V | SREG_N; 1049 else if (res & 0x80) 1050 sram[SREG] |= SREG_N | SREG_S; 1051 else if (res == 0) 1052 sram[SREG] |= SREG_Z; 1053 break; 1054 1055 case OP_dec: 1056 d = get_d (op); 1057 res = sram[d] - 1; 1058 sram[d] = res; 1059 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z); 1060 if (res == 0x7f) 1061 sram[SREG] |= SREG_V | SREG_S; 1062 else if (res & 0x80) 1063 sram[SREG] |= SREG_N | SREG_S; 1064 else if (res == 0) 1065 sram[SREG] |= SREG_Z; 1066 break; 1067 1068 case OP_lsr: 1069 case OP_asr: 1070 d = get_d (op); 1071 vd = sram[d]; 1072 res = (vd >> 1) | (vd & flash[ipc].r); 1073 sram[d] = res; 1074 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C); 1075 if (vd & 1) 1076 sram[SREG] |= SREG_C | SREG_S; 1077 if (res & 0x80) 1078 sram[SREG] |= SREG_N; 1079 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_C)) 1080 sram[SREG] |= SREG_V; 1081 if (res == 0) 1082 sram[SREG] |= SREG_Z; 1083 break; 1084 1085 case OP_ror: 1086 d = get_d (op); 1087 vd = sram[d]; 1088 res = vd >> 1 | (sram[SREG] << 7); 1089 sram[d] = res; 1090 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C); 1091 if (vd & 1) 1092 sram[SREG] |= SREG_C | SREG_S; 1093 if (res & 0x80) 1094 sram[SREG] |= SREG_N; 1095 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_C)) 1096 sram[SREG] |= SREG_V; 1097 if (res == 0) 1098 sram[SREG] |= SREG_Z; 1099 break; 1100 1101 case OP_mul: 1102 gen_mul (cpu, (word)sram[get_r (op)] * (word)sram[get_d (op)]); 1103 break; 1104 1105 case OP_muls: 1106 gen_mul (cpu, (sword)(sbyte)sram[get_r16 (op)] 1107 * (sword)(sbyte)sram[get_d16 (op)]); 1108 break; 1109 1110 case OP_mulsu: 1111 gen_mul (cpu, (sword)(word)sram[get_r16_23 (op)] 1112 * (sword)(sbyte)sram[get_d16_23 (op)]); 1113 break; 1114 1115 case OP_fmul: 1116 gen_mul (cpu, ((word)sram[get_r16_23 (op)] 1117 * (word)sram[get_d16_23 (op)]) << 1); 1118 break; 1119 1120 case OP_fmuls: 1121 gen_mul (cpu, ((sword)(sbyte)sram[get_r16_23 (op)] 1122 * (sword)(sbyte)sram[get_d16_23 (op)]) << 1); 1123 break; 1124 1125 case OP_fmulsu: 1126 gen_mul (cpu, ((sword)(word)sram[get_r16_23 (op)] 1127 * (sword)(sbyte)sram[get_d16_23 (op)]) << 1); 1128 break; 1129 1130 case OP_adc: 1131 case OP_add: 1132 r = sram[get_r (op)]; 1133 d = get_d (op); 1134 vd = sram[d]; 1135 res = r + vd + (sram[SREG] & flash[ipc].r); 1136 sram[d] = res; 1137 update_flags_add (res, vd, r); 1138 break; 1139 1140 case OP_sub: 1141 d = get_d (op); 1142 vd = sram[d]; 1143 r = sram[get_r (op)]; 1144 res = vd - r; 1145 sram[d] = res; 1146 update_flags_sub (res, vd, r); 1147 if (res == 0) 1148 sram[SREG] |= SREG_Z; 1149 break; 1150 1151 case OP_sbc: 1152 { 1153 byte old = sram[SREG]; 1154 d = get_d (op); 1155 vd = sram[d]; 1156 r = sram[get_r (op)]; 1157 res = vd - r - (old & SREG_C); 1158 sram[d] = res; 1159 update_flags_sub (res, vd, r); 1160 if (res == 0 && (old & SREG_Z)) 1161 sram[SREG] |= SREG_Z; 1162 } 1163 break; 1164 1165 case OP_subi: 1166 d = get_d16 (op); 1167 vd = sram[d]; 1168 r = get_K (op); 1169 res = vd - r; 1170 sram[d] = res; 1171 update_flags_sub (res, vd, r); 1172 if (res == 0) 1173 sram[SREG] |= SREG_Z; 1174 break; 1175 1176 case OP_sbci: 1177 { 1178 byte old = sram[SREG]; 1179 1180 d = get_d16 (op); 1181 vd = sram[d]; 1182 r = get_K (op); 1183 res = vd - r - (old & SREG_C); 1184 sram[d] = res; 1185 update_flags_sub (res, vd, r); 1186 if (res == 0 && (old & SREG_Z)) 1187 sram[SREG] |= SREG_Z; 1188 } 1189 break; 1190 1191 case OP_mov: 1192 sram[get_d (op)] = sram[get_r (op)]; 1193 break; 1194 1195 case OP_movw: 1196 d = (op & 0xf0) >> 3; 1197 r = (op & 0x0f) << 1; 1198 sram[d] = sram[r]; 1199 sram[d + 1] = sram[r + 1]; 1200 break; 1201 1202 case OP_out: 1203 d = get_A (op) + 0x20; 1204 res = sram[get_d (op)]; 1205 sram[d] = res; 1206 if (d == STDIO_PORT) 1207 putchar (res); 1208 else if (d == EXIT_PORT) 1209 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, cpu->pc, sim_exited, 0); 1210 else if (d == ABORT_PORT) 1211 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, cpu->pc, sim_exited, 1); 1212 break; 1213 1214 case OP_in: 1215 d = get_A (op) + 0x20; 1216 sram[get_d (op)] = sram[d]; 1217 break; 1218 1219 case OP_cbi: 1220 d = get_biA (op) + 0x20; 1221 sram[d] &= ~(1 << get_b(op)); 1222 break; 1223 1224 case OP_sbi: 1225 d = get_biA (op) + 0x20; 1226 sram[d] |= 1 << get_b(op); 1227 break; 1228 1229 case OP_sbic: 1230 if (!(sram[get_biA (op) + 0x20] & 1 << get_b(op))) 1231 { 1232 int l = get_insn_length (cpu->pc); 1233 cpu->pc += l; 1234 cpu->cycles += l; 1235 } 1236 break; 1237 1238 case OP_sbis: 1239 if (sram[get_biA (op) + 0x20] & 1 << get_b(op)) 1240 { 1241 int l = get_insn_length (cpu->pc); 1242 cpu->pc += l; 1243 cpu->cycles += l; 1244 } 1245 break; 1246 1247 case OP_ldi: 1248 res = get_K (op); 1249 d = get_d16 (op); 1250 sram[d] = res; 1251 break; 1252 1253 case OP_lds: 1254 sram[get_d (op)] = sram[flash[cpu->pc].op]; 1255 cpu->pc++; 1256 cpu->cycles++; 1257 break; 1258 1259 case OP_sts: 1260 sram[flash[cpu->pc].op] = sram[get_d (op)]; 1261 cpu->pc++; 1262 cpu->cycles++; 1263 break; 1264 1265 case OP_cpse: 1266 if (sram[get_r (op)] == sram[get_d (op)]) 1267 { 1268 int l = get_insn_length (cpu->pc); 1269 cpu->pc += l; 1270 cpu->cycles += l; 1271 } 1272 break; 1273 1274 case OP_cp: 1275 r = sram[get_r (op)]; 1276 d = sram[get_d (op)]; 1277 res = d - r; 1278 update_flags_sub (res, d, r); 1279 if (res == 0) 1280 sram[SREG] |= SREG_Z; 1281 break; 1282 1283 case OP_cpi: 1284 r = get_K (op); 1285 d = sram[get_d16 (op)]; 1286 res = d - r; 1287 update_flags_sub (res, d, r); 1288 if (res == 0) 1289 sram[SREG] |= SREG_Z; 1290 break; 1291 1292 case OP_cpc: 1293 { 1294 byte old = sram[SREG]; 1295 d = sram[get_d (op)]; 1296 r = sram[get_r (op)]; 1297 res = d - r - (old & SREG_C); 1298 update_flags_sub (res, d, r); 1299 if (res == 0 && (old & SREG_Z)) 1300 sram[SREG] |= SREG_Z; 1301 } 1302 break; 1303 1304 case OP_brbc: 1305 if (!(sram[SREG] & flash[ipc].r)) 1306 { 1307 cpu->pc = (cpu->pc + get_k (op)) & PC_MASK; 1308 cpu->cycles++; 1309 } 1310 break; 1311 1312 case OP_brbs: 1313 if (sram[SREG] & flash[ipc].r) 1314 { 1315 cpu->pc = (cpu->pc + get_k (op)) & PC_MASK; 1316 cpu->cycles++; 1317 } 1318 break; 1319 1320 case OP_lpm: 1321 sram[0] = get_lpm (read_word (REGZ)); 1322 cpu->cycles += 2; 1323 break; 1324 1325 case OP_lpm_Z: 1326 sram[get_d (op)] = get_lpm (read_word (REGZ)); 1327 cpu->cycles += 2; 1328 break; 1329 1330 case OP_lpm_inc_Z: 1331 sram[get_d (op)] = get_lpm (read_word_post_inc (REGZ)); 1332 cpu->cycles += 2; 1333 break; 1334 1335 case OP_elpm: 1336 sram[0] = get_lpm (get_z ()); 1337 cpu->cycles += 2; 1338 break; 1339 1340 case OP_elpm_Z: 1341 sram[get_d (op)] = get_lpm (get_z ()); 1342 cpu->cycles += 2; 1343 break; 1344 1345 case OP_elpm_inc_Z: 1346 { 1347 unsigned int z = get_z (); 1348 1349 sram[get_d (op)] = get_lpm (z); 1350 z++; 1351 sram[REGZ_LO] = z; 1352 sram[REGZ_HI] = z >> 8; 1353 sram[RAMPZ] = z >> 16; 1354 } 1355 cpu->cycles += 2; 1356 break; 1357 1358 case OP_ld_Z_inc: 1359 sram[get_d (op)] = sram[read_word_post_inc (REGZ) & SRAM_MASK]; 1360 cpu->cycles++; 1361 break; 1362 1363 case OP_ld_dec_Z: 1364 sram[get_d (op)] = sram[read_word_pre_dec (REGZ) & SRAM_MASK]; 1365 cpu->cycles++; 1366 break; 1367 1368 case OP_ld_X_inc: 1369 sram[get_d (op)] = sram[read_word_post_inc (REGX) & SRAM_MASK]; 1370 cpu->cycles++; 1371 break; 1372 1373 case OP_ld_dec_X: 1374 sram[get_d (op)] = sram[read_word_pre_dec (REGX) & SRAM_MASK]; 1375 cpu->cycles++; 1376 break; 1377 1378 case OP_ld_Y_inc: 1379 sram[get_d (op)] = sram[read_word_post_inc (REGY) & SRAM_MASK]; 1380 cpu->cycles++; 1381 break; 1382 1383 case OP_ld_dec_Y: 1384 sram[get_d (op)] = sram[read_word_pre_dec (REGY) & SRAM_MASK]; 1385 cpu->cycles++; 1386 break; 1387 1388 case OP_st_X: 1389 sram[read_word (REGX) & SRAM_MASK] = sram[get_d (op)]; 1390 cpu->cycles++; 1391 break; 1392 1393 case OP_st_X_inc: 1394 sram[read_word_post_inc (REGX) & SRAM_MASK] = sram[get_d (op)]; 1395 cpu->cycles++; 1396 break; 1397 1398 case OP_st_dec_X: 1399 sram[read_word_pre_dec (REGX) & SRAM_MASK] = sram[get_d (op)]; 1400 cpu->cycles++; 1401 break; 1402 1403 case OP_st_Z_inc: 1404 sram[read_word_post_inc (REGZ) & SRAM_MASK] = sram[get_d (op)]; 1405 cpu->cycles++; 1406 break; 1407 1408 case OP_st_dec_Z: 1409 sram[read_word_pre_dec (REGZ) & SRAM_MASK] = sram[get_d (op)]; 1410 cpu->cycles++; 1411 break; 1412 1413 case OP_st_Y_inc: 1414 sram[read_word_post_inc (REGY) & SRAM_MASK] = sram[get_d (op)]; 1415 cpu->cycles++; 1416 break; 1417 1418 case OP_st_dec_Y: 1419 sram[read_word_pre_dec (REGY) & SRAM_MASK] = sram[get_d (op)]; 1420 cpu->cycles++; 1421 break; 1422 1423 case OP_std_Y: 1424 sram[read_word (REGY) + flash[ipc].r] = sram[get_d (op)]; 1425 cpu->cycles++; 1426 break; 1427 1428 case OP_std_Z: 1429 sram[read_word (REGZ) + flash[ipc].r] = sram[get_d (op)]; 1430 cpu->cycles++; 1431 break; 1432 1433 case OP_ldd_Z: 1434 sram[get_d (op)] = sram[read_word (REGZ) + flash[ipc].r]; 1435 cpu->cycles++; 1436 break; 1437 1438 case OP_ldd_Y: 1439 sram[get_d (op)] = sram[read_word (REGY) + flash[ipc].r]; 1440 cpu->cycles++; 1441 break; 1442 1443 case OP_ld_X: 1444 sram[get_d (op)] = sram[read_word (REGX) & SRAM_MASK]; 1445 cpu->cycles++; 1446 break; 1447 1448 case OP_sbiw: 1449 { 1450 word wk = get_k6 (op); 1451 word wres; 1452 word wr; 1453 1454 d = get_d24 (op); 1455 wr = read_word (d); 1456 wres = wr - wk; 1457 1458 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C); 1459 if (wres == 0) 1460 sram[SREG] |= SREG_Z; 1461 if (wres & 0x8000) 1462 sram[SREG] |= SREG_N; 1463 if (wres & ~wr & 0x8000) 1464 sram[SREG] |= SREG_C; 1465 if (~wres & wr & 0x8000) 1466 sram[SREG] |= SREG_V; 1467 if (((~wres & wr) ^ wres) & 0x8000) 1468 sram[SREG] |= SREG_S; 1469 write_word (d, wres); 1470 } 1471 cpu->cycles++; 1472 break; 1473 1474 case OP_adiw: 1475 { 1476 word wk = get_k6 (op); 1477 word wres; 1478 word wr; 1479 1480 d = get_d24 (op); 1481 wr = read_word (d); 1482 wres = wr + wk; 1483 1484 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C); 1485 if (wres == 0) 1486 sram[SREG] |= SREG_Z; 1487 if (wres & 0x8000) 1488 sram[SREG] |= SREG_N; 1489 if (~wres & wr & 0x8000) 1490 sram[SREG] |= SREG_C; 1491 if (wres & ~wr & 0x8000) 1492 sram[SREG] |= SREG_V; 1493 if (((wres & ~wr) ^ wres) & 0x8000) 1494 sram[SREG] |= SREG_S; 1495 write_word (d, wres); 1496 } 1497 cpu->cycles++; 1498 break; 1499 1500 case OP_bad: 1501 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL); 1502 1503 default: 1504 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL); 1505 } 1506 } 1507 1508 void 1509 sim_engine_run (SIM_DESC sd, 1510 int next_cpu_nr, /* ignore */ 1511 int nr_cpus, /* ignore */ 1512 int siggnal) /* ignore */ 1513 { 1514 SIM_CPU *cpu; 1515 1516 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); 1517 1518 cpu = STATE_CPU (sd, 0); 1519 1520 while (1) 1521 { 1522 step_once (cpu); 1523 if (sim_events_tick (sd)) 1524 sim_events_process (sd); 1525 } 1526 } 1527 1528 int 1529 sim_write (SIM_DESC sd, SIM_ADDR addr, const void *buffer, int size) 1530 { 1531 int osize = size; 1532 1533 if (addr >= 0 && addr < SRAM_VADDR) 1534 { 1535 const unsigned char *data = buffer; 1536 while (size > 0 && addr < (MAX_AVR_FLASH << 1)) 1537 { 1538 word val = flash[addr >> 1].op; 1539 1540 if (addr & 1) 1541 val = (val & 0xff) | (data[0] << 8); 1542 else 1543 val = (val & 0xff00) | data[0]; 1544 1545 flash[addr >> 1].op = val; 1546 flash[addr >> 1].code = OP_unknown; 1547 addr++; 1548 data++; 1549 size--; 1550 } 1551 return osize - size; 1552 } 1553 else if (addr >= SRAM_VADDR && addr < SRAM_VADDR + MAX_AVR_SRAM) 1554 { 1555 addr -= SRAM_VADDR; 1556 if (addr + size > MAX_AVR_SRAM) 1557 size = MAX_AVR_SRAM - addr; 1558 memcpy (sram + addr, buffer, size); 1559 return size; 1560 } 1561 else 1562 return 0; 1563 } 1564 1565 int 1566 sim_read (SIM_DESC sd, SIM_ADDR addr, void *buffer, int size) 1567 { 1568 int osize = size; 1569 1570 if (addr >= 0 && addr < SRAM_VADDR) 1571 { 1572 unsigned char *data = buffer; 1573 while (size > 0 && addr < (MAX_AVR_FLASH << 1)) 1574 { 1575 word val = flash[addr >> 1].op; 1576 1577 if (addr & 1) 1578 val >>= 8; 1579 1580 *data++ = val; 1581 addr++; 1582 size--; 1583 } 1584 return osize - size; 1585 } 1586 else if (addr >= SRAM_VADDR && addr < SRAM_VADDR + MAX_AVR_SRAM) 1587 { 1588 addr -= SRAM_VADDR; 1589 if (addr + size > MAX_AVR_SRAM) 1590 size = MAX_AVR_SRAM - addr; 1591 memcpy (buffer, sram + addr, size); 1592 return size; 1593 } 1594 else 1595 { 1596 /* Avoid errors. */ 1597 memset (buffer, 0, size); 1598 return size; 1599 } 1600 } 1601 1602 static int 1603 avr_reg_store (SIM_CPU *cpu, int rn, const void *buf, int length) 1604 { 1605 const unsigned char *memory = buf; 1606 1607 if (rn < 32 && length == 1) 1608 { 1609 sram[rn] = *memory; 1610 return 1; 1611 } 1612 if (rn == AVR_SREG_REGNUM && length == 1) 1613 { 1614 sram[SREG] = *memory; 1615 return 1; 1616 } 1617 if (rn == AVR_SP_REGNUM && length == 2) 1618 { 1619 sram[REG_SP] = memory[0]; 1620 sram[REG_SP + 1] = memory[1]; 1621 return 2; 1622 } 1623 if (rn == AVR_PC_REGNUM && length == 4) 1624 { 1625 cpu->pc = (memory[0] >> 1) | (memory[1] << 7) 1626 | (memory[2] << 15) | (memory[3] << 23); 1627 cpu->pc &= PC_MASK; 1628 return 4; 1629 } 1630 return 0; 1631 } 1632 1633 static int 1634 avr_reg_fetch (SIM_CPU *cpu, int rn, void *buf, int length) 1635 { 1636 unsigned char *memory = buf; 1637 1638 if (rn < 32 && length == 1) 1639 { 1640 *memory = sram[rn]; 1641 return 1; 1642 } 1643 if (rn == AVR_SREG_REGNUM && length == 1) 1644 { 1645 *memory = sram[SREG]; 1646 return 1; 1647 } 1648 if (rn == AVR_SP_REGNUM && length == 2) 1649 { 1650 memory[0] = sram[REG_SP]; 1651 memory[1] = sram[REG_SP + 1]; 1652 return 2; 1653 } 1654 if (rn == AVR_PC_REGNUM && length == 4) 1655 { 1656 memory[0] = cpu->pc << 1; 1657 memory[1] = cpu->pc >> 7; 1658 memory[2] = cpu->pc >> 15; 1659 memory[3] = cpu->pc >> 23; 1660 return 4; 1661 } 1662 return 0; 1663 } 1664 1665 static sim_cia 1666 avr_pc_get (sim_cpu *cpu) 1667 { 1668 return cpu->pc; 1669 } 1670 1671 static void 1672 avr_pc_set (sim_cpu *cpu, sim_cia pc) 1673 { 1674 cpu->pc = pc; 1675 } 1676 1677 static void 1678 free_state (SIM_DESC sd) 1679 { 1680 if (STATE_MODULES (sd) != NULL) 1681 sim_module_uninstall (sd); 1682 sim_cpu_free_all (sd); 1683 sim_state_free (sd); 1684 } 1685 1686 SIM_DESC 1687 sim_open (SIM_OPEN_KIND kind, host_callback *cb, 1688 struct bfd *abfd, char * const *argv) 1689 { 1690 int i; 1691 SIM_DESC sd = sim_state_alloc_extra (kind, cb, sizeof (struct avr_sim_state)); 1692 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); 1693 1694 /* Set default options before parsing user options. */ 1695 current_alignment = STRICT_ALIGNMENT; 1696 current_target_byte_order = BFD_ENDIAN_LITTLE; 1697 1698 /* The cpu data is kept in a separately allocated chunk of memory. */ 1699 if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK) 1700 { 1701 free_state (sd); 1702 return 0; 1703 } 1704 1705 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) 1706 { 1707 free_state (sd); 1708 return 0; 1709 } 1710 1711 /* The parser will print an error message for us, so we silently return. */ 1712 if (sim_parse_args (sd, argv) != SIM_RC_OK) 1713 { 1714 free_state (sd); 1715 return 0; 1716 } 1717 1718 /* Check for/establish the a reference program image. */ 1719 if (sim_analyze_program (sd, STATE_PROG_FILE (sd), abfd) != SIM_RC_OK) 1720 { 1721 free_state (sd); 1722 return 0; 1723 } 1724 1725 /* Configure/verify the target byte order and other runtime 1726 configuration options. */ 1727 if (sim_config (sd) != SIM_RC_OK) 1728 { 1729 sim_module_uninstall (sd); 1730 return 0; 1731 } 1732 1733 if (sim_post_argv_init (sd) != SIM_RC_OK) 1734 { 1735 /* Uninstall the modules to avoid memory leaks, 1736 file descriptor leaks, etc. */ 1737 sim_module_uninstall (sd); 1738 return 0; 1739 } 1740 1741 /* CPU specific initialization. */ 1742 for (i = 0; i < MAX_NR_PROCESSORS; ++i) 1743 { 1744 SIM_CPU *cpu = STATE_CPU (sd, i); 1745 1746 CPU_REG_FETCH (cpu) = avr_reg_fetch; 1747 CPU_REG_STORE (cpu) = avr_reg_store; 1748 CPU_PC_FETCH (cpu) = avr_pc_get; 1749 CPU_PC_STORE (cpu) = avr_pc_set; 1750 } 1751 1752 /* Clear all the memory. */ 1753 memset (sram, 0, sizeof (sram)); 1754 memset (flash, 0, sizeof (flash)); 1755 1756 return sd; 1757 } 1758 1759 SIM_RC 1760 sim_create_inferior (SIM_DESC sd, struct bfd *abfd, 1761 char * const *argv, char * const *env) 1762 { 1763 struct avr_sim_state *state = AVR_SIM_STATE (sd); 1764 SIM_CPU *cpu = STATE_CPU (sd, 0); 1765 SIM_ADDR addr; 1766 1767 /* Set the PC. */ 1768 if (abfd != NULL) 1769 addr = bfd_get_start_address (abfd); 1770 else 1771 addr = 0; 1772 sim_pc_set (cpu, addr); 1773 1774 if (abfd != NULL) 1775 state->avr_pc22 = (bfd_get_mach (abfd) >= bfd_mach_avr6); 1776 1777 return SIM_RC_OK; 1778 } 1779