1 /* Simulator for Atmel's AVR core. 2 Copyright (C) 2009-2020 Free Software Foundation, Inc. 3 Written by Tristan Gingold, AdaCore. 4 5 This file is part of GDB, the GNU debugger. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #include "config.h" 21 22 #ifdef HAVE_STRING_H 23 #include <string.h> 24 #endif 25 #include "bfd.h" 26 #include "libiberty.h" 27 #include "gdb/remote-sim.h" 28 29 #include "sim-main.h" 30 #include "sim-base.h" 31 #include "sim-options.h" 32 33 /* As AVR is a 8/16 bits processor, define handy types. */ 34 typedef unsigned short int word; 35 typedef signed short int sword; 36 typedef unsigned char byte; 37 typedef signed char sbyte; 38 39 /* Max size of I space (which is always flash on avr). */ 40 #define MAX_AVR_FLASH (128 * 1024) 41 #define PC_MASK (MAX_AVR_FLASH - 1) 42 43 /* Mac size of D space. */ 44 #define MAX_AVR_SRAM (64 * 1024) 45 #define SRAM_MASK (MAX_AVR_SRAM - 1) 46 47 /* D space offset in ELF file. */ 48 #define SRAM_VADDR 0x800000 49 50 /* Simulator specific ports. */ 51 #define STDIO_PORT 0x52 52 #define EXIT_PORT 0x4F 53 #define ABORT_PORT 0x49 54 55 /* GDB defined register numbers. */ 56 #define AVR_SREG_REGNUM 32 57 #define AVR_SP_REGNUM 33 58 #define AVR_PC_REGNUM 34 59 60 /* Memory mapped registers. */ 61 #define SREG 0x5F 62 #define REG_SP 0x5D 63 #define EIND 0x5C 64 #define RAMPZ 0x5B 65 66 #define REGX 0x1a 67 #define REGY 0x1c 68 #define REGZ 0x1e 69 #define REGZ_LO 0x1e 70 #define REGZ_HI 0x1f 71 72 /* Sreg (status) bits. */ 73 #define SREG_I 0x80 74 #define SREG_T 0x40 75 #define SREG_H 0x20 76 #define SREG_S 0x10 77 #define SREG_V 0x08 78 #define SREG_N 0x04 79 #define SREG_Z 0x02 80 #define SREG_C 0x01 81 82 /* In order to speed up emulation we use a simple approach: 83 a code is associated with each instruction. The pre-decoding occurs 84 usually once when the instruction is first seen. 85 This works well because I&D spaces are separated. 86 87 Missing opcodes: sleep, spm, wdr (as they are mmcu dependent). 88 */ 89 enum avr_opcode 90 { 91 /* Opcode not yet decoded. */ 92 OP_unknown, 93 OP_bad, 94 95 OP_nop, 96 97 OP_rjmp, 98 OP_rcall, 99 OP_ret, 100 OP_reti, 101 102 OP_break, 103 104 OP_brbs, 105 OP_brbc, 106 107 OP_bset, 108 OP_bclr, 109 110 OP_bld, 111 OP_bst, 112 113 OP_sbrc, 114 OP_sbrs, 115 116 OP_eor, 117 OP_and, 118 OP_andi, 119 OP_or, 120 OP_ori, 121 OP_com, 122 OP_swap, 123 OP_neg, 124 125 OP_out, 126 OP_in, 127 OP_cbi, 128 OP_sbi, 129 130 OP_sbic, 131 OP_sbis, 132 133 OP_ldi, 134 OP_cpse, 135 OP_cp, 136 OP_cpi, 137 OP_cpc, 138 OP_sub, 139 OP_sbc, 140 OP_sbiw, 141 OP_adiw, 142 OP_add, 143 OP_adc, 144 OP_subi, 145 OP_sbci, 146 OP_inc, 147 OP_dec, 148 OP_lsr, 149 OP_ror, 150 OP_asr, 151 152 OP_mul, 153 OP_muls, 154 OP_mulsu, 155 OP_fmul, 156 OP_fmuls, 157 OP_fmulsu, 158 159 OP_mov, 160 OP_movw, 161 162 OP_push, 163 OP_pop, 164 165 OP_st_X, 166 OP_st_dec_X, 167 OP_st_X_inc, 168 OP_st_Y_inc, 169 OP_st_dec_Y, 170 OP_st_Z_inc, 171 OP_st_dec_Z, 172 OP_std_Y, 173 OP_std_Z, 174 OP_ldd_Y, 175 OP_ldd_Z, 176 OP_ld_Z_inc, 177 OP_ld_dec_Z, 178 OP_ld_Y_inc, 179 OP_ld_dec_Y, 180 OP_ld_X, 181 OP_ld_X_inc, 182 OP_ld_dec_X, 183 184 OP_lpm, 185 OP_lpm_Z, 186 OP_lpm_inc_Z, 187 OP_elpm, 188 OP_elpm_Z, 189 OP_elpm_inc_Z, 190 191 OP_ijmp, 192 OP_icall, 193 194 OP_eijmp, 195 OP_eicall, 196 197 /* 2 words opcodes. */ 198 #define OP_2words OP_jmp 199 OP_jmp, 200 OP_call, 201 OP_sts, 202 OP_lds 203 }; 204 205 struct avr_insn_cell 206 { 207 /* The insn (16 bits). */ 208 word op; 209 210 /* Pre-decoding code. */ 211 enum avr_opcode code : 8; 212 /* One byte of additional information. */ 213 byte r; 214 }; 215 216 /* I&D memories. */ 217 /* TODO: Should be moved to SIM_CPU. */ 218 static struct avr_insn_cell flash[MAX_AVR_FLASH]; 219 static byte sram[MAX_AVR_SRAM]; 220 221 /* Sign extend a value. */ 222 static int sign_ext (word val, int nb_bits) 223 { 224 if (val & (1 << (nb_bits - 1))) 225 return val | -(1 << nb_bits); 226 return val; 227 } 228 229 /* Insn field extractors. */ 230 231 /* Extract xxxx_xxxRx_xxxx_RRRR. */ 232 static inline byte get_r (word op) 233 { 234 return (op & 0xf) | ((op >> 5) & 0x10); 235 } 236 237 /* Extract xxxx_xxxxx_xxxx_RRRR. */ 238 static inline byte get_r16 (word op) 239 { 240 return 16 + (op & 0xf); 241 } 242 243 /* Extract xxxx_xxxxx_xxxx_xRRR. */ 244 static inline byte get_r16_23 (word op) 245 { 246 return 16 + (op & 0x7); 247 } 248 249 /* Extract xxxx_xxxD_DDDD_xxxx. */ 250 static inline byte get_d (word op) 251 { 252 return (op >> 4) & 0x1f; 253 } 254 255 /* Extract xxxx_xxxx_DDDD_xxxx. */ 256 static inline byte get_d16 (word op) 257 { 258 return 16 + ((op >> 4) & 0x0f); 259 } 260 261 /* Extract xxxx_xxxx_xDDD_xxxx. */ 262 static inline byte get_d16_23 (word op) 263 { 264 return 16 + ((op >> 4) & 0x07); 265 } 266 267 /* Extract xxxx_xAAx_xxxx_AAAA. */ 268 static inline byte get_A (word op) 269 { 270 return (op & 0x0f) | ((op & 0x600) >> 5); 271 } 272 273 /* Extract xxxx_xxxx_AAAA_Axxx. */ 274 static inline byte get_biA (word op) 275 { 276 return (op >> 3) & 0x1f; 277 } 278 279 /* Extract xxxx_KKKK_xxxx_KKKK. */ 280 static inline byte get_K (word op) 281 { 282 return (op & 0xf) | ((op & 0xf00) >> 4); 283 } 284 285 /* Extract xxxx_xxKK_KKKK_Kxxx. */ 286 static inline int get_k (word op) 287 { 288 return sign_ext ((op & 0x3f8) >> 3, 7); 289 } 290 291 /* Extract xxxx_xxxx_xxDD_xxxx. */ 292 static inline byte get_d24 (word op) 293 { 294 return 24 + ((op >> 3) & 6); 295 } 296 297 /* Extract xxxx_xxxx_KKxx_KKKK. */ 298 static inline byte get_k6 (word op) 299 { 300 return (op & 0xf) | ((op >> 2) & 0x30); 301 } 302 303 /* Extract xxQx_QQxx_xxxx_xQQQ. */ 304 static inline byte get_q (word op) 305 { 306 return (op & 7) | ((op >> 7) & 0x18)| ((op >> 8) & 0x20); 307 } 308 309 /* Extract xxxx_xxxx_xxxx_xBBB. */ 310 static inline byte get_b (word op) 311 { 312 return (op & 7); 313 } 314 315 /* AVR is little endian. */ 316 static inline word 317 read_word (unsigned int addr) 318 { 319 return sram[addr] | (sram[addr + 1] << 8); 320 } 321 322 static inline void 323 write_word (unsigned int addr, word w) 324 { 325 sram[addr] = w; 326 sram[addr + 1] = w >> 8; 327 } 328 329 static inline word 330 read_word_post_inc (unsigned int addr) 331 { 332 word v = read_word (addr); 333 write_word (addr, v + 1); 334 return v; 335 } 336 337 static inline word 338 read_word_pre_dec (unsigned int addr) 339 { 340 word v = read_word (addr) - 1; 341 write_word (addr, v); 342 return v; 343 } 344 345 static void 346 update_flags_logic (byte res) 347 { 348 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z); 349 if (res == 0) 350 sram[SREG] |= SREG_Z; 351 if (res & 0x80) 352 sram[SREG] |= SREG_N | SREG_S; 353 } 354 355 static void 356 update_flags_add (byte r, byte a, byte b) 357 { 358 byte carry; 359 360 sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C); 361 if (r & 0x80) 362 sram[SREG] |= SREG_N; 363 carry = (a & b) | (a & ~r) | (b & ~r); 364 if (carry & 0x08) 365 sram[SREG] |= SREG_H; 366 if (carry & 0x80) 367 sram[SREG] |= SREG_C; 368 if (((a & b & ~r) | (~a & ~b & r)) & 0x80) 369 sram[SREG] |= SREG_V; 370 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_V)) 371 sram[SREG] |= SREG_S; 372 if (r == 0) 373 sram[SREG] |= SREG_Z; 374 } 375 376 static void update_flags_sub (byte r, byte a, byte b) 377 { 378 byte carry; 379 380 sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C); 381 if (r & 0x80) 382 sram[SREG] |= SREG_N; 383 carry = (~a & b) | (b & r) | (r & ~a); 384 if (carry & 0x08) 385 sram[SREG] |= SREG_H; 386 if (carry & 0x80) 387 sram[SREG] |= SREG_C; 388 if (((a & ~b & ~r) | (~a & b & r)) & 0x80) 389 sram[SREG] |= SREG_V; 390 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_V)) 391 sram[SREG] |= SREG_S; 392 /* Note: Z is not set. */ 393 } 394 395 static enum avr_opcode 396 decode (unsigned int pc) 397 { 398 word op1 = flash[pc].op; 399 400 switch ((op1 >> 12) & 0x0f) 401 { 402 case 0x0: 403 switch ((op1 >> 10) & 0x3) 404 { 405 case 0x0: 406 switch ((op1 >> 8) & 0x3) 407 { 408 case 0x0: 409 if (op1 == 0) 410 return OP_nop; 411 break; 412 case 0x1: 413 return OP_movw; 414 case 0x2: 415 return OP_muls; 416 case 0x3: 417 if (op1 & 0x80) 418 { 419 if (op1 & 0x08) 420 return OP_fmulsu; 421 else 422 return OP_fmuls; 423 } 424 else 425 { 426 if (op1 & 0x08) 427 return OP_fmul; 428 else 429 return OP_mulsu; 430 } 431 } 432 break; 433 case 0x1: 434 return OP_cpc; 435 case 0x2: 436 flash[pc].r = SREG_C; 437 return OP_sbc; 438 case 0x3: 439 flash[pc].r = 0; 440 return OP_add; 441 } 442 break; 443 case 0x1: 444 switch ((op1 >> 10) & 0x3) 445 { 446 case 0x0: 447 return OP_cpse; 448 case 0x1: 449 return OP_cp; 450 case 0x2: 451 flash[pc].r = 0; 452 return OP_sub; 453 case 0x3: 454 flash[pc].r = SREG_C; 455 return OP_adc; 456 } 457 break; 458 case 0x2: 459 switch ((op1 >> 10) & 0x3) 460 { 461 case 0x0: 462 return OP_and; 463 case 0x1: 464 return OP_eor; 465 case 0x2: 466 return OP_or; 467 case 0x3: 468 return OP_mov; 469 } 470 break; 471 case 0x3: 472 return OP_cpi; 473 case 0x4: 474 return OP_sbci; 475 case 0x5: 476 return OP_subi; 477 case 0x6: 478 return OP_ori; 479 case 0x7: 480 return OP_andi; 481 case 0x8: 482 case 0xa: 483 if (op1 & 0x0200) 484 { 485 if (op1 & 0x0008) 486 { 487 flash[pc].r = get_q (op1); 488 return OP_std_Y; 489 } 490 else 491 { 492 flash[pc].r = get_q (op1); 493 return OP_std_Z; 494 } 495 } 496 else 497 { 498 if (op1 & 0x0008) 499 { 500 flash[pc].r = get_q (op1); 501 return OP_ldd_Y; 502 } 503 else 504 { 505 flash[pc].r = get_q (op1); 506 return OP_ldd_Z; 507 } 508 } 509 break; 510 case 0x9: /* 9xxx */ 511 switch ((op1 >> 8) & 0xf) 512 { 513 case 0x0: 514 case 0x1: 515 switch ((op1 >> 0) & 0xf) 516 { 517 case 0x0: 518 return OP_lds; 519 case 0x1: 520 return OP_ld_Z_inc; 521 case 0x2: 522 return OP_ld_dec_Z; 523 case 0x4: 524 return OP_lpm_Z; 525 case 0x5: 526 return OP_lpm_inc_Z; 527 case 0x6: 528 return OP_elpm_Z; 529 case 0x7: 530 return OP_elpm_inc_Z; 531 case 0x9: 532 return OP_ld_Y_inc; 533 case 0xa: 534 return OP_ld_dec_Y; 535 case 0xc: 536 return OP_ld_X; 537 case 0xd: 538 return OP_ld_X_inc; 539 case 0xe: 540 return OP_ld_dec_X; 541 case 0xf: 542 return OP_pop; 543 } 544 break; 545 case 0x2: 546 case 0x3: 547 switch ((op1 >> 0) & 0xf) 548 { 549 case 0x0: 550 return OP_sts; 551 case 0x1: 552 return OP_st_Z_inc; 553 case 0x2: 554 return OP_st_dec_Z; 555 case 0x9: 556 return OP_st_Y_inc; 557 case 0xa: 558 return OP_st_dec_Y; 559 case 0xc: 560 return OP_st_X; 561 case 0xd: 562 return OP_st_X_inc; 563 case 0xe: 564 return OP_st_dec_X; 565 case 0xf: 566 return OP_push; 567 } 568 break; 569 case 0x4: 570 case 0x5: 571 switch (op1 & 0xf) 572 { 573 case 0x0: 574 return OP_com; 575 case 0x1: 576 return OP_neg; 577 case 0x2: 578 return OP_swap; 579 case 0x3: 580 return OP_inc; 581 case 0x5: 582 flash[pc].r = 0x80; 583 return OP_asr; 584 case 0x6: 585 flash[pc].r = 0; 586 return OP_lsr; 587 case 0x7: 588 return OP_ror; 589 case 0x8: /* 9[45]x8 */ 590 switch ((op1 >> 4) & 0x1f) 591 { 592 case 0x00: 593 case 0x01: 594 case 0x02: 595 case 0x03: 596 case 0x04: 597 case 0x05: 598 case 0x06: 599 case 0x07: 600 return OP_bset; 601 case 0x08: 602 case 0x09: 603 case 0x0a: 604 case 0x0b: 605 case 0x0c: 606 case 0x0d: 607 case 0x0e: 608 case 0x0f: 609 return OP_bclr; 610 case 0x10: 611 return OP_ret; 612 case 0x11: 613 return OP_reti; 614 case 0x19: 615 return OP_break; 616 case 0x1c: 617 return OP_lpm; 618 case 0x1d: 619 return OP_elpm; 620 default: 621 break; 622 } 623 break; 624 case 0x9: /* 9[45]x9 */ 625 switch ((op1 >> 4) & 0x1f) 626 { 627 case 0x00: 628 return OP_ijmp; 629 case 0x01: 630 return OP_eijmp; 631 case 0x10: 632 return OP_icall; 633 case 0x11: 634 return OP_eicall; 635 default: 636 break; 637 } 638 break; 639 case 0xa: 640 return OP_dec; 641 case 0xc: 642 case 0xd: 643 flash[pc].r = ((op1 & 0x1f0) >> 3) | (op1 & 1); 644 return OP_jmp; 645 case 0xe: 646 case 0xf: 647 flash[pc].r = ((op1 & 0x1f0) >> 3) | (op1 & 1); 648 return OP_call; 649 } 650 break; 651 case 0x6: 652 return OP_adiw; 653 case 0x7: 654 return OP_sbiw; 655 case 0x8: 656 return OP_cbi; 657 case 0x9: 658 return OP_sbic; 659 case 0xa: 660 return OP_sbi; 661 case 0xb: 662 return OP_sbis; 663 case 0xc: 664 case 0xd: 665 case 0xe: 666 case 0xf: 667 return OP_mul; 668 } 669 break; 670 case 0xb: 671 flash[pc].r = get_A (op1); 672 if (((op1 >> 11) & 1) == 0) 673 return OP_in; 674 else 675 return OP_out; 676 case 0xc: 677 return OP_rjmp; 678 case 0xd: 679 return OP_rcall; 680 case 0xe: 681 return OP_ldi; 682 case 0xf: 683 switch ((op1 >> 9) & 7) 684 { 685 case 0: 686 case 1: 687 flash[pc].r = 1 << (op1 & 7); 688 return OP_brbs; 689 case 2: 690 case 3: 691 flash[pc].r = 1 << (op1 & 7); 692 return OP_brbc; 693 case 4: 694 if ((op1 & 8) == 0) 695 { 696 flash[pc].r = 1 << (op1 & 7); 697 return OP_bld; 698 } 699 break; 700 case 5: 701 if ((op1 & 8) == 0) 702 { 703 flash[pc].r = 1 << (op1 & 7); 704 return OP_bst; 705 } 706 break; 707 case 6: 708 if ((op1 & 8) == 0) 709 { 710 flash[pc].r = 1 << (op1 & 7); 711 return OP_sbrc; 712 } 713 break; 714 case 7: 715 if ((op1 & 8) == 0) 716 { 717 flash[pc].r = 1 << (op1 & 7); 718 return OP_sbrs; 719 } 720 break; 721 } 722 } 723 724 return OP_bad; 725 } 726 727 static void 728 do_call (SIM_CPU *cpu, unsigned int npc) 729 { 730 SIM_DESC sd = CPU_STATE (cpu); 731 unsigned int sp = read_word (REG_SP); 732 733 /* Big endian! */ 734 sram[sp--] = cpu->pc; 735 sram[sp--] = cpu->pc >> 8; 736 if (sd->avr_pc22) 737 { 738 sram[sp--] = cpu->pc >> 16; 739 cpu->cycles++; 740 } 741 write_word (REG_SP, sp); 742 cpu->pc = npc & PC_MASK; 743 cpu->cycles += 3; 744 } 745 746 static int 747 get_insn_length (unsigned int p) 748 { 749 if (flash[p].code == OP_unknown) 750 flash[p].code = decode(p); 751 if (flash[p].code >= OP_2words) 752 return 2; 753 else 754 return 1; 755 } 756 757 static unsigned int 758 get_z (void) 759 { 760 return (sram[RAMPZ] << 16) | (sram[REGZ_HI] << 8) | sram[REGZ_LO]; 761 } 762 763 static unsigned char 764 get_lpm (unsigned int addr) 765 { 766 word w; 767 768 w = flash[(addr >> 1) & PC_MASK].op; 769 if (addr & 1) 770 w >>= 8; 771 return w; 772 } 773 774 static void 775 gen_mul (SIM_CPU *cpu, unsigned int res) 776 { 777 write_word (0, res); 778 sram[SREG] &= ~(SREG_Z | SREG_C); 779 if (res == 0) 780 sram[SREG] |= SREG_Z; 781 if (res & 0x8000) 782 sram[SREG] |= SREG_C; 783 cpu->cycles++; 784 } 785 786 static void 787 step_once (SIM_CPU *cpu) 788 { 789 unsigned int ipc; 790 791 int code; 792 word op; 793 byte res; 794 byte r, d, vd; 795 796 again: 797 code = flash[cpu->pc].code; 798 op = flash[cpu->pc].op; 799 800 #if 0 801 if (tracing && code != OP_unknown) 802 { 803 if (verbose > 0) { 804 int flags; 805 int i; 806 807 sim_cb_eprintf (callback, "R00-07:"); 808 for (i = 0; i < 8; i++) 809 sim_cb_eprintf (callback, " %02x", sram[i]); 810 sim_cb_eprintf (callback, " -"); 811 for (i = 8; i < 16; i++) 812 sim_cb_eprintf (callback, " %02x", sram[i]); 813 sim_cb_eprintf (callback, " SP: %02x %02x", 814 sram[REG_SP + 1], sram[REG_SP]); 815 sim_cb_eprintf (callback, "\n"); 816 sim_cb_eprintf (callback, "R16-31:"); 817 for (i = 16; i < 24; i++) 818 sim_cb_eprintf (callback, " %02x", sram[i]); 819 sim_cb_eprintf (callback, " -"); 820 for (i = 24; i < 32; i++) 821 sim_cb_eprintf (callback, " %02x", sram[i]); 822 sim_cb_eprintf (callback, " "); 823 flags = sram[SREG]; 824 for (i = 0; i < 8; i++) 825 sim_cb_eprintf (callback, "%c", 826 flags & (0x80 >> i) ? "ITHSVNZC"[i] : '-'); 827 sim_cb_eprintf (callback, "\n"); 828 } 829 830 if (!tracing) 831 sim_cb_eprintf (callback, "%06x: %04x\n", 2 * cpu->pc, flash[cpu->pc].op); 832 else 833 { 834 sim_cb_eprintf (callback, "pc=0x%06x insn=0x%04x code=%d r=%d\n", 835 2 * cpu->pc, flash[cpu->pc].op, code, flash[cpu->pc].r); 836 disassemble_insn (CPU_STATE (cpu), cpu->pc); 837 sim_cb_eprintf (callback, "\n"); 838 } 839 } 840 #endif 841 842 ipc = cpu->pc; 843 cpu->pc = (cpu->pc + 1) & PC_MASK; 844 cpu->cycles++; 845 846 switch (code) 847 { 848 case OP_unknown: 849 flash[ipc].code = decode(ipc); 850 cpu->pc = ipc; 851 cpu->cycles--; 852 goto again; 853 854 case OP_nop: 855 break; 856 857 case OP_jmp: 858 /* 2 words instruction, but we don't care about the pc. */ 859 cpu->pc = ((flash[ipc].r << 16) | flash[ipc + 1].op) & PC_MASK; 860 cpu->cycles += 2; 861 break; 862 863 case OP_eijmp: 864 cpu->pc = ((sram[EIND] << 16) | read_word (REGZ)) & PC_MASK; 865 cpu->cycles += 2; 866 break; 867 868 case OP_ijmp: 869 cpu->pc = read_word (REGZ) & PC_MASK; 870 cpu->cycles += 1; 871 break; 872 873 case OP_call: 874 /* 2 words instruction. */ 875 cpu->pc++; 876 do_call (cpu, (flash[ipc].r << 16) | flash[ipc + 1].op); 877 break; 878 879 case OP_eicall: 880 do_call (cpu, (sram[EIND] << 16) | read_word (REGZ)); 881 break; 882 883 case OP_icall: 884 do_call (cpu, read_word (REGZ)); 885 break; 886 887 case OP_rcall: 888 do_call (cpu, cpu->pc + sign_ext (op & 0xfff, 12)); 889 break; 890 891 case OP_reti: 892 sram[SREG] |= SREG_I; 893 /* Fall through */ 894 case OP_ret: 895 { 896 SIM_DESC sd = CPU_STATE (cpu); 897 unsigned int sp = read_word (REG_SP); 898 if (sd->avr_pc22) 899 { 900 cpu->pc = sram[++sp] << 16; 901 cpu->cycles++; 902 } 903 else 904 cpu->pc = 0; 905 cpu->pc |= sram[++sp] << 8; 906 cpu->pc |= sram[++sp]; 907 write_word (REG_SP, sp); 908 } 909 cpu->cycles += 3; 910 break; 911 912 case OP_break: 913 /* Stop on this address. */ 914 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, ipc, sim_stopped, SIM_SIGTRAP); 915 break; 916 917 case OP_bld: 918 d = get_d (op); 919 r = flash[ipc].r; 920 if (sram[SREG] & SREG_T) 921 sram[d] |= r; 922 else 923 sram[d] &= ~r; 924 break; 925 926 case OP_bst: 927 if (sram[get_d (op)] & flash[ipc].r) 928 sram[SREG] |= SREG_T; 929 else 930 sram[SREG] &= ~SREG_T; 931 break; 932 933 case OP_sbrc: 934 case OP_sbrs: 935 if (((sram[get_d (op)] & flash[ipc].r) == 0) ^ ((op & 0x0200) != 0)) 936 { 937 int l = get_insn_length (cpu->pc); 938 cpu->pc += l; 939 cpu->cycles += l; 940 } 941 break; 942 943 case OP_push: 944 { 945 unsigned int sp = read_word (REG_SP); 946 sram[sp--] = sram[get_d (op)]; 947 write_word (REG_SP, sp); 948 } 949 cpu->cycles++; 950 break; 951 952 case OP_pop: 953 { 954 unsigned int sp = read_word (REG_SP); 955 sram[get_d (op)] = sram[++sp]; 956 write_word (REG_SP, sp); 957 } 958 cpu->cycles++; 959 break; 960 961 case OP_bclr: 962 sram[SREG] &= ~(1 << ((op >> 4) & 0x7)); 963 break; 964 965 case OP_bset: 966 sram[SREG] |= 1 << ((op >> 4) & 0x7); 967 break; 968 969 case OP_rjmp: 970 cpu->pc = (cpu->pc + sign_ext (op & 0xfff, 12)) & PC_MASK; 971 cpu->cycles++; 972 break; 973 974 case OP_eor: 975 d = get_d (op); 976 res = sram[d] ^ sram[get_r (op)]; 977 sram[d] = res; 978 update_flags_logic (res); 979 break; 980 981 case OP_and: 982 d = get_d (op); 983 res = sram[d] & sram[get_r (op)]; 984 sram[d] = res; 985 update_flags_logic (res); 986 break; 987 988 case OP_andi: 989 d = get_d16 (op); 990 res = sram[d] & get_K (op); 991 sram[d] = res; 992 update_flags_logic (res); 993 break; 994 995 case OP_or: 996 d = get_d (op); 997 res = sram[d] | sram[get_r (op)]; 998 sram[d] = res; 999 update_flags_logic (res); 1000 break; 1001 1002 case OP_ori: 1003 d = get_d16 (op); 1004 res = sram[d] | get_K (op); 1005 sram[d] = res; 1006 update_flags_logic (res); 1007 break; 1008 1009 case OP_com: 1010 d = get_d (op); 1011 res = ~sram[d]; 1012 sram[d] = res; 1013 update_flags_logic (res); 1014 sram[SREG] |= SREG_C; 1015 break; 1016 1017 case OP_swap: 1018 d = get_d (op); 1019 vd = sram[d]; 1020 sram[d] = (vd >> 4) | (vd << 4); 1021 break; 1022 1023 case OP_neg: 1024 d = get_d (op); 1025 vd = sram[d]; 1026 res = -vd; 1027 sram[d] = res; 1028 sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C); 1029 if (res == 0) 1030 sram[SREG] |= SREG_Z; 1031 else 1032 sram[SREG] |= SREG_C; 1033 if (res == 0x80) 1034 sram[SREG] |= SREG_V | SREG_N; 1035 else if (res & 0x80) 1036 sram[SREG] |= SREG_N | SREG_S; 1037 if ((res | vd) & 0x08) 1038 sram[SREG] |= SREG_H; 1039 break; 1040 1041 case OP_inc: 1042 d = get_d (op); 1043 res = sram[d] + 1; 1044 sram[d] = res; 1045 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z); 1046 if (res == 0x80) 1047 sram[SREG] |= SREG_V | SREG_N; 1048 else if (res & 0x80) 1049 sram[SREG] |= SREG_N | SREG_S; 1050 else if (res == 0) 1051 sram[SREG] |= SREG_Z; 1052 break; 1053 1054 case OP_dec: 1055 d = get_d (op); 1056 res = sram[d] - 1; 1057 sram[d] = res; 1058 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z); 1059 if (res == 0x7f) 1060 sram[SREG] |= SREG_V | SREG_S; 1061 else if (res & 0x80) 1062 sram[SREG] |= SREG_N | SREG_S; 1063 else if (res == 0) 1064 sram[SREG] |= SREG_Z; 1065 break; 1066 1067 case OP_lsr: 1068 case OP_asr: 1069 d = get_d (op); 1070 vd = sram[d]; 1071 res = (vd >> 1) | (vd & flash[ipc].r); 1072 sram[d] = res; 1073 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C); 1074 if (vd & 1) 1075 sram[SREG] |= SREG_C | SREG_S; 1076 if (res & 0x80) 1077 sram[SREG] |= SREG_N; 1078 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_C)) 1079 sram[SREG] |= SREG_V; 1080 if (res == 0) 1081 sram[SREG] |= SREG_Z; 1082 break; 1083 1084 case OP_ror: 1085 d = get_d (op); 1086 vd = sram[d]; 1087 res = vd >> 1 | (sram[SREG] << 7); 1088 sram[d] = res; 1089 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C); 1090 if (vd & 1) 1091 sram[SREG] |= SREG_C | SREG_S; 1092 if (res & 0x80) 1093 sram[SREG] |= SREG_N; 1094 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_C)) 1095 sram[SREG] |= SREG_V; 1096 if (res == 0) 1097 sram[SREG] |= SREG_Z; 1098 break; 1099 1100 case OP_mul: 1101 gen_mul (cpu, (word)sram[get_r (op)] * (word)sram[get_d (op)]); 1102 break; 1103 1104 case OP_muls: 1105 gen_mul (cpu, (sword)(sbyte)sram[get_r16 (op)] 1106 * (sword)(sbyte)sram[get_d16 (op)]); 1107 break; 1108 1109 case OP_mulsu: 1110 gen_mul (cpu, (sword)(word)sram[get_r16_23 (op)] 1111 * (sword)(sbyte)sram[get_d16_23 (op)]); 1112 break; 1113 1114 case OP_fmul: 1115 gen_mul (cpu, ((word)sram[get_r16_23 (op)] 1116 * (word)sram[get_d16_23 (op)]) << 1); 1117 break; 1118 1119 case OP_fmuls: 1120 gen_mul (cpu, ((sword)(sbyte)sram[get_r16_23 (op)] 1121 * (sword)(sbyte)sram[get_d16_23 (op)]) << 1); 1122 break; 1123 1124 case OP_fmulsu: 1125 gen_mul (cpu, ((sword)(word)sram[get_r16_23 (op)] 1126 * (sword)(sbyte)sram[get_d16_23 (op)]) << 1); 1127 break; 1128 1129 case OP_adc: 1130 case OP_add: 1131 r = sram[get_r (op)]; 1132 d = get_d (op); 1133 vd = sram[d]; 1134 res = r + vd + (sram[SREG] & flash[ipc].r); 1135 sram[d] = res; 1136 update_flags_add (res, vd, r); 1137 break; 1138 1139 case OP_sub: 1140 d = get_d (op); 1141 vd = sram[d]; 1142 r = sram[get_r (op)]; 1143 res = vd - r; 1144 sram[d] = res; 1145 update_flags_sub (res, vd, r); 1146 if (res == 0) 1147 sram[SREG] |= SREG_Z; 1148 break; 1149 1150 case OP_sbc: 1151 { 1152 byte old = sram[SREG]; 1153 d = get_d (op); 1154 vd = sram[d]; 1155 r = sram[get_r (op)]; 1156 res = vd - r - (old & SREG_C); 1157 sram[d] = res; 1158 update_flags_sub (res, vd, r); 1159 if (res == 0 && (old & SREG_Z)) 1160 sram[SREG] |= SREG_Z; 1161 } 1162 break; 1163 1164 case OP_subi: 1165 d = get_d16 (op); 1166 vd = sram[d]; 1167 r = get_K (op); 1168 res = vd - r; 1169 sram[d] = res; 1170 update_flags_sub (res, vd, r); 1171 if (res == 0) 1172 sram[SREG] |= SREG_Z; 1173 break; 1174 1175 case OP_sbci: 1176 { 1177 byte old = sram[SREG]; 1178 1179 d = get_d16 (op); 1180 vd = sram[d]; 1181 r = get_K (op); 1182 res = vd - r - (old & SREG_C); 1183 sram[d] = res; 1184 update_flags_sub (res, vd, r); 1185 if (res == 0 && (old & SREG_Z)) 1186 sram[SREG] |= SREG_Z; 1187 } 1188 break; 1189 1190 case OP_mov: 1191 sram[get_d (op)] = sram[get_r (op)]; 1192 break; 1193 1194 case OP_movw: 1195 d = (op & 0xf0) >> 3; 1196 r = (op & 0x0f) << 1; 1197 sram[d] = sram[r]; 1198 sram[d + 1] = sram[r + 1]; 1199 break; 1200 1201 case OP_out: 1202 d = get_A (op) + 0x20; 1203 res = sram[get_d (op)]; 1204 sram[d] = res; 1205 if (d == STDIO_PORT) 1206 putchar (res); 1207 else if (d == EXIT_PORT) 1208 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, cpu->pc, sim_exited, 0); 1209 else if (d == ABORT_PORT) 1210 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, cpu->pc, sim_exited, 1); 1211 break; 1212 1213 case OP_in: 1214 d = get_A (op) + 0x20; 1215 sram[get_d (op)] = sram[d]; 1216 break; 1217 1218 case OP_cbi: 1219 d = get_biA (op) + 0x20; 1220 sram[d] &= ~(1 << get_b(op)); 1221 break; 1222 1223 case OP_sbi: 1224 d = get_biA (op) + 0x20; 1225 sram[d] |= 1 << get_b(op); 1226 break; 1227 1228 case OP_sbic: 1229 if (!(sram[get_biA (op) + 0x20] & 1 << get_b(op))) 1230 { 1231 int l = get_insn_length (cpu->pc); 1232 cpu->pc += l; 1233 cpu->cycles += l; 1234 } 1235 break; 1236 1237 case OP_sbis: 1238 if (sram[get_biA (op) + 0x20] & 1 << get_b(op)) 1239 { 1240 int l = get_insn_length (cpu->pc); 1241 cpu->pc += l; 1242 cpu->cycles += l; 1243 } 1244 break; 1245 1246 case OP_ldi: 1247 res = get_K (op); 1248 d = get_d16 (op); 1249 sram[d] = res; 1250 break; 1251 1252 case OP_lds: 1253 sram[get_d (op)] = sram[flash[cpu->pc].op]; 1254 cpu->pc++; 1255 cpu->cycles++; 1256 break; 1257 1258 case OP_sts: 1259 sram[flash[cpu->pc].op] = sram[get_d (op)]; 1260 cpu->pc++; 1261 cpu->cycles++; 1262 break; 1263 1264 case OP_cpse: 1265 if (sram[get_r (op)] == sram[get_d (op)]) 1266 { 1267 int l = get_insn_length (cpu->pc); 1268 cpu->pc += l; 1269 cpu->cycles += l; 1270 } 1271 break; 1272 1273 case OP_cp: 1274 r = sram[get_r (op)]; 1275 d = sram[get_d (op)]; 1276 res = d - r; 1277 update_flags_sub (res, d, r); 1278 if (res == 0) 1279 sram[SREG] |= SREG_Z; 1280 break; 1281 1282 case OP_cpi: 1283 r = get_K (op); 1284 d = sram[get_d16 (op)]; 1285 res = d - r; 1286 update_flags_sub (res, d, r); 1287 if (res == 0) 1288 sram[SREG] |= SREG_Z; 1289 break; 1290 1291 case OP_cpc: 1292 { 1293 byte old = sram[SREG]; 1294 d = sram[get_d (op)]; 1295 r = sram[get_r (op)]; 1296 res = d - r - (old & SREG_C); 1297 update_flags_sub (res, d, r); 1298 if (res == 0 && (old & SREG_Z)) 1299 sram[SREG] |= SREG_Z; 1300 } 1301 break; 1302 1303 case OP_brbc: 1304 if (!(sram[SREG] & flash[ipc].r)) 1305 { 1306 cpu->pc = (cpu->pc + get_k (op)) & PC_MASK; 1307 cpu->cycles++; 1308 } 1309 break; 1310 1311 case OP_brbs: 1312 if (sram[SREG] & flash[ipc].r) 1313 { 1314 cpu->pc = (cpu->pc + get_k (op)) & PC_MASK; 1315 cpu->cycles++; 1316 } 1317 break; 1318 1319 case OP_lpm: 1320 sram[0] = get_lpm (read_word (REGZ)); 1321 cpu->cycles += 2; 1322 break; 1323 1324 case OP_lpm_Z: 1325 sram[get_d (op)] = get_lpm (read_word (REGZ)); 1326 cpu->cycles += 2; 1327 break; 1328 1329 case OP_lpm_inc_Z: 1330 sram[get_d (op)] = get_lpm (read_word_post_inc (REGZ)); 1331 cpu->cycles += 2; 1332 break; 1333 1334 case OP_elpm: 1335 sram[0] = get_lpm (get_z ()); 1336 cpu->cycles += 2; 1337 break; 1338 1339 case OP_elpm_Z: 1340 sram[get_d (op)] = get_lpm (get_z ()); 1341 cpu->cycles += 2; 1342 break; 1343 1344 case OP_elpm_inc_Z: 1345 { 1346 unsigned int z = get_z (); 1347 1348 sram[get_d (op)] = get_lpm (z); 1349 z++; 1350 sram[REGZ_LO] = z; 1351 sram[REGZ_HI] = z >> 8; 1352 sram[RAMPZ] = z >> 16; 1353 } 1354 cpu->cycles += 2; 1355 break; 1356 1357 case OP_ld_Z_inc: 1358 sram[get_d (op)] = sram[read_word_post_inc (REGZ) & SRAM_MASK]; 1359 cpu->cycles++; 1360 break; 1361 1362 case OP_ld_dec_Z: 1363 sram[get_d (op)] = sram[read_word_pre_dec (REGZ) & SRAM_MASK]; 1364 cpu->cycles++; 1365 break; 1366 1367 case OP_ld_X_inc: 1368 sram[get_d (op)] = sram[read_word_post_inc (REGX) & SRAM_MASK]; 1369 cpu->cycles++; 1370 break; 1371 1372 case OP_ld_dec_X: 1373 sram[get_d (op)] = sram[read_word_pre_dec (REGX) & SRAM_MASK]; 1374 cpu->cycles++; 1375 break; 1376 1377 case OP_ld_Y_inc: 1378 sram[get_d (op)] = sram[read_word_post_inc (REGY) & SRAM_MASK]; 1379 cpu->cycles++; 1380 break; 1381 1382 case OP_ld_dec_Y: 1383 sram[get_d (op)] = sram[read_word_pre_dec (REGY) & SRAM_MASK]; 1384 cpu->cycles++; 1385 break; 1386 1387 case OP_st_X: 1388 sram[read_word (REGX) & SRAM_MASK] = sram[get_d (op)]; 1389 cpu->cycles++; 1390 break; 1391 1392 case OP_st_X_inc: 1393 sram[read_word_post_inc (REGX) & SRAM_MASK] = sram[get_d (op)]; 1394 cpu->cycles++; 1395 break; 1396 1397 case OP_st_dec_X: 1398 sram[read_word_pre_dec (REGX) & SRAM_MASK] = sram[get_d (op)]; 1399 cpu->cycles++; 1400 break; 1401 1402 case OP_st_Z_inc: 1403 sram[read_word_post_inc (REGZ) & SRAM_MASK] = sram[get_d (op)]; 1404 cpu->cycles++; 1405 break; 1406 1407 case OP_st_dec_Z: 1408 sram[read_word_pre_dec (REGZ) & SRAM_MASK] = sram[get_d (op)]; 1409 cpu->cycles++; 1410 break; 1411 1412 case OP_st_Y_inc: 1413 sram[read_word_post_inc (REGY) & SRAM_MASK] = sram[get_d (op)]; 1414 cpu->cycles++; 1415 break; 1416 1417 case OP_st_dec_Y: 1418 sram[read_word_pre_dec (REGY) & SRAM_MASK] = sram[get_d (op)]; 1419 cpu->cycles++; 1420 break; 1421 1422 case OP_std_Y: 1423 sram[read_word (REGY) + flash[ipc].r] = sram[get_d (op)]; 1424 cpu->cycles++; 1425 break; 1426 1427 case OP_std_Z: 1428 sram[read_word (REGZ) + flash[ipc].r] = sram[get_d (op)]; 1429 cpu->cycles++; 1430 break; 1431 1432 case OP_ldd_Z: 1433 sram[get_d (op)] = sram[read_word (REGZ) + flash[ipc].r]; 1434 cpu->cycles++; 1435 break; 1436 1437 case OP_ldd_Y: 1438 sram[get_d (op)] = sram[read_word (REGY) + flash[ipc].r]; 1439 cpu->cycles++; 1440 break; 1441 1442 case OP_ld_X: 1443 sram[get_d (op)] = sram[read_word (REGX) & SRAM_MASK]; 1444 cpu->cycles++; 1445 break; 1446 1447 case OP_sbiw: 1448 { 1449 word wk = get_k6 (op); 1450 word wres; 1451 word wr; 1452 1453 d = get_d24 (op); 1454 wr = read_word (d); 1455 wres = wr - wk; 1456 1457 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C); 1458 if (wres == 0) 1459 sram[SREG] |= SREG_Z; 1460 if (wres & 0x8000) 1461 sram[SREG] |= SREG_N; 1462 if (wres & ~wr & 0x8000) 1463 sram[SREG] |= SREG_C; 1464 if (~wres & wr & 0x8000) 1465 sram[SREG] |= SREG_V; 1466 if (((~wres & wr) ^ wres) & 0x8000) 1467 sram[SREG] |= SREG_S; 1468 write_word (d, wres); 1469 } 1470 cpu->cycles++; 1471 break; 1472 1473 case OP_adiw: 1474 { 1475 word wk = get_k6 (op); 1476 word wres; 1477 word wr; 1478 1479 d = get_d24 (op); 1480 wr = read_word (d); 1481 wres = wr + wk; 1482 1483 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C); 1484 if (wres == 0) 1485 sram[SREG] |= SREG_Z; 1486 if (wres & 0x8000) 1487 sram[SREG] |= SREG_N; 1488 if (~wres & wr & 0x8000) 1489 sram[SREG] |= SREG_C; 1490 if (wres & ~wr & 0x8000) 1491 sram[SREG] |= SREG_V; 1492 if (((wres & ~wr) ^ wres) & 0x8000) 1493 sram[SREG] |= SREG_S; 1494 write_word (d, wres); 1495 } 1496 cpu->cycles++; 1497 break; 1498 1499 case OP_bad: 1500 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL); 1501 1502 default: 1503 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL); 1504 } 1505 } 1506 1507 void 1508 sim_engine_run (SIM_DESC sd, 1509 int next_cpu_nr, /* ignore */ 1510 int nr_cpus, /* ignore */ 1511 int siggnal) /* ignore */ 1512 { 1513 SIM_CPU *cpu; 1514 1515 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); 1516 1517 cpu = STATE_CPU (sd, 0); 1518 1519 while (1) 1520 { 1521 step_once (cpu); 1522 if (sim_events_tick (sd)) 1523 sim_events_process (sd); 1524 } 1525 } 1526 1527 int 1528 sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size) 1529 { 1530 int osize = size; 1531 1532 if (addr >= 0 && addr < SRAM_VADDR) 1533 { 1534 while (size > 0 && addr < (MAX_AVR_FLASH << 1)) 1535 { 1536 word val = flash[addr >> 1].op; 1537 1538 if (addr & 1) 1539 val = (val & 0xff) | (buffer[0] << 8); 1540 else 1541 val = (val & 0xff00) | buffer[0]; 1542 1543 flash[addr >> 1].op = val; 1544 flash[addr >> 1].code = OP_unknown; 1545 addr++; 1546 buffer++; 1547 size--; 1548 } 1549 return osize - size; 1550 } 1551 else if (addr >= SRAM_VADDR && addr < SRAM_VADDR + MAX_AVR_SRAM) 1552 { 1553 addr -= SRAM_VADDR; 1554 if (addr + size > MAX_AVR_SRAM) 1555 size = MAX_AVR_SRAM - addr; 1556 memcpy (sram + addr, buffer, size); 1557 return size; 1558 } 1559 else 1560 return 0; 1561 } 1562 1563 int 1564 sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size) 1565 { 1566 int osize = size; 1567 1568 if (addr >= 0 && addr < SRAM_VADDR) 1569 { 1570 while (size > 0 && addr < (MAX_AVR_FLASH << 1)) 1571 { 1572 word val = flash[addr >> 1].op; 1573 1574 if (addr & 1) 1575 val >>= 8; 1576 1577 *buffer++ = val; 1578 addr++; 1579 size--; 1580 } 1581 return osize - size; 1582 } 1583 else if (addr >= SRAM_VADDR && addr < SRAM_VADDR + MAX_AVR_SRAM) 1584 { 1585 addr -= SRAM_VADDR; 1586 if (addr + size > MAX_AVR_SRAM) 1587 size = MAX_AVR_SRAM - addr; 1588 memcpy (buffer, sram + addr, size); 1589 return size; 1590 } 1591 else 1592 { 1593 /* Avoid errors. */ 1594 memset (buffer, 0, size); 1595 return size; 1596 } 1597 } 1598 1599 static int 1600 avr_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length) 1601 { 1602 if (rn < 32 && length == 1) 1603 { 1604 sram[rn] = *memory; 1605 return 1; 1606 } 1607 if (rn == AVR_SREG_REGNUM && length == 1) 1608 { 1609 sram[SREG] = *memory; 1610 return 1; 1611 } 1612 if (rn == AVR_SP_REGNUM && length == 2) 1613 { 1614 sram[REG_SP] = memory[0]; 1615 sram[REG_SP + 1] = memory[1]; 1616 return 2; 1617 } 1618 if (rn == AVR_PC_REGNUM && length == 4) 1619 { 1620 cpu->pc = (memory[0] >> 1) | (memory[1] << 7) 1621 | (memory[2] << 15) | (memory[3] << 23); 1622 cpu->pc &= PC_MASK; 1623 return 4; 1624 } 1625 return 0; 1626 } 1627 1628 static int 1629 avr_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) 1630 { 1631 if (rn < 32 && length == 1) 1632 { 1633 *memory = sram[rn]; 1634 return 1; 1635 } 1636 if (rn == AVR_SREG_REGNUM && length == 1) 1637 { 1638 *memory = sram[SREG]; 1639 return 1; 1640 } 1641 if (rn == AVR_SP_REGNUM && length == 2) 1642 { 1643 memory[0] = sram[REG_SP]; 1644 memory[1] = sram[REG_SP + 1]; 1645 return 2; 1646 } 1647 if (rn == AVR_PC_REGNUM && length == 4) 1648 { 1649 memory[0] = cpu->pc << 1; 1650 memory[1] = cpu->pc >> 7; 1651 memory[2] = cpu->pc >> 15; 1652 memory[3] = cpu->pc >> 23; 1653 return 4; 1654 } 1655 return 0; 1656 } 1657 1658 static sim_cia 1659 avr_pc_get (sim_cpu *cpu) 1660 { 1661 return cpu->pc; 1662 } 1663 1664 static void 1665 avr_pc_set (sim_cpu *cpu, sim_cia pc) 1666 { 1667 cpu->pc = pc; 1668 } 1669 1670 static void 1671 free_state (SIM_DESC sd) 1672 { 1673 if (STATE_MODULES (sd) != NULL) 1674 sim_module_uninstall (sd); 1675 sim_cpu_free_all (sd); 1676 sim_state_free (sd); 1677 } 1678 1679 SIM_DESC 1680 sim_open (SIM_OPEN_KIND kind, host_callback *cb, 1681 struct bfd *abfd, char * const *argv) 1682 { 1683 int i; 1684 SIM_DESC sd = sim_state_alloc (kind, cb); 1685 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); 1686 1687 /* The cpu data is kept in a separately allocated chunk of memory. */ 1688 if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK) 1689 { 1690 free_state (sd); 1691 return 0; 1692 } 1693 1694 { 1695 /* XXX: Only first core gets profiled ? */ 1696 SIM_CPU *cpu = STATE_CPU (sd, 0); 1697 STATE_WATCHPOINTS (sd)->pc = &cpu->pc; 1698 STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (cpu->pc); 1699 } 1700 1701 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) 1702 { 1703 free_state (sd); 1704 return 0; 1705 } 1706 1707 /* The parser will print an error message for us, so we silently return. */ 1708 if (sim_parse_args (sd, argv) != SIM_RC_OK) 1709 { 1710 free_state (sd); 1711 return 0; 1712 } 1713 1714 /* Check for/establish the a reference program image. */ 1715 if (sim_analyze_program (sd, 1716 (STATE_PROG_ARGV (sd) != NULL 1717 ? *STATE_PROG_ARGV (sd) 1718 : NULL), abfd) != SIM_RC_OK) 1719 { 1720 free_state (sd); 1721 return 0; 1722 } 1723 1724 /* Configure/verify the target byte order and other runtime 1725 configuration options. */ 1726 if (sim_config (sd) != SIM_RC_OK) 1727 { 1728 sim_module_uninstall (sd); 1729 return 0; 1730 } 1731 1732 if (sim_post_argv_init (sd) != SIM_RC_OK) 1733 { 1734 /* Uninstall the modules to avoid memory leaks, 1735 file descriptor leaks, etc. */ 1736 sim_module_uninstall (sd); 1737 return 0; 1738 } 1739 1740 /* CPU specific initialization. */ 1741 for (i = 0; i < MAX_NR_PROCESSORS; ++i) 1742 { 1743 SIM_CPU *cpu = STATE_CPU (sd, i); 1744 1745 CPU_REG_FETCH (cpu) = avr_reg_fetch; 1746 CPU_REG_STORE (cpu) = avr_reg_store; 1747 CPU_PC_FETCH (cpu) = avr_pc_get; 1748 CPU_PC_STORE (cpu) = avr_pc_set; 1749 } 1750 1751 /* Clear all the memory. */ 1752 memset (sram, 0, sizeof (sram)); 1753 memset (flash, 0, sizeof (flash)); 1754 1755 return sd; 1756 } 1757 1758 SIM_RC 1759 sim_create_inferior (SIM_DESC sd, struct bfd *abfd, 1760 char * const *argv, char * const *env) 1761 { 1762 SIM_CPU *cpu = STATE_CPU (sd, 0); 1763 SIM_ADDR addr; 1764 1765 /* Set the PC. */ 1766 if (abfd != NULL) 1767 addr = bfd_get_start_address (abfd); 1768 else 1769 addr = 0; 1770 sim_pc_set (cpu, addr); 1771 1772 if (abfd != NULL) 1773 sd->avr_pc22 = (bfd_get_mach (abfd) >= bfd_mach_avr6); 1774 1775 return SIM_RC_OK; 1776 } 1777