xref: /netbsd-src/external/gpl3/gdb/dist/sim/arm/wrapper.c (revision b7b7574d3bf8eeb51a1fa3977b59142ec6434a55)
1 /* run front end support for arm
2    Copyright (C) 1995-2014 Free Software Foundation, Inc.
3 
4    This file is part of ARM SIM.
5 
6    This program is free software; you can redistribute it and/or modify
7    it under the terms of the GNU General Public License as published by
8    the Free Software Foundation; either version 3 of the License, or
9    (at your option) any later version.
10 
11    This program is distributed in the hope that it will be useful,
12    but WITHOUT ANY WARRANTY; without even the implied warranty of
13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14    GNU General Public License for more details.
15 
16    You should have received a copy of the GNU General Public License
17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
18 
19 /* This file provides the interface between the simulator and
20    run.c and gdb (when the simulator is linked with gdb).
21    All simulator interaction should go through this file.  */
22 
23 #include "config.h"
24 #include <stdio.h>
25 #include <stdarg.h>
26 #include <string.h>
27 #include <bfd.h>
28 #include <signal.h>
29 #include "gdb/callback.h"
30 #include "gdb/remote-sim.h"
31 #include "armdefs.h"
32 #include "armemu.h"
33 #include "dbg_rdi.h"
34 #include "ansidecl.h"
35 #include "sim-utils.h"
36 #include "run-sim.h"
37 #include "gdb/sim-arm.h"
38 #include "gdb/signals.h"
39 #include "libiberty.h"
40 
41 host_callback *sim_callback;
42 
43 static struct ARMul_State *state;
44 
45 /* Who is using the simulator.  */
46 static SIM_OPEN_KIND sim_kind;
47 
48 /* argv[0] */
49 static char *myname;
50 
51 /* Memory size in bytes.  */
52 static int mem_size = (1 << 21);
53 
54 /* Non-zero to display start up banner, and maybe other things.  */
55 static int verbosity;
56 
57 /* Non-zero to set big endian mode.  */
58 static int big_endian;
59 
60 int stop_simulator;
61 
62 /* Cirrus DSP registers.
63 
64    We need to define these registers outside of maverick.c because
65    maverick.c might not be linked in unless --target=arm9e-* in which
66    case wrapper.c will not compile because it tries to access Cirrus
67    registers.  This should all go away once we get the Cirrus and ARM
68    Coprocessor to coexist in armcopro.c-- aldyh.  */
69 
70 struct maverick_regs
71 {
72   union
73   {
74     int i;
75     float f;
76   } upper;
77 
78   union
79   {
80     int i;
81     float f;
82   } lower;
83 };
84 
85 union maverick_acc_regs
86 {
87   long double ld;		/* Acc registers are 72-bits.  */
88 };
89 
90 struct maverick_regs     DSPregs[16];
91 union maverick_acc_regs  DSPacc[4];
92 ARMword DSPsc;
93 
94 static void
95 init ()
96 {
97   static int done;
98 
99   if (!done)
100     {
101       ARMul_EmulateInit ();
102       state = ARMul_NewState ();
103       state->bigendSig = (big_endian ? HIGH : LOW);
104       ARMul_MemoryInit (state, mem_size);
105       ARMul_OSInit (state);
106       state->verbose = verbosity;
107       done = 1;
108     }
109 }
110 
111 /* Set verbosity level of simulator.
112    This is not intended to produce detailed tracing or debugging information.
113    Just summaries.  */
114 /* FIXME: common/run.c doesn't do this yet.  */
115 
116 void
117 sim_set_verbose (v)
118      int v;
119 {
120   verbosity = v;
121 }
122 
123 /* Set the memory size to SIZE bytes.
124    Must be called before initializing simulator.  */
125 /* FIXME: Rename to sim_set_mem_size.  */
126 
127 void
128 sim_size (size)
129      int size;
130 {
131   mem_size = size;
132 }
133 
134 void
135 ARMul_ConsolePrint (ARMul_State * state,
136 		    const char * format,
137 		    ...)
138 {
139   va_list ap;
140 
141   if (state->verbose)
142     {
143       va_start (ap, format);
144       vprintf (format, ap);
145       va_end (ap);
146     }
147 }
148 
149 ARMword
150 ARMul_Debug (state, pc, instr)
151      ARMul_State * state ATTRIBUTE_UNUSED;
152      ARMword       pc    ATTRIBUTE_UNUSED;
153      ARMword       instr ATTRIBUTE_UNUSED;
154 {
155   return 0;
156 }
157 
158 int
159 sim_write (sd, addr, buffer, size)
160      SIM_DESC sd ATTRIBUTE_UNUSED;
161      SIM_ADDR addr;
162      const unsigned char * buffer;
163      int size;
164 {
165   int i;
166 
167   init ();
168 
169   for (i = 0; i < size; i++)
170     ARMul_SafeWriteByte (state, addr + i, buffer[i]);
171 
172   return size;
173 }
174 
175 int
176 sim_read (sd, addr, buffer, size)
177      SIM_DESC sd ATTRIBUTE_UNUSED;
178      SIM_ADDR addr;
179      unsigned char * buffer;
180      int size;
181 {
182   int i;
183 
184   init ();
185 
186   for (i = 0; i < size; i++)
187     buffer[i] = ARMul_SafeReadByte (state, addr + i);
188 
189   return size;
190 }
191 
192 int
193 sim_trace (sd)
194      SIM_DESC sd ATTRIBUTE_UNUSED;
195 {
196   (*sim_callback->printf_filtered)
197     (sim_callback,
198      "This simulator does not support tracing\n");
199   return 1;
200 }
201 
202 int
203 sim_stop (sd)
204      SIM_DESC sd ATTRIBUTE_UNUSED;
205 {
206   state->Emulate = STOP;
207   stop_simulator = 1;
208   return 1;
209 }
210 
211 void
212 sim_resume (sd, step, siggnal)
213      SIM_DESC sd ATTRIBUTE_UNUSED;
214      int step;
215      int siggnal ATTRIBUTE_UNUSED;
216 {
217   state->EndCondition = 0;
218   stop_simulator = 0;
219 
220   if (step)
221     {
222       state->Reg[15] = ARMul_DoInstr (state);
223       if (state->EndCondition == 0)
224 	state->EndCondition = RDIError_BreakpointReached;
225     }
226   else
227     {
228       state->NextInstr = RESUME;	/* treat as PC change */
229       state->Reg[15] = ARMul_DoProg (state);
230     }
231 
232   FLUSHPIPE;
233 }
234 
235 SIM_RC
236 sim_create_inferior (sd, abfd, argv, env)
237      SIM_DESC sd ATTRIBUTE_UNUSED;
238      struct bfd * abfd;
239      char ** argv;
240      char ** env;
241 {
242   int argvlen = 0;
243   int mach;
244   char **arg;
245 
246   init ();
247 
248   if (abfd != NULL)
249     {
250       ARMul_SetPC (state, bfd_get_start_address (abfd));
251       mach = bfd_get_mach (abfd);
252     }
253   else
254     {
255       ARMul_SetPC (state, 0);	/* ??? */
256       mach = 0;
257     }
258 
259   switch (mach)
260     {
261     default:
262       (*sim_callback->printf_filtered)
263 	(sim_callback,
264 	 "Unknown machine type '%d'; please update sim_create_inferior.\n",
265 	 mach);
266       /* fall through */
267 
268     case 0:
269       /* We wouldn't set the machine type with earlier toolchains, so we
270 	 explicitly select a processor capable of supporting all ARMs in
271 	 32bit mode.  */
272       /* We choose the XScale rather than the iWMMXt, because the iWMMXt
273 	 removes the FPE emulator, since it conflicts with its coprocessors.
274 	 For the most generic ARM support, we want the FPE emulator in place.  */
275     case bfd_mach_arm_XScale:
276       ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_v6_Prop);
277       break;
278 
279     case bfd_mach_arm_iWMMXt2:
280     case bfd_mach_arm_iWMMXt:
281       {
282 	extern int SWI_vector_installed;
283 	ARMword i;
284 
285 	if (! SWI_vector_installed)
286 	  {
287 	    /* Intialise the hardware vectors to zero.  */
288 	    if (! SWI_vector_installed)
289 	      for (i = ARMul_ResetV; i <= ARMFIQV; i += 4)
290 		ARMul_WriteWord (state, i, 0);
291 
292 	    /* ARM_WriteWord will have detected the write to the SWI vector,
293 	       but we want SWI_vector_installed to remain at 0 so that thumb
294 	       mode breakpoints will work.  */
295 	    SWI_vector_installed = 0;
296 	  }
297       }
298       ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_iWMMXt_Prop);
299       break;
300 
301     case bfd_mach_arm_ep9312:
302       ARMul_SelectProcessor (state, ARM_v4_Prop | ARM_ep9312_Prop);
303       break;
304 
305     case bfd_mach_arm_5:
306       if (bfd_family_coff (abfd))
307 	{
308 	  /* This is a special case in order to support COFF based ARM toolchains.
309 	     The COFF header does not have enough room to store all the different
310 	     kinds of ARM cpu, so the XScale, v5T and v5TE architectures all default
311 	     to v5.  (See coff_set_flags() in bdf/coffcode.h).  So if we see a v5
312 	     machine type here, we assume it could be any of the above architectures
313 	     and so select the most feature-full.  */
314 	  ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop);
315 	  break;
316 	}
317       /* Otherwise drop through.  */
318 
319     case bfd_mach_arm_5T:
320       ARMul_SelectProcessor (state, ARM_v5_Prop);
321       break;
322 
323     case bfd_mach_arm_5TE:
324       ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop);
325       break;
326 
327     case bfd_mach_arm_4:
328     case bfd_mach_arm_4T:
329       ARMul_SelectProcessor (state, ARM_v4_Prop);
330       break;
331 
332     case bfd_mach_arm_3:
333     case bfd_mach_arm_3M:
334       ARMul_SelectProcessor (state, ARM_Lock_Prop);
335       break;
336 
337     case bfd_mach_arm_2:
338     case bfd_mach_arm_2a:
339       ARMul_SelectProcessor (state, ARM_Fix26_Prop);
340       break;
341     }
342 
343   if (   mach != bfd_mach_arm_3
344       && mach != bfd_mach_arm_3M
345       && mach != bfd_mach_arm_2
346       && mach != bfd_mach_arm_2a)
347     {
348       /* Reset mode to ARM.  A gdb user may rerun a program that had entered
349 	 THUMB mode from the start and cause the ARM-mode startup code to be
350 	 executed in THUMB mode.  */
351       ARMul_SetCPSR (state, SVC32MODE);
352     }
353 
354   if (argv != NULL)
355     {
356       /* Set up the command line by laboriously stringing together
357 	 the environment carefully picked apart by our caller.  */
358 
359       /* Free any old stuff.  */
360       if (state->CommandLine != NULL)
361 	{
362 	  free (state->CommandLine);
363 	  state->CommandLine = NULL;
364 	}
365 
366       /* See how much we need.  */
367       for (arg = argv; *arg != NULL; arg++)
368 	argvlen += strlen (*arg) + 1;
369 
370       /* Allocate it.  */
371       state->CommandLine = malloc (argvlen + 1);
372       if (state->CommandLine != NULL)
373 	{
374 	  arg = argv;
375 	  state->CommandLine[0] = '\0';
376 
377 	  for (arg = argv; *arg != NULL; arg++)
378 	    {
379 	      strcat (state->CommandLine, *arg);
380 	      strcat (state->CommandLine, " ");
381 	    }
382 	}
383     }
384 
385   if (env != NULL)
386     {
387       /* Now see if there's a MEMSIZE spec in the environment.  */
388       while (*env)
389 	{
390 	  if (strncmp (*env, "MEMSIZE=", sizeof ("MEMSIZE=") - 1) == 0)
391 	    {
392 	      char *end_of_num;
393 
394 	      /* Set up memory limit.  */
395 	      state->MemSize =
396 		strtoul (*env + sizeof ("MEMSIZE=") - 1, &end_of_num, 0);
397 	    }
398 	  env++;
399 	}
400     }
401 
402   return SIM_RC_OK;
403 }
404 
405 void
406 sim_info (sd, verbose)
407      SIM_DESC sd ATTRIBUTE_UNUSED;
408      int verbose ATTRIBUTE_UNUSED;
409 {
410 }
411 
412 static int
413 frommem (state, memory)
414      struct ARMul_State *state;
415      unsigned char *memory;
416 {
417   if (state->bigendSig == HIGH)
418     return (memory[0] << 24) | (memory[1] << 16)
419       | (memory[2] << 8) | (memory[3] << 0);
420   else
421     return (memory[3] << 24) | (memory[2] << 16)
422       | (memory[1] << 8) | (memory[0] << 0);
423 }
424 
425 static void
426 tomem (state, memory, val)
427      struct ARMul_State *state;
428      unsigned char *memory;
429      int val;
430 {
431   if (state->bigendSig == HIGH)
432     {
433       memory[0] = val >> 24;
434       memory[1] = val >> 16;
435       memory[2] = val >> 8;
436       memory[3] = val >> 0;
437     }
438   else
439     {
440       memory[3] = val >> 24;
441       memory[2] = val >> 16;
442       memory[1] = val >> 8;
443       memory[0] = val >> 0;
444     }
445 }
446 
447 int
448 sim_store_register (sd, rn, memory, length)
449      SIM_DESC sd ATTRIBUTE_UNUSED;
450      int rn;
451      unsigned char *memory;
452      int length;
453 {
454   init ();
455 
456   switch ((enum sim_arm_regs) rn)
457     {
458     case SIM_ARM_R0_REGNUM:
459     case SIM_ARM_R1_REGNUM:
460     case SIM_ARM_R2_REGNUM:
461     case SIM_ARM_R3_REGNUM:
462     case SIM_ARM_R4_REGNUM:
463     case SIM_ARM_R5_REGNUM:
464     case SIM_ARM_R6_REGNUM:
465     case SIM_ARM_R7_REGNUM:
466     case SIM_ARM_R8_REGNUM:
467     case SIM_ARM_R9_REGNUM:
468     case SIM_ARM_R10_REGNUM:
469     case SIM_ARM_R11_REGNUM:
470     case SIM_ARM_R12_REGNUM:
471     case SIM_ARM_R13_REGNUM:
472     case SIM_ARM_R14_REGNUM:
473     case SIM_ARM_R15_REGNUM: /* PC */
474     case SIM_ARM_FP0_REGNUM:
475     case SIM_ARM_FP1_REGNUM:
476     case SIM_ARM_FP2_REGNUM:
477     case SIM_ARM_FP3_REGNUM:
478     case SIM_ARM_FP4_REGNUM:
479     case SIM_ARM_FP5_REGNUM:
480     case SIM_ARM_FP6_REGNUM:
481     case SIM_ARM_FP7_REGNUM:
482     case SIM_ARM_FPS_REGNUM:
483       ARMul_SetReg (state, state->Mode, rn, frommem (state, memory));
484       break;
485 
486     case SIM_ARM_PS_REGNUM:
487       state->Cpsr = frommem (state, memory);
488       ARMul_CPSRAltered (state);
489       break;
490 
491     case SIM_ARM_MAVERIC_COP0R0_REGNUM:
492     case SIM_ARM_MAVERIC_COP0R1_REGNUM:
493     case SIM_ARM_MAVERIC_COP0R2_REGNUM:
494     case SIM_ARM_MAVERIC_COP0R3_REGNUM:
495     case SIM_ARM_MAVERIC_COP0R4_REGNUM:
496     case SIM_ARM_MAVERIC_COP0R5_REGNUM:
497     case SIM_ARM_MAVERIC_COP0R6_REGNUM:
498     case SIM_ARM_MAVERIC_COP0R7_REGNUM:
499     case SIM_ARM_MAVERIC_COP0R8_REGNUM:
500     case SIM_ARM_MAVERIC_COP0R9_REGNUM:
501     case SIM_ARM_MAVERIC_COP0R10_REGNUM:
502     case SIM_ARM_MAVERIC_COP0R11_REGNUM:
503     case SIM_ARM_MAVERIC_COP0R12_REGNUM:
504     case SIM_ARM_MAVERIC_COP0R13_REGNUM:
505     case SIM_ARM_MAVERIC_COP0R14_REGNUM:
506     case SIM_ARM_MAVERIC_COP0R15_REGNUM:
507       memcpy (& DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM],
508 	      memory, sizeof (struct maverick_regs));
509       return sizeof (struct maverick_regs);
510 
511     case SIM_ARM_MAVERIC_DSPSC_REGNUM:
512       memcpy (&DSPsc, memory, sizeof DSPsc);
513       return sizeof DSPsc;
514 
515     case SIM_ARM_IWMMXT_COP0R0_REGNUM:
516     case SIM_ARM_IWMMXT_COP0R1_REGNUM:
517     case SIM_ARM_IWMMXT_COP0R2_REGNUM:
518     case SIM_ARM_IWMMXT_COP0R3_REGNUM:
519     case SIM_ARM_IWMMXT_COP0R4_REGNUM:
520     case SIM_ARM_IWMMXT_COP0R5_REGNUM:
521     case SIM_ARM_IWMMXT_COP0R6_REGNUM:
522     case SIM_ARM_IWMMXT_COP0R7_REGNUM:
523     case SIM_ARM_IWMMXT_COP0R8_REGNUM:
524     case SIM_ARM_IWMMXT_COP0R9_REGNUM:
525     case SIM_ARM_IWMMXT_COP0R10_REGNUM:
526     case SIM_ARM_IWMMXT_COP0R11_REGNUM:
527     case SIM_ARM_IWMMXT_COP0R12_REGNUM:
528     case SIM_ARM_IWMMXT_COP0R13_REGNUM:
529     case SIM_ARM_IWMMXT_COP0R14_REGNUM:
530     case SIM_ARM_IWMMXT_COP0R15_REGNUM:
531     case SIM_ARM_IWMMXT_COP1R0_REGNUM:
532     case SIM_ARM_IWMMXT_COP1R1_REGNUM:
533     case SIM_ARM_IWMMXT_COP1R2_REGNUM:
534     case SIM_ARM_IWMMXT_COP1R3_REGNUM:
535     case SIM_ARM_IWMMXT_COP1R4_REGNUM:
536     case SIM_ARM_IWMMXT_COP1R5_REGNUM:
537     case SIM_ARM_IWMMXT_COP1R6_REGNUM:
538     case SIM_ARM_IWMMXT_COP1R7_REGNUM:
539     case SIM_ARM_IWMMXT_COP1R8_REGNUM:
540     case SIM_ARM_IWMMXT_COP1R9_REGNUM:
541     case SIM_ARM_IWMMXT_COP1R10_REGNUM:
542     case SIM_ARM_IWMMXT_COP1R11_REGNUM:
543     case SIM_ARM_IWMMXT_COP1R12_REGNUM:
544     case SIM_ARM_IWMMXT_COP1R13_REGNUM:
545     case SIM_ARM_IWMMXT_COP1R14_REGNUM:
546     case SIM_ARM_IWMMXT_COP1R15_REGNUM:
547       return Store_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory);
548 
549     default:
550       return 0;
551     }
552 
553   return length;
554 }
555 
556 int
557 sim_fetch_register (sd, rn, memory, length)
558      SIM_DESC sd ATTRIBUTE_UNUSED;
559      int rn;
560      unsigned char *memory;
561      int length;
562 {
563   ARMword regval;
564   int len = length;
565 
566   init ();
567 
568   switch ((enum sim_arm_regs) rn)
569     {
570     case SIM_ARM_R0_REGNUM:
571     case SIM_ARM_R1_REGNUM:
572     case SIM_ARM_R2_REGNUM:
573     case SIM_ARM_R3_REGNUM:
574     case SIM_ARM_R4_REGNUM:
575     case SIM_ARM_R5_REGNUM:
576     case SIM_ARM_R6_REGNUM:
577     case SIM_ARM_R7_REGNUM:
578     case SIM_ARM_R8_REGNUM:
579     case SIM_ARM_R9_REGNUM:
580     case SIM_ARM_R10_REGNUM:
581     case SIM_ARM_R11_REGNUM:
582     case SIM_ARM_R12_REGNUM:
583     case SIM_ARM_R13_REGNUM:
584     case SIM_ARM_R14_REGNUM:
585     case SIM_ARM_R15_REGNUM: /* PC */
586       regval = ARMul_GetReg (state, state->Mode, rn);
587       break;
588 
589     case SIM_ARM_FP0_REGNUM:
590     case SIM_ARM_FP1_REGNUM:
591     case SIM_ARM_FP2_REGNUM:
592     case SIM_ARM_FP3_REGNUM:
593     case SIM_ARM_FP4_REGNUM:
594     case SIM_ARM_FP5_REGNUM:
595     case SIM_ARM_FP6_REGNUM:
596     case SIM_ARM_FP7_REGNUM:
597     case SIM_ARM_FPS_REGNUM:
598       memset (memory, 0, length);
599       return 0;
600 
601     case SIM_ARM_PS_REGNUM:
602       regval = ARMul_GetCPSR (state);
603       break;
604 
605     case SIM_ARM_MAVERIC_COP0R0_REGNUM:
606     case SIM_ARM_MAVERIC_COP0R1_REGNUM:
607     case SIM_ARM_MAVERIC_COP0R2_REGNUM:
608     case SIM_ARM_MAVERIC_COP0R3_REGNUM:
609     case SIM_ARM_MAVERIC_COP0R4_REGNUM:
610     case SIM_ARM_MAVERIC_COP0R5_REGNUM:
611     case SIM_ARM_MAVERIC_COP0R6_REGNUM:
612     case SIM_ARM_MAVERIC_COP0R7_REGNUM:
613     case SIM_ARM_MAVERIC_COP0R8_REGNUM:
614     case SIM_ARM_MAVERIC_COP0R9_REGNUM:
615     case SIM_ARM_MAVERIC_COP0R10_REGNUM:
616     case SIM_ARM_MAVERIC_COP0R11_REGNUM:
617     case SIM_ARM_MAVERIC_COP0R12_REGNUM:
618     case SIM_ARM_MAVERIC_COP0R13_REGNUM:
619     case SIM_ARM_MAVERIC_COP0R14_REGNUM:
620     case SIM_ARM_MAVERIC_COP0R15_REGNUM:
621       memcpy (memory, & DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM],
622 	      sizeof (struct maverick_regs));
623       return sizeof (struct maverick_regs);
624 
625     case SIM_ARM_MAVERIC_DSPSC_REGNUM:
626       memcpy (memory, & DSPsc, sizeof DSPsc);
627       return sizeof DSPsc;
628 
629     case SIM_ARM_IWMMXT_COP0R0_REGNUM:
630     case SIM_ARM_IWMMXT_COP0R1_REGNUM:
631     case SIM_ARM_IWMMXT_COP0R2_REGNUM:
632     case SIM_ARM_IWMMXT_COP0R3_REGNUM:
633     case SIM_ARM_IWMMXT_COP0R4_REGNUM:
634     case SIM_ARM_IWMMXT_COP0R5_REGNUM:
635     case SIM_ARM_IWMMXT_COP0R6_REGNUM:
636     case SIM_ARM_IWMMXT_COP0R7_REGNUM:
637     case SIM_ARM_IWMMXT_COP0R8_REGNUM:
638     case SIM_ARM_IWMMXT_COP0R9_REGNUM:
639     case SIM_ARM_IWMMXT_COP0R10_REGNUM:
640     case SIM_ARM_IWMMXT_COP0R11_REGNUM:
641     case SIM_ARM_IWMMXT_COP0R12_REGNUM:
642     case SIM_ARM_IWMMXT_COP0R13_REGNUM:
643     case SIM_ARM_IWMMXT_COP0R14_REGNUM:
644     case SIM_ARM_IWMMXT_COP0R15_REGNUM:
645     case SIM_ARM_IWMMXT_COP1R0_REGNUM:
646     case SIM_ARM_IWMMXT_COP1R1_REGNUM:
647     case SIM_ARM_IWMMXT_COP1R2_REGNUM:
648     case SIM_ARM_IWMMXT_COP1R3_REGNUM:
649     case SIM_ARM_IWMMXT_COP1R4_REGNUM:
650     case SIM_ARM_IWMMXT_COP1R5_REGNUM:
651     case SIM_ARM_IWMMXT_COP1R6_REGNUM:
652     case SIM_ARM_IWMMXT_COP1R7_REGNUM:
653     case SIM_ARM_IWMMXT_COP1R8_REGNUM:
654     case SIM_ARM_IWMMXT_COP1R9_REGNUM:
655     case SIM_ARM_IWMMXT_COP1R10_REGNUM:
656     case SIM_ARM_IWMMXT_COP1R11_REGNUM:
657     case SIM_ARM_IWMMXT_COP1R12_REGNUM:
658     case SIM_ARM_IWMMXT_COP1R13_REGNUM:
659     case SIM_ARM_IWMMXT_COP1R14_REGNUM:
660     case SIM_ARM_IWMMXT_COP1R15_REGNUM:
661       return Fetch_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory);
662 
663     default:
664       return 0;
665     }
666 
667   while (len)
668     {
669       tomem (state, memory, regval);
670 
671       len -= 4;
672       memory += 4;
673       regval = 0;
674     }
675 
676   return length;
677 }
678 
679 #ifdef SIM_TARGET_SWITCHES
680 
681 static void sim_target_parse_arg_array (char **);
682 
683 typedef struct
684 {
685   char * 	swi_option;
686   unsigned int	swi_mask;
687 } swi_options;
688 
689 #define SWI_SWITCH	"--swi-support"
690 
691 static swi_options options[] =
692   {
693     { "none",    0 },
694     { "demon",   SWI_MASK_DEMON },
695     { "angel",   SWI_MASK_ANGEL },
696     { "redboot", SWI_MASK_REDBOOT },
697     { "all",     -1 },
698     { "NONE",    0 },
699     { "DEMON",   SWI_MASK_DEMON },
700     { "ANGEL",   SWI_MASK_ANGEL },
701     { "REDBOOT", SWI_MASK_REDBOOT },
702     { "ALL",     -1 }
703   };
704 
705 
706 int
707 sim_target_parse_command_line (argc, argv)
708      int argc;
709      char ** argv;
710 {
711   int i;
712 
713   for (i = 1; i < argc; i++)
714     {
715       char * ptr = argv[i];
716       int arg;
717 
718       if ((ptr == NULL) || (* ptr != '-'))
719 	break;
720 
721       if (strncmp (ptr, SWI_SWITCH, sizeof SWI_SWITCH - 1) != 0)
722 	continue;
723 
724       if (ptr[sizeof SWI_SWITCH - 1] == 0)
725 	{
726 	  /* Remove this option from the argv array.  */
727 	  for (arg = i; arg < argc; arg ++)
728 	    argv[arg] = argv[arg + 1];
729 	  argc --;
730 
731 	  ptr = argv[i];
732 	}
733       else
734 	ptr += sizeof SWI_SWITCH;
735 
736       swi_mask = 0;
737 
738       while (* ptr)
739 	{
740 	  int i;
741 
742 	  for (i = sizeof options / sizeof options[0]; i--;)
743 	    if (strncmp (ptr, options[i].swi_option,
744 			 strlen (options[i].swi_option)) == 0)
745 	      {
746 		swi_mask |= options[i].swi_mask;
747 		ptr += strlen (options[i].swi_option);
748 
749 		if (* ptr == ',')
750 		  ++ ptr;
751 
752 		break;
753 	      }
754 
755 	  if (i < 0)
756 	    break;
757 	}
758 
759       if (* ptr != 0)
760 	fprintf (stderr, "Ignoring swi options: %s\n", ptr);
761 
762       /* Remove this option from the argv array.  */
763       for (arg = i; arg < argc; arg ++)
764 	argv[arg] = argv[arg + 1];
765       argc --;
766       i --;
767     }
768   return argc;
769 }
770 
771 static void
772 sim_target_parse_arg_array (argv)
773      char ** argv;
774 {
775   int i;
776 
777   for (i = 0; argv[i]; i++)
778     ;
779 
780   sim_target_parse_command_line (i, argv);
781 }
782 
783 void
784 sim_target_display_usage (help)
785      int help;
786 {
787   FILE *stream = help ? stdout : stderr;
788 
789   fprintf (stream, "%s=<list>  Comma seperated list of SWI protocols to supoport.\n\
790                 This list can contain: NONE, DEMON, ANGEL, REDBOOT and/or ALL.\n",
791 	   SWI_SWITCH);
792 }
793 #endif
794 
795 SIM_DESC
796 sim_open (kind, ptr, abfd, argv)
797      SIM_OPEN_KIND kind;
798      host_callback *ptr;
799      struct bfd *abfd;
800      char **argv;
801 {
802   sim_kind = kind;
803   if (myname) free (myname);
804   myname = (char *) xstrdup (argv[0]);
805   sim_callback = ptr;
806 
807 #ifdef SIM_TARGET_SWITCHES
808   sim_target_parse_arg_array (argv);
809 #endif
810 
811   /* Decide upon the endian-ness of the processor.
812      If we can, get the information from the bfd itself.
813      Otherwise look to see if we have been given a command
814      line switch that tells us.  Otherwise default to little endian.  */
815   if (abfd != NULL)
816     big_endian = bfd_big_endian (abfd);
817   else if (argv[1] != NULL)
818     {
819       int i;
820 
821       /* Scan for endian-ness and memory-size switches.  */
822       for (i = 0; (argv[i] != NULL) && (argv[i][0] != 0); i++)
823 	if (argv[i][0] == '-' && argv[i][1] == 'E')
824 	  {
825 	    char c;
826 
827 	    if ((c = argv[i][2]) == 0)
828 	      {
829 		++i;
830 		c = argv[i][0];
831 	      }
832 
833 	    switch (c)
834 	      {
835 	      case 0:
836 		sim_callback->printf_filtered
837 		  (sim_callback, "No argument to -E option provided\n");
838 		break;
839 
840 	      case 'b':
841 	      case 'B':
842 		big_endian = 1;
843 		break;
844 
845 	      case 'l':
846 	      case 'L':
847 		big_endian = 0;
848 		break;
849 
850 	      default:
851 		sim_callback->printf_filtered
852 		  (sim_callback, "Unrecognised argument to -E option\n");
853 		break;
854 	      }
855 	  }
856 	else if (argv[i][0] == '-' && argv[i][1] == 'm')
857 	  {
858 	    if (argv[i][2] != '\0')
859 	      sim_size (atoi (&argv[i][2]));
860 	    else if (argv[i + 1] != NULL)
861 	      {
862 		sim_size (atoi (argv[i + 1]));
863 		i++;
864 	      }
865 	    else
866 	      {
867 		sim_callback->printf_filtered (sim_callback,
868 					       "Missing argument to -m option\n");
869 		return NULL;
870 	      }
871 
872 	  }
873     }
874 
875   return (SIM_DESC) 1;
876 }
877 
878 void
879 sim_close (sd, quitting)
880      SIM_DESC sd ATTRIBUTE_UNUSED;
881      int quitting ATTRIBUTE_UNUSED;
882 {
883   if (myname)
884     free (myname);
885   myname = NULL;
886 }
887 
888 SIM_RC
889 sim_load (sd, prog, abfd, from_tty)
890      SIM_DESC sd;
891      char *prog;
892      bfd *abfd;
893      int from_tty ATTRIBUTE_UNUSED;
894 {
895   bfd *prog_bfd;
896 
897   prog_bfd = sim_load_file (sd, myname, sim_callback, prog, abfd,
898 			    sim_kind == SIM_OPEN_DEBUG, 0, sim_write);
899   if (prog_bfd == NULL)
900     return SIM_RC_FAIL;
901   ARMul_SetPC (state, bfd_get_start_address (prog_bfd));
902   if (abfd == NULL)
903     bfd_close (prog_bfd);
904   return SIM_RC_OK;
905 }
906 
907 void
908 sim_stop_reason (sd, reason, sigrc)
909      SIM_DESC sd ATTRIBUTE_UNUSED;
910      enum sim_stop *reason;
911      int *sigrc;
912 {
913   if (stop_simulator)
914     {
915       *reason = sim_stopped;
916       *sigrc = GDB_SIGNAL_INT;
917     }
918   else if (state->EndCondition == 0)
919     {
920       *reason = sim_exited;
921       *sigrc = state->Reg[0] & 255;
922     }
923   else
924     {
925       *reason = sim_stopped;
926       if (state->EndCondition == RDIError_BreakpointReached)
927 	*sigrc = GDB_SIGNAL_TRAP;
928       else if (   state->EndCondition == RDIError_DataAbort
929 	       || state->EndCondition == RDIError_AddressException)
930 	*sigrc = GDB_SIGNAL_BUS;
931       else
932 	*sigrc = 0;
933     }
934 }
935 
936 void
937 sim_do_command (sd, cmd)
938      SIM_DESC sd ATTRIBUTE_UNUSED;
939      char *cmd ATTRIBUTE_UNUSED;
940 {
941   (*sim_callback->printf_filtered)
942     (sim_callback,
943      "This simulator does not accept any commands.\n");
944 }
945 
946 void
947 sim_set_callbacks (ptr)
948      host_callback *ptr;
949 {
950   sim_callback = ptr;
951 }
952 
953 char **
954 sim_complete_command (SIM_DESC sd, const char *text, const char *word)
955 {
956   return NULL;
957 }
958